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Whitespace fixes for files in sys/mips/nlm

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Clean up whitespace issues under sys/mips/nlm (except dev). No
functional change in this commit.
This commit is contained in:
Jayachandran C. 2015-02-28 00:17:29 +00:00
parent 3a6a9a3bcc
commit 72e64728c9
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=279387
31 changed files with 191 additions and 190 deletions
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10
sys/mips/nlm/board.c
View File

@ -71,7 +71,7 @@ static struct vfbid_tbl nlm_vfbid[] = {
{43, 1011}, {42, 1010}, {41, 1009}, {40, 1008},
{39, 1007}, {38, 1006}, {37, 1005}, {36, 1004},
{35, 1003}, {34, 1002}, {33, 1001}, {32, 1000},
/* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
/* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
{31, 127}, {30, 123}, {29, 119}, {28, 115},
{27, 111}, {26, 107}, {25, 103}, {24, 99},
{23, 95}, {22, 91}, {21, 87}, {20, 83},
@ -87,7 +87,7 @@ static struct vfbid_tbl nlm3xx_vfbid[] = {
{127, 0}, /* NAE <-> NAE mappings */
{39, 503}, {38, 502}, {37, 501}, {36, 500},
{35, 499}, {34, 498}, {33, 497}, {32, 496},
/* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
/* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
{31, 127}, {30, 123}, {29, 119}, {28, 115},
{27, 111}, {26, 107}, {25, 103}, {24, 99},
{23, 95}, {22, 91}, {21, 87}, {20, 83},
@ -240,7 +240,7 @@ nlm_setup_port_defaults(struct xlp_port_ivars *p)
/* XLP 8XX evaluation boards have the following phy-addr
* assignment. There are two external mdio buses in XLP --
* bus 0 and bus 1. The management ports (16 and 17) are
* on mdio bus 0 while blocks/complexes[0 to 3] are all
* on mdio bus 0 while blocks/complexes[0 to 3] are all
* on mdio bus 1. The phy_addr on bus 0 (mgmt ports 16
* and 17) match the port numbers.
* These are the details:
@ -263,7 +263,7 @@ nlm_setup_port_defaults(struct xlp_port_ivars *p)
* 3 2 14 1
* 3 3 13 1
*
* 4 0 16 0
* 4 0 16 0
* 4 1 17 0
*
* The XLP 3XX evaluation boards have the following phy-addr
@ -366,7 +366,7 @@ nlm_print_processor_info(void)
}
/*
* All our knowledge of chip and board that cannot be detected by probing
* All our knowledge of chip and board that cannot be detected by probing
* at run-time goes here
*/
static int

6
sys/mips/nlm/board.h
View File

@ -5,7 +5,7 @@
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
@ -40,7 +40,7 @@
*/
#define EEPROM_I2CBUS 1
#define EEPROM_I2CADDR 0xAE
#define EEPROM_SIZE 48
#define EEPROM_SIZE 48
#define EEPROM_MACADDR_OFFSET 2
/* used if there is no FDT */
@ -113,7 +113,7 @@ struct xlp_block_ivars {
};
struct xlp_nae_ivars {
int node;
int node;
int nblocks;
u_int blockmask;
u_int ilmask;

2
sys/mips/nlm/board_cpld.c
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

6
sys/mips/nlm/board_eeprom.c
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -78,7 +78,7 @@ oc_rd_cmd(uint8_t cmd)
data = oc_read_reg(OC_I2C_DATA_REG);
return (data);
}
static int
oc_wr_cmd(uint8_t data, uint8_t cmd)
{
@ -142,7 +142,7 @@ nlm_board_eeprom_read(int node, int bus, int addr, int offs, uint8_t *buf,
err = "No ack after read start";
goto err_exit_stop;
}
for (i = 0; i < sz - 1; i++) {
if ((rd = oc_rd_cmd(OC_COMMAND_READ)) < 0) {
err = "I2C read data byte failed.";

81
sys/mips/nlm/bus_space_rmi_pci.c
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
@ -46,199 +46,202 @@ __FBSDID("$FreeBSD$");
#include <machine/bus.h>
#include <machine/cache.h>
static int
static int
rmi_pci_bus_space_map(void *t, bus_addr_t addr,
bus_size_t size, int flags,
bus_space_handle_t * bshp);
static void
static void
rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh,
bus_size_t size);
static int
static int
rmi_pci_bus_space_subregion(void *t,
bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size,
bus_space_handle_t * nbshp);
static u_int8_t
static u_int8_t
rmi_pci_bus_space_read_1(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static u_int16_t
static u_int16_t
rmi_pci_bus_space_read_2(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static u_int32_t
static u_int32_t
rmi_pci_bus_space_read_4(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static void
static void
rmi_pci_bus_space_read_multi_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_read_multi_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_read_multi_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_read_region_1(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int8_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_read_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int16_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_read_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int32_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_write_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t value);
static void
static void
rmi_pci_bus_space_write_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t value);
static void
static void
rmi_pci_bus_space_write_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t value);
static void
static void
rmi_pci_bus_space_write_multi_1(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int8_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_write_multi_2(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int16_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_write_multi_4(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int32_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_write_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int16_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_write_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int32_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_set_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value,
size_t count);
static void
static void
rmi_pci_bus_space_set_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value,
size_t count);
static void
static void
rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
bus_size_t offset __unused, bus_size_t len __unused, int flags);
static void
static void
rmi_pci_bus_space_copy_region_2(void *t,
bus_space_handle_t bsh1,
bus_size_t off1,
bus_space_handle_t bsh2,
bus_size_t off2, size_t count);
u_int8_t
u_int8_t
rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset);
static u_int16_t
static u_int16_t
rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset);
static u_int32_t
static u_int32_t
rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset);
static void
static void
rmi_pci_bus_space_read_multi_stream_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_read_multi_stream_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_read_multi_stream_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr,
size_t count);
void
void
rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t value);
static void
static void
rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value);
static void
static void
rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value);
static void
static void
rmi_pci_bus_space_write_multi_stream_1(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int8_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_write_multi_stream_2(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int16_t * addr,
size_t count);
static void
static void
rmi_pci_bus_space_write_multi_stream_4(void *t,
bus_space_handle_t handle,
bus_size_t offset,

6
sys/mips/nlm/cms.c
View File

@ -107,7 +107,7 @@ static int fmn_loops[XLP_MAX_CORES * XLP_MAX_THREADS];
static int polled = 0;
/* We do only i/o device credit setup here. CPU credit setup is now
* moved to xlp_msgring_cpu_init() so that the credits get setup
* moved to xlp_msgring_cpu_init() so that the credits get setup
* only if the CPU exists. xlp_msgring_cpu_init() gets called from
* platform_init_ap; and this makes it easy for us to setup CMS
* credits for various types of XLP chips, with varying number of
@ -198,9 +198,9 @@ xlp_handle_msg_vc(u_int vcmask, int max_msgs)
mflags = nlm_save_flags_cop2();
status = nlm_fmn_msgrcv(vc, &srcid, &size, &code,
&msg);
&msg);
nlm_restore_flags(mflags);
if (status != 0) /* no msg or error */
if (status != 0) /* no msg or error */
continue;
if (srcid < 0 && srcid >= 1024) {
printf("[%s]: bad src id %d\n", __func__,

2
sys/mips/nlm/hal/fmn.h
View File

@ -94,7 +94,7 @@
/* Each XLP chip can hold upto 32K messages on the chip itself */
#define CMS_ON_CHIP_MESG_SPACE (32*1024)
#define CMS_MAX_ONCHIP_SEGMENTS 1024
#define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64
#define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64
/* FMN Network error */
#define CMS_ILLEGAL_DST_ERROR 0x100

2
sys/mips/nlm/hal/gbu.h
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

2
sys/mips/nlm/hal/interlaken.h
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

4
sys/mips/nlm/hal/mdio.h
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -34,7 +34,7 @@
/**
* @file_name mdio.h
* @author Netlogic Microsystems
* @brief Access functions for XLP MDIO
* @brief Access functions for XLP MDIO
*/
#define INT_MDIO_CTRL 0x19
#define INT_MDIO_CTRL_DATA 0x1A

6
sys/mips/nlm/hal/mips-extns.h
View File

@ -161,7 +161,7 @@ nlm_ldaddwu(unsigned int value, unsigned int *addr)
#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */
/*
* 32 bit compilation, 64 bit values has to split
* 32 bit compilation, 64 bit values has to split
*/
#define read_c0_register64(reg, sel) \
({ \
@ -207,7 +207,7 @@ do { \
* cp0 register 9 sel 7
* bits 0...7 are same as status register 8...15
*/
static __inline uint64_t
static __inline uint64_t
nlm_read_c0_eirr(void)
{
@ -221,7 +221,7 @@ nlm_write_c0_eirr(uint64_t val)
write_c0_register64(9, 6, val);
}
static __inline uint64_t
static __inline uint64_t
nlm_read_c0_eimr(void)
{

8
sys/mips/nlm/hal/mmu.h
View File

@ -43,7 +43,7 @@ nlm_read_c0_config6(void)
".set push\n"
".set mips64\n"
"mfc0 %0, $16, 6\n"
".set pop\n"
".set pop\n"
: "=r" (rv));
return rv;
@ -56,7 +56,7 @@ nlm_write_c0_config6(uint32_t value)
".set push\n"
".set mips64\n"
"mtc0 %0, $16, 6\n"
".set pop\n"
".set pop\n"
: : "r" (value));
}
@ -69,7 +69,7 @@ nlm_read_c0_config7(void)
".set push\n"
".set mips64\n"
"mfc0 %0, $16, 7\n"
".set pop\n"
".set pop\n"
: "=r" (rv));
return rv;
@ -82,7 +82,7 @@ nlm_write_c0_config7(uint32_t value)
".set push\n"
".set mips64\n"
"mtc0 %0, $16, 7\n"
".set pop\n"
".set pop\n"
: : "r" (value));
}
/**

4
sys/mips/nlm/hal/nae.h
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -457,7 +457,7 @@
#define XLP8XX_MS_FIFO_SZ 2048
#define XLP8XX_PKT_FIFO_SZ 16384
#define XLP8XX_PKTLEN_FIFO_SZ 2048
#define XLP8XX_MAX_STG2_OFFSET 0x7F
#define XLP8XX_MAX_EH_OFFSET 0x7F
#define XLP8XX_MAX_FREE_OUT_OFFSET 0x7F

4
sys/mips/nlm/hal/nlm_hal.c
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

78
sys/mips/nlm/hal/nlmsaelib.h
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -66,7 +66,7 @@
* Since buffer allocation for crypto at kernel is done as malloc, each
* segment size is given as page size which is 4K by default
*/
#define NLM_CRYPTO_MAX_SEG_LEN PAGE_SIZE
#define NLM_CRYPTO_MAX_SEG_LEN PAGE_SIZE
#define MAX_KEY_LEN_IN_DW 20
@ -83,16 +83,16 @@
enum nlm_cipher_algo {
NLM_CIPHER_BYPASS = 0,
NLM_CIPHER_DES = 1,
NLM_CIPHER_3DES = 2,
NLM_CIPHER_3DES = 2,
NLM_CIPHER_AES128 = 3,
NLM_CIPHER_AES192 = 4,
NLM_CIPHER_AES256 = 5,
NLM_CIPHER_ARC4 = 6,
NLM_CIPHER_AES256 = 5,
NLM_CIPHER_ARC4 = 6,
NLM_CIPHER_KASUMI_F8 = 7,
NLM_CIPHER_SNOW3G_F8 = 8,
NLM_CIPHER_CAMELLIA128 = 9,
NLM_CIPHER_CAMELLIA192 = 0xA,
NLM_CIPHER_CAMELLIA256 = 0xB,
NLM_CIPHER_SNOW3G_F8 = 8,
NLM_CIPHER_CAMELLIA128 = 9,
NLM_CIPHER_CAMELLIA192 = 0xA,
NLM_CIPHER_CAMELLIA256 = 0xB,
NLM_CIPHER_MAX = 0xC,
};
@ -153,7 +153,7 @@ enum nlm_hash_mode {
NLM_HASH_MODE_CCM = 8, /* AES */
NLM_HASH_MODE_GCM = 9, /* AES */
NLM_HASH_MODE_MAX = 0xA,
};
};
/**
* @brief crypto control descriptor, should be cache aligned
@ -163,28 +163,28 @@ struct nlm_crypto_pkt_ctrl {
uint64_t desc0;
/* combination of cipher and hash keys */
uint64_t key[MAX_KEY_LEN_IN_DW];
uint32_t cipherkeylen;
uint32_t hashkeylen;
uint32_t cipherkeylen;
uint32_t hashkeylen;
uint32_t taglen;
};
/**
* @brief crypto packet descriptor, should be cache aligned
* @brief crypto packet descriptor, should be cache aligned
* @ingroup crypto
*/
struct nlm_crypto_pkt_param {
uint64_t desc0;
uint64_t desc1;
uint64_t desc1;
uint64_t desc2;
uint64_t desc3;
uint64_t segment[1][2];
};
static __inline__ uint64_t
nlm_crypto_form_rsa_ecc_fmn_entry0(unsigned int l3alloc, unsigned int type,
nlm_crypto_form_rsa_ecc_fmn_entry0(unsigned int l3alloc, unsigned int type,
unsigned int func, uint64_t srcaddr)
{
return (left_shift64(l3alloc, 61, 1) |
return (left_shift64(l3alloc, 61, 1) |
left_shift64(type, 46, 7) |
left_shift64(func, 40, 6) |
left_shift64(srcaddr, 0, 40));
@ -203,14 +203,14 @@ nlm_crypto_form_rsa_ecc_fmn_entry1(unsigned int dstclobber,
/**
* @brief Generate cypto control descriptor
* @ingroup crypto
* hmac : 1 for hash with hmac
* hmac : 1 for hash with hmac
* hashalg, see hash_alg enums
* hashmode, see hash_mode enums
* cipherhalg, see cipher_alg enums
* ciphermode, see cipher_mode enums
* arc4_cipherkeylen : length of arc4 cipher key, 0 is interpreted as 32
* arc4_keyinit :
* cfbmask : cipher text for feedback,
* arc4_cipherkeylen : length of arc4 cipher key, 0 is interpreted as 32
* arc4_keyinit :
* cfbmask : cipher text for feedback,
* 0(1 bit), 1(2 bits), 2(4 bits), 3(8 bits), 4(16bits), 5(32 bits),
* 6(64 bits), 7(128 bits)
*/
@ -220,13 +220,13 @@ nlm_crypto_form_pkt_ctrl_desc(unsigned int hmac, unsigned int hashalg,
unsigned int arc4_cipherkeylen, unsigned int arc4_keyinit,
unsigned int cfbmask)
{
return (left_shift64(hmac, 61, 1) |
left_shift64(hashalg, 52, 8) |
left_shift64(hashmode, 43, 8) |
left_shift64(cipheralg, 34, 8) |
left_shift64(ciphermode, 25, 8) |
left_shift64(arc4_cipherkeylen, 18, 5) |
left_shift64(arc4_keyinit, 17, 1) |
return (left_shift64(hmac, 61, 1) |
left_shift64(hashalg, 52, 8) |
left_shift64(hashmode, 43, 8) |
left_shift64(cipheralg, 34, 8) |
left_shift64(ciphermode, 25, 8) |
left_shift64(arc4_cipherkeylen, 18, 5) |
left_shift64(arc4_keyinit, 17, 1) |
left_shift64(cfbmask, 0, 3));
}
/**
@ -264,7 +264,7 @@ nlm_crypto_form_pkt_desc1(unsigned int cipherlen, unsigned int hashlen)
{
return (left_shift64_mask((cipherlen - 1), 32, 32) |
left_shift64_mask((hashlen - 1), 0, 32));
}
}
/**
* @brief Generate cypto packet descriptor 2
@ -300,7 +300,7 @@ nlm_crypto_form_pkt_desc2(unsigned int ivoff, unsigned int cipherbit_cnt,
* taglen : length in bits of the tag generated by the auth engine
* md5 (128 bits), sha1 (160), sha224 (224), sha384 (384),
* sha512 (512), Kasumi (32), snow3g (32), gcm (128)
* hmacpad : 1 if hmac padding is already done
* hmacpad : 1 if hmac padding is already done
*/
static __inline__ uint64_t
nlm_crypto_form_pkt_desc3(unsigned int designer_vc, unsigned int taglen,
@ -398,23 +398,23 @@ nlm_crypto_get_hklen_taglen(enum nlm_hash_algo hashalg,
*hklen = 64;
} else if (hashalg == NLM_HASH_SHA) {
switch (hashmode) {
case NLM_HASH_MODE_SHA1:
case NLM_HASH_MODE_SHA1:
*taglen = 160;
*hklen = 64;
break;
case NLM_HASH_MODE_SHA224:
case NLM_HASH_MODE_SHA224:
*taglen = 224;
*hklen = 64;
break;
case NLM_HASH_MODE_SHA256:
case NLM_HASH_MODE_SHA256:
*taglen = 256;
*hklen = 64;
break;
case NLM_HASH_MODE_SHA384:
case NLM_HASH_MODE_SHA384:
*taglen = 384;
*hklen = 128;
break;
case NLM_HASH_MODE_SHA512:
case NLM_HASH_MODE_SHA512:
*taglen = 512;
*hklen = 128;
break;
@ -449,7 +449,7 @@ nlm_crypto_get_hklen_taglen(enum nlm_hash_algo hashalg,
/**
* @brief Generate fill cryto control info structure
* @ingroup crypto
* hmac : 1 for hash with hmac
* hmac : 1 for hash with hmac
* hashalg: see above, hash_alg enums
* hashmode: see above, hash_mode enums
* cipherhalg: see above, cipher_alg enums
@ -465,7 +465,7 @@ nlm_crypto_fill_pkt_ctrl(struct nlm_crypto_pkt_ctrl *ctrl, unsigned int hmac,
{
unsigned int taglen = 0, hklen = 0;
ctrl->desc0 = nlm_crypto_form_pkt_ctrl_desc(hmac, hashalg, hashmode,
ctrl->desc0 = nlm_crypto_form_pkt_ctrl_desc(hmac, hashalg, hashmode,
cipheralg, ciphermode, 0, 0, 0);
memset(ctrl->key, 0, sizeof(ctrl->key));
if (cipherkey)
@ -480,7 +480,7 @@ nlm_crypto_fill_pkt_ctrl(struct nlm_crypto_pkt_ctrl *ctrl, unsigned int hmac,
ctrl->cipherkeylen = cipherkeylen;
ctrl->hashkeylen = hklen;
ctrl->taglen = taglen;
/* TODO : add the invalid checks and return error */
return (0);
}
@ -529,8 +529,6 @@ nlm_crypto_fill_cipher_auth_pkt_param(struct nlm_crypto_pkt_ctrl *ctrl,
* cipheroff : cipher offset from start of data
* cipherlen : cipher length in bytes
*/
static __inline__ void
nlm_crypto_fill_cipher_pkt_param(struct nlm_crypto_pkt_ctrl *ctrl,
struct nlm_crypto_pkt_param *param, unsigned int encrypt,
@ -586,7 +584,7 @@ nlm_crypto_fill_src_seg(struct nlm_crypto_pkt_param *param, int seg,
}
static __inline__ unsigned int
nlm_crypto_fill_dst_seg(struct nlm_crypto_pkt_param *param,
nlm_crypto_fill_dst_seg(struct nlm_crypto_pkt_param *param,
int seg, unsigned char *output, unsigned int outlen)
{
unsigned off = 0, len = 0;

4
sys/mips/nlm/hal/pcibus.h
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

4
sys/mips/nlm/hal/poe.h
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -277,7 +277,7 @@ nlm_poe_max_flows(uint64_t poe_pcibase)
* thr_vcmask: destination VCs for a thread
*/
static __inline void
nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3,
nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3,
uint32_t thr_vcmask, uint32_t *distvec)
{
uint32_t cpumask = 0, val;

2
sys/mips/nlm/hal/sgmii.h
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

12
sys/mips/nlm/hal/ucore_loader.h
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -52,7 +52,7 @@ nlm_ucore_load_image(uint64_t nae_base, int ucore)
nlm_store_word_daddr(addr, htobe32(p[i]));
/* add a 'nop' if number of instructions are odd */
if (size & 0x1)
if (size & 0x1)
nlm_store_word_daddr(addr, 0x0);
}
@ -66,11 +66,11 @@ nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data)
return (-1);
ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
/* set iram to zero */
/* set iram to zero */
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
(ucore_cfg & ~(0x1 << 7)));
nlm_store_word_daddr(addr + (index * 4), data);
nlm_store_word_daddr(addr + (index * 4), data);
/* restore ucore config */
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
@ -84,11 +84,11 @@ nlm_ucore_read_sharedmem(uint64_t nae_base, int index)
uint32_t ucore_cfg, val;
ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
/* set iram to zero */
/* set iram to zero */
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
(ucore_cfg & ~(0x1 << 7)));
val = nlm_load_word_daddr(addr + (index * 4));
val = nlm_load_word_daddr(addr + (index * 4));
/* restore ucore config */
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);

4
sys/mips/nlm/hal/usb.h
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

2
sys/mips/nlm/hal/xaui.h
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

4
sys/mips/nlm/interrupt.h
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

16
sys/mips/nlm/intr_machdep.c
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
@ -64,7 +64,7 @@ struct xlp_intrsrc {
int irq;
int irt;
};
static struct xlp_intrsrc xlp_interrupts[XLR_MAX_INTR];
static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR];
static int intrcnt_index;
@ -124,7 +124,7 @@ static void
xlp_post_filter(void *source)
{
struct xlp_intrsrc *src = source;
if (src->bus_ack)
src->bus_ack(src->irq, src->bus_ack_arg);
nlm_pic_ack(xlp_pic_base, src->irt);
@ -228,8 +228,8 @@ cpu_intr(struct trapframe *tf)
eirr = nlm_read_c0_eirr();
eimr = nlm_read_c0_eimr();
eirr &= eimr;
if (eirr == 0) {
if (eirr == 0) {
critical_exit();
return;
}
@ -242,7 +242,7 @@ cpu_intr(struct trapframe *tf)
critical_exit();
return;
}
/* FIXME sched pin >? LOCK>? */
for (i = sizeof(eirr) * 8 - 1; i >= 0; i--) {
if ((eirr & (1ULL << i)) == 0)
@ -295,7 +295,7 @@ cpu_init_interrupts()
/*
* Initialize all available vectors so spare IRQ
* would show up in systat output
* would show up in systat output
*/
for (i = 0; i < XLR_MAX_INTR; i++) {
snprintf(name, MAXCOMLEN + 1, "int%d:", i);

10
sys/mips/nlm/mpreset.S
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
@ -124,7 +124,7 @@ nmi_handler:
/*
* Enable other threads in the core, called from thread 0
* of the core
*/
*/
LEAF(xlp_enable_threads)
/*
* Save and restore callee saved registers of all ABIs
@ -152,7 +152,7 @@ LEAF(xlp_enable_threads)
/* Use register number to work in o32 and n32 */
li $9, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
move $8, a0
move $8, a0
sync
MTCR(8, 9)
mfc0 t0, MIPS_COP_0_PRID, 1
@ -164,7 +164,7 @@ LEAF(xlp_enable_threads)
nop
2: /*
2: /*
* Parent hardware thread, restore registers, return
*/
#if 1

4
sys/mips/nlm/msgring.h
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

8
sys/mips/nlm/tick.c
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
@ -85,7 +85,7 @@ static void clock_identify(driver_t *, device_t);
static int clock_attach(device_t);
static unsigned counter_get_timecount(struct timecounter *tc);
void
void
mips_timer_early_init(uint64_t clock_hz)
{
/* Initialize clock early so that we can use DELAY sooner */
@ -287,7 +287,7 @@ clock_intr(void *arg)
*/
lost_ticks = DPCPU_GET(lost_ticks);
lost_ticks += count - compare_last;
/*
* If the COUNT and COMPARE registers are no longer in sync
* then make up some reasonable value for the 'lost_ticks'.

6
sys/mips/nlm/uart_cpu_xlp.c
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
@ -79,7 +79,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->bas.chan = 0;
di->bas.bst = rmi_uart_bus_space;
di->bas.bsh = nlm_get_uart_regbase(0, BOARD_CONSOLE_UART);
di->bas.regshft = 2;
/* divisor = rclk / (baudrate * 16); */
di->bas.rclk = XLP_IO_CLK;

22
sys/mips/nlm/usb_init.c
View File

@ -47,26 +47,26 @@ nlm_usb_intr_en(int node, int port)
uint32_t val;
uint64_t port_addr;
port_addr = nlm_get_usb_regbase(node, port);
port_addr = nlm_get_usb_regbase(node, port);
val = nlm_read_usb_reg(port_addr, USB_INT_EN);
val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN |
val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN |
USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN |
USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
nlm_write_usb_reg(port_addr, USB_INT_EN, val);
}
static void
static void
nlm_usb_hw_reset(int node, int port)
{
uint64_t port_addr;
uint32_t val;
/* reset USB phy */
port_addr = nlm_get_usb_regbase(node, port);
port_addr = nlm_get_usb_regbase(node, port);
val = nlm_read_usb_reg(port_addr, USB_PHY_0);
val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1);
nlm_write_usb_reg(port_addr, USB_PHY_0, val);
DELAY(100);
val = nlm_read_usb_reg(port_addr, USB_CTL_0);
val &= ~(USB_CONTROLLER_RESET);
@ -74,17 +74,17 @@ nlm_usb_hw_reset(int node, int port)
nlm_write_usb_reg(port_addr, USB_CTL_0, val);
}
static void
static void
nlm_usb_init(void)
{
/* XXX: should be checking if these are in Device mode here */
printf("Initialize USB Interface\n");
nlm_usb_hw_reset(0, 0);
nlm_usb_hw_reset(0, 3);
nlm_usb_hw_reset(0, 0);
nlm_usb_hw_reset(0, 3);
/* Enable PHY interrupts */
nlm_usb_intr_en(0, 0);
nlm_usb_intr_en(0, 3);
nlm_usb_intr_en(0, 0);
nlm_usb_intr_en(0, 3);
}
SYSINIT(nlm_usb_init, SI_SUB_CPU, SI_ORDER_MIDDLE,

4
sys/mips/nlm/xlp.h
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

42
sys/mips/nlm/xlp_machdep.c
View File

@ -12,11 +12,11 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
@ -136,7 +136,7 @@ xlp_setup_core(void)
nlm_mtcr(SCHED_DEFEATURE, reg);
}
static void
static void
xlp_setup_mmu(void)
{
uint32_t pagegrain;
@ -197,15 +197,15 @@ xlp_parse_mmu_options(void)
case 1:
xlp_threads_per_core = 1;
xlp_mmuval = 0;
break;
break;
case 3:
xlp_threads_per_core = 2;
xlp_mmuval = 2;
break;
case 0xf:
break;
case 0xf:
xlp_threads_per_core = 4;
xlp_mmuval = 3;
break;
break;
default:
goto unsupp;
}
@ -224,20 +224,20 @@ xlp_parse_mmu_options(void)
cpu_map &= ~(0xfu << (4 * i));
}
/* Verify other cores' CPU masks */
/* Verify other cores' CPU masks */
for (i = 1; i < XLP_MAX_CORES; i++) {
core_thr_mask = (cpu_map >> (4 * i)) & 0xf;
if (core_thr_mask == 0)
continue;
continue;
if (core_thr_mask != core0_thr_mask)
goto unsupp;
goto unsupp;
xlp_ncores++;
}
xlp_hw_thread_mask = cpu_map;
/* setup hardware processor id to cpu id mapping */
for (i = 0; i< MAXCPU; i++)
xlp_cpuid_to_hwtid[i] =
xlp_cpuid_to_hwtid[i] =
xlp_hwtid_to_cpuid[i] = -1;
for (i = 0, k = 0; i < XLP_MAX_CORES; i++) {
if (((cpu_map >> (i * 4)) & 0xf) == 0)
@ -396,7 +396,7 @@ platform_get_timecount(struct timecounter *tc __unused)
return (unsigned int)~count;
}
static void
static void
xlp_pic_init(void)
{
struct timecounter pic_timecounter = {
@ -452,7 +452,7 @@ mem_exclude_add(vm_paddr_t *avail, vm_paddr_t mstart, vm_paddr_t mend)
continue;
if (mstart < xlp_mem_excl[i]) {
avail[pos++] = mstart;
if (mend < xlp_mem_excl[i])
if (mend < xlp_mem_excl[i])
avail[pos++] = mend;
else
avail[pos++] = xlp_mem_excl[i];
@ -523,7 +523,7 @@ xlp_mem_init(void)
phys_avail[j] = phys_avail[j + 1] = 0;
/* copy phys_avail to dump_avail */
for (i = 0; i <= j + 1; i++)
for (i = 0; i <= j + 1; i++)
dump_avail[i] = phys_avail[i];
realmem = physmem = btoc(physsz);
@ -562,7 +562,7 @@ platform_start(__register_t a0 __unused,
bcopy(XLPResetEntry, (void *)MIPS_RESET_EXC_VEC,
XLPResetEntryEnd - XLPResetEntry);
#ifdef SMP
/*
/*
* We will enable the other threads in core 0 here
* so that the TLB and cache info is correct when
* mips_init runs
@ -582,14 +582,14 @@ platform_start(__register_t a0 __unused,
/*
* XLP specific post initialization
* initialize other on chip stuff
* initialize other on chip stuff
*/
xlp_pic_init();
mips_timer_init_params(xlp_cpu_frequency, 0);
}
void
void
platform_cpu_init()
{
}
@ -607,7 +607,7 @@ platform_reset(void)
#ifdef SMP
/*
* XLP threads are started simultaneously when we enable threads, this will
* ensure that the threads are blocked in platform_init_ap, until they are
* ensure that the threads are blocked in platform_init_ap, until they are
* ready to proceed to smp_init_secondary()
*/
static volatile int thr_unblock[4];
@ -642,7 +642,7 @@ platform_start_ap(int cpuid)
/* Poll for CPU to mark itself coherent */
do {
val = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
} while ((val & coremask) != 0);
} while ((val & coremask) != 0);
if (bootverbose)
printf("Done\n");
} else {
@ -666,7 +666,7 @@ platform_init_ap(int cpuid)
xlp_enable_threads(xlp_mmuval);
} else {
/*
* FIXME busy wait here eats too many cycles, especially
* FIXME busy wait here eats too many cycles, especially
* in the core 0 while bootup
*/
while (thr_unblock[thr] == 0)
@ -690,7 +690,7 @@ platform_init_ap(int cpuid)
}
int
platform_ipi_intrnum(void)
platform_ipi_intrnum(void)
{
return (IRQ_IPI);

16
sys/mips/nlm/xlp_pci.c
View File

@ -12,7 +12,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -220,7 +220,7 @@ xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
else if ((width == 4) && (reg & 3))
return 0xFFFFFFFF;
/*
/*
* The intline and int pin of SoC devices are DOA, except
* for bridges (slot %8 == 1).
* use the values we stashed in a writable PCI scratch reg.
@ -304,7 +304,7 @@ xlp_pcib_hardware_swap_enable(int node, int link)
#endif
}
static int
static int
xlp_pcib_attach(device_t dev)
{
int node, link;
@ -321,7 +321,7 @@ xlp_pcib_attach(device_t dev)
/*
* XLS PCIe can have upto 4 links, and each link has its on IRQ
* Find the link on which the device is on
* Find the link on which the device is on
*/
static int
xlp_pcie_link(device_t pcib, device_t dev)
@ -351,7 +351,7 @@ xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
/*
* Each link has 32 MSIs that can be allocated, but for now
* we only support one device per link.
* msi_alloc() equivalent is needed when we start supporting
* msi_alloc() equivalent is needed when we start supporting
* bridges on the PCIe link.
*/
link = xlp_pcie_link(pcib, dev);
@ -381,7 +381,7 @@ xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
int link;
if (irq < 64) {
device_printf(dev, "%s: map_msi for irq %d - ignored",
device_printf(dev, "%s: map_msi for irq %d - ignored",
device_get_nameunit(pcib), irq);
return (ENXIO);
}
@ -444,7 +444,7 @@ mips_platform_pcib_setup_intr(device_t dev, device_t child,
if (strcmp(device_get_name(dev), "pcib") != 0)
return (0);
/*
/*
* temporary hack for MSI, we support just one device per
* link, and assign the link interrupt to the device interrupt
*/
@ -480,7 +480,7 @@ mips_platform_pcib_setup_intr(device_t dev, device_t child,
val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP);
/* MSI capability enable at bridge */
nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP,
nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP,
(val | (PCIM_MSICTRL_MSI_ENABLE << 16) |
(PCIM_MSICTRL_MMC_32 << 16)));
xlpirq = PIC_PCIE_IRQ(link);