From 72e9d2e8a2274a2c7e1a6e65b1bd323f94b3942e Mon Sep 17 00:00:00 2001 From: Andrew Gallatin Date: Mon, 19 Jun 2000 21:15:45 +0000 Subject: [PATCH] Add support for the Alpha Processor, Inc. UP1000 system. Reviewed by: dfr Thanks to: Alpha Processor Inc. for supplying the hardware. --- sys/alpha/alpha/api_up1000.c | 127 +++++++++++ sys/alpha/alpha/cpuconf.c | 24 +- sys/alpha/alpha/machdep.c | 18 +- sys/alpha/include/cpuconf.h | 2 + sys/alpha/include/rpb.h | 7 + sys/alpha/pci/irongate.c | 420 +++++++++++++++++++++++++++++++++++ sys/alpha/pci/irongate_pci.c | 95 ++++++++ sys/alpha/pci/irongatereg.h | 43 ++++ sys/alpha/pci/irongatevar.h | 30 +++ sys/conf/files.alpha | 3 + sys/conf/options.alpha | 1 + 11 files changed, 765 insertions(+), 5 deletions(-) create mode 100644 sys/alpha/alpha/api_up1000.c create mode 100644 sys/alpha/pci/irongate.c create mode 100644 sys/alpha/pci/irongate_pci.c create mode 100644 sys/alpha/pci/irongatereg.h create mode 100644 sys/alpha/pci/irongatevar.h diff --git a/sys/alpha/alpha/api_up1000.c b/sys/alpha/alpha/api_up1000.c new file mode 100644 index 000000000000..26e8e2fc1192 --- /dev/null +++ b/sys/alpha/alpha/api_up1000.c @@ -0,0 +1,127 @@ +/*- + * Copyright (c) 2000 Andrew Gallatin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include "opt_ddb.h" +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "sio.h" +#include "sc.h" + +#ifndef CONSPEED +#define CONSPEED TTYDEF_SPEED +#endif +static int comcnrate = CONSPEED; + +void api_up1000_init __P((void)); +static void api_up1000_cons_init __P((void)); + +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + +void +api_up1000_init() +{ + platform.family = "UP1000"; + + if ((platform.model = alpha_dsr_sysname()) == NULL) { + /* XXX Don't know the system variations, yet. */ + platform.model = alpha_unknown_sysname(); + } + + platform.iobus = "irongate"; + platform.cons_init = api_up1000_cons_init; +} + +extern int comconsole; + +static void +api_up1000_cons_init() +{ + struct ctb *ctb; + + irongate_init(); +#ifdef DDB + siogdbattach(0x2f8, 57600); +#endif + + ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off); + + switch (ctb->ctb_term_type) { + case 2: + /* serial console ... */ + /* XXX */ + { + /* + * Delay to allow PROM putchars to complete. + * FIFO depth * character time, + * character time = (1000000 / (defaultrate / 10)) + */ + DELAY(160000000 / comcnrate); + comconsole = 0; + if (siocnattach(0x3f8, comcnrate)) + panic("can't init serial console"); + + break; + } + + case 3: + /* display console ... */ + /* XXX */ +#if NSC > 0 + sccnattach(); +#else + panic("not configured to use display && keyboard console"); +#endif + break; + + default: + printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type); + printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot); + + panic("consinit: unknown console type %ld\n", + ctb->ctb_term_type); + } +} + + diff --git a/sys/alpha/alpha/cpuconf.c b/sys/alpha/alpha/cpuconf.c index 0a6f3d9989af..5198ce0dd917 100644 --- a/sys/alpha/alpha/cpuconf.c +++ b/sys/alpha/alpha/cpuconf.c @@ -122,6 +122,12 @@ extern void dec_2100_a500_init __P((int)); #define dec_2100_a500_init platform_not_configured #endif +#ifdef API_UP1000 +extern void api_up1000_init __P((int)); +#else +#define api_up1000_init(n) platform_not_configured((n) + API_ST_BASE) +#endif + struct cpuinit cpuinit[] = { cpu_notsupp("???"), /* 0: ??? */ cpu_notsupp("ST_ADU"), /* 1: ST_ADU */ @@ -161,14 +167,30 @@ struct cpuinit cpuinit[] = { }; int ncpuinit = (sizeof(cpuinit) / sizeof(cpuinit[0])); +struct cpuinit api_cpuinit[] = { + cpu_notsupp("???"), /* 0: ??? */ + cpu_init(api_up1000_init,"API_UP1000"), /* 1: ST_API_UP1000 */ +}; +int napi_cpuinit = (sizeof(api_cpuinit) / sizeof(api_cpuinit[0])); + + void platform_not_configured(int cputype) { + struct cpuinit *cpu; + + if (cputype >= API_ST_BASE) { + cputype -= API_ST_BASE; + cpu = api_cpuinit; + } else { + cpu = cpuinit; + } + printf("\n"); printf("Support for system type %d is not present in this kernel.\n", cputype); printf("Please build a kernel with \"options %s\" and reboot.\n", - cpuinit[cputype].option); + cpu[cputype].option); printf("\n"); panic("platform not configured\n"); } diff --git a/sys/alpha/alpha/machdep.c b/sys/alpha/alpha/machdep.c index 4ff34362017e..68680ea5f791 100644 --- a/sys/alpha/alpha/machdep.c +++ b/sys/alpha/alpha/machdep.c @@ -733,11 +733,21 @@ alpha_init(pfn, ptb, bim, bip, biv) */ cputype = -cputype; } - if (cputype >= ncpuinit) { - platform_not_supported(cputype); - /* NOTREACHED */ + + if (cputype >= API_ST_BASE) { + if (cputype >= napi_cpuinit + API_ST_BASE) { + platform_not_supported(cputype); + /* NOTREACHED */ + } + cputype -= API_ST_BASE; + api_cpuinit[cputype].init(cputype); + } else { + if (cputype >= ncpuinit) { + platform_not_supported(cputype); + /* NOTREACHED */ + } + cpuinit[cputype].init(cputype); } - cpuinit[cputype].init(cputype); snprintf(cpu_model, sizeof(cpu_model), "%s", platform.model); /* diff --git a/sys/alpha/include/cpuconf.h b/sys/alpha/include/cpuconf.h index 8bdb79431895..7ff7d9881216 100644 --- a/sys/alpha/include/cpuconf.h +++ b/sys/alpha/include/cpuconf.h @@ -121,7 +121,9 @@ const char *alpha_variation_name __P((u_int64_t variation, const char *alpha_unknown_sysname __P((void)); extern struct cpuinit cpuinit[]; +extern struct cpuinit api_cpuinit[]; extern int ncpuinit; +extern int napi_cpuinit; extern void platform_not_configured __P((int)); extern void platform_not_supported __P((int)); diff --git a/sys/alpha/include/rpb.h b/sys/alpha/include/rpb.h index 75c0c5b8e9be..1f2f884ec6b4 100644 --- a/sys/alpha/include/rpb.h +++ b/sys/alpha/include/rpb.h @@ -79,6 +79,13 @@ struct rpb { #define ST_DEC_ALPHAVME_320 33 /* "Yukon" (VME?) */ #define ST_DEC_6600 34 /* "Monet/Goldrush" */ +/* + * System types for Alpha Processor Inc. machines + */ + +#define API_ST_BASE 200 +#define ST_API_UP1000 201 /* "Nautilus" */ + u_int64_t rpb_type; /* 50: */ #define SV_MPCAP 0x00000001 /* multiprocessor capable */ diff --git a/sys/alpha/pci/irongate.c b/sys/alpha/pci/irongate.c new file mode 100644 index 000000000000..296d09dcd4a0 --- /dev/null +++ b/sys/alpha/pci/irongate.c @@ -0,0 +1,420 @@ +/*- + * Copyright (c) 2000 Andrew Gallatin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include "opt_cpu.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa) + +static devclass_t irongate_devclass; +static device_t irongate0; /* XXX only one for now */ + +struct irongate_softc { + int junk; /* no softc */ +}; + +#define IRONGATE_SOFTC(dev) (struct irongate_softc*) device_get_softc(dev) + +static alpha_chipset_inb_t irongate_inb; +static alpha_chipset_inw_t irongate_inw; +static alpha_chipset_inl_t irongate_inl; +static alpha_chipset_outb_t irongate_outb; +static alpha_chipset_outw_t irongate_outw; +static alpha_chipset_outl_t irongate_outl; +static alpha_chipset_readb_t irongate_readb; +static alpha_chipset_readw_t irongate_readw; +static alpha_chipset_readl_t irongate_readl; +static alpha_chipset_writeb_t irongate_writeb; +static alpha_chipset_writew_t irongate_writew; +static alpha_chipset_writel_t irongate_writel; +static alpha_chipset_maxdevs_t irongate_maxdevs; +static alpha_chipset_cfgreadb_t irongate_cfgreadb; +static alpha_chipset_cfgreadw_t irongate_cfgreadw; +static alpha_chipset_cfgreadl_t irongate_cfgreadl; +static alpha_chipset_cfgwriteb_t irongate_cfgwriteb; +static alpha_chipset_cfgwritew_t irongate_cfgwritew; +static alpha_chipset_cfgwritel_t irongate_cfgwritel; +static alpha_chipset_addrcvt_t irongate_cvt_dense, irongate_cvt_bwx; + +static alpha_chipset_read_hae_t irongate_read_hae; +static alpha_chipset_write_hae_t irongate_write_hae; + +static alpha_chipset_t irongate_chipset = { + irongate_inb, + irongate_inw, + irongate_inl, + irongate_outb, + irongate_outw, + irongate_outl, + irongate_readb, + irongate_readw, + irongate_readl, + irongate_writeb, + irongate_writew, + irongate_writel, + irongate_maxdevs, + irongate_cfgreadb, + irongate_cfgreadw, + irongate_cfgreadl, + irongate_cfgwriteb, + irongate_cfgwritew, + irongate_cfgwritel, + irongate_cvt_dense, + irongate_cvt_bwx, + irongate_read_hae, + irongate_write_hae, +}; + +static u_int8_t +irongate_inb(u_int32_t port) +{ + alpha_mb(); + return ldbu(KV(IRONGATE_IO + port)); +} + +static u_int16_t +irongate_inw(u_int32_t port) +{ + alpha_mb(); + return ldwu(KV(IRONGATE_IO + port)); +} + +static u_int32_t +irongate_inl(u_int32_t port) +{ + alpha_mb(); + return ldl(KV(IRONGATE_IO + port)); +} + +static void +irongate_outb(u_int32_t port, u_int8_t data) +{ + stb(KV(IRONGATE_IO + port), data); + alpha_mb(); +} + +static void +irongate_outw(u_int32_t port, u_int16_t data) +{ + stw(KV(IRONGATE_IO + port), data); + alpha_mb(); +} + +static void +irongate_outl(u_int32_t port, u_int32_t data) +{ + stl(KV(IRONGATE_IO + port), data); + alpha_mb(); +} + +static u_int8_t +irongate_readb(u_int32_t pa) +{ + alpha_mb(); + return ldbu(KV(IRONGATE_MEM + pa)); +} + +static u_int16_t +irongate_readw(u_int32_t pa) +{ + alpha_mb(); + return ldwu(KV(IRONGATE_MEM + pa)); +} + +static u_int32_t +irongate_readl(u_int32_t pa) +{ + alpha_mb(); + return ldl(KV(IRONGATE_MEM + pa)); +} + +static void +irongate_writeb(u_int32_t pa, u_int8_t data) +{ + stb(KV(IRONGATE_MEM + pa), data); + alpha_mb(); +} + +static void +irongate_writew(u_int32_t pa, u_int16_t data) +{ + stw(KV(IRONGATE_MEM + pa), data); + alpha_mb(); +} + +static void +irongate_writel(u_int32_t pa, u_int32_t data) +{ + stl(KV(IRONGATE_MEM + pa), data); + alpha_mb(); +} + +static int +irongate_maxdevs(u_int b) +{ + return 12; /* XXX */ +} + +static void +irongate_clear_abort(void) +{ + alpha_mb(); + alpha_pal_draina(); +} + +static int +irongate_check_abort(void) +{ + alpha_pal_draina(); + alpha_mb(); + + return 0; +} + +#define IRONGATE_CFGADDR(b, s, f, r) \ + KV(IRONGATE_CONF | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) + +#define CFGREAD(h, b, s, f, r, op, width, type) \ + vm_offset_t va; \ + type data; \ + va = IRONGATE_CFGADDR(b, s, f, r); \ + irongate_clear_abort(); \ + if (badaddr((caddr_t)va, width)) { \ + irongate_check_abort(); \ + return ~0; \ + } \ + data = ##op##(va); \ + if (irongate_check_abort()) \ + return ~0; \ + return data; + +#define CFWRITE(h, b, s, f, r, data, op, width) \ + vm_offset_t va; \ + va = IRONGATE_CFGADDR(b, s, f, r); \ + irongate_clear_abort(); \ + if (badaddr((caddr_t)va, width)) \ + return; \ + ##op##(va, data); \ + irongate_check_abort(); + + + + +static u_int8_t +irongate_cfgreadb(u_int h, u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(h, b, s, f, r, ldbu, 1, u_int8_t) +} + +static u_int16_t +irongate_cfgreadw(u_int h, u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(h, b, s, f, r, ldwu, 2, u_int16_t) +} + +static u_int32_t +irongate_cfgreadl(u_int h, u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(h, b, s, f, r, ldl, 4, u_int32_t) +} + +static void +irongate_cfgwriteb(u_int h, u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + CFWRITE(h, b, s, f, r, data, stb, 1) +} + +static void +irongate_cfgwritew(u_int h, u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + CFWRITE(h, b, s, f, r, data, stw, 2) +} + +static void +irongate_cfgwritel(u_int h, u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + CFWRITE(h, b, s, f, r, data, stl, 4) +} + + +vm_offset_t +irongate_cvt_bwx(vm_offset_t addr) +{ + addr &= 0xffffffffUL; + return (KV(addr | IRONGATE_MEM)); +} + +vm_offset_t +irongate_cvt_dense(vm_offset_t addr) +{ + return irongate_cvt_bwx(addr); +} + + +/* + * There doesn't appear to be an hae on this platform + */ + + +static u_int64_t +irongate_read_hae(void) +{ + return 0; +} + +static void +irongate_write_hae(u_int64_t hae) +{ +} + +static int irongate_probe(device_t dev); +static int irongate_attach(device_t dev); + +static device_method_t irongate_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, irongate_probe), + DEVMETHOD(device_attach, irongate_attach), + + /* Bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_alloc_resource, pci_alloc_resource), + DEVMETHOD(bus_release_resource, pci_release_resource), + DEVMETHOD(bus_activate_resource, pci_activate_resource), + DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), + DEVMETHOD(bus_setup_intr, isa_setup_intr), + DEVMETHOD(bus_teardown_intr, isa_teardown_intr), + + { 0, 0 } +}; + +static driver_t irongate_driver = { + "irongate", + irongate_methods, + sizeof(struct irongate_softc), +}; + +void +irongate_init() +{ + static int initted = 0; + + if (initted) return; + initted = 1; + + chipset = irongate_chipset; + alpha_XXX_dmamap_or = 0UL; + + if (platform.pci_intr_init) + platform.pci_intr_init(); +} + +static int +irongate_probe(device_t dev) +{ + + if (irongate0) + return ENXIO; + irongate0 = dev; + device_set_desc(dev, "AMD 751 Core Logic chipset"); + pci_init_resources(); + isa_init_intr(); + device_add_child(dev, "pcib", 0); + return 0; +} + + + +static int +irongate_attach(device_t dev) +{ + u_int8_t value; + pcicfgregs southbridge; + + + irongate_init(); + + if (!platform.iointr) /* XXX */ + set_iointr(alpha_dispatch_intr); + + snprintf(chipset_type, sizeof(chipset_type), "irongate"); + chipset_bwx = 1; + + chipset_ports = IRONGATE_IO; + chipset_memory = IRONGATE_MEM; + chipset_dense = IRONGATE_MEM; + /* no s/g support in this chipset, must use bounce-buffers */ + chipset.sgmap = NULL; + + /* + * XXX -- The SRM console doesn't properly initialize + * the AcerLabs M1533C southbridge. We must turn off 32-bit + * DMA support. + */ + + southbridge.hose = 0; + southbridge.bus = 0; + southbridge.slot = 7; + southbridge.func = 0; + if ((0x153310b9 == pci_cfgread(&southbridge, PCIR_DEVVENDOR, 4))) { + value = (u_int8_t)pci_cfgread(&southbridge, 0x42, 1); + value &= ~0x40; + pci_cfgwrite(&southbridge, 0x42, 0, 1); + } + + bus_generic_attach(dev); + + return 0; +} + +DRIVER_MODULE(irongate, root, irongate_driver, irongate_devclass, 0, 0); + diff --git a/sys/alpha/pci/irongate_pci.c b/sys/alpha/pci/irongate_pci.c new file mode 100644 index 000000000000..e8cf2917b819 --- /dev/null +++ b/sys/alpha/pci/irongate_pci.c @@ -0,0 +1,95 @@ +/*- + * Copyright (c) 2000 Andrew Gallatin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +static devclass_t pcib_devclass; + + +static int +irongate_pcib_probe(device_t dev) +{ + + device_set_desc(dev, "AMD 751 PCI host bus adapter"); + + device_add_child(dev, "pci", -1); + + return 0; +} + +static int +irongate_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result) +{ + if (which == PCIB_IVAR_HOSE) { + *result = 0; + return 0; + } + return ENOENT; +} + +static device_method_t irongate_pcib_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, irongate_pcib_probe), + DEVMETHOD(device_attach, bus_generic_attach), + + /* Bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_read_ivar, irongate_pcib_read_ivar), + DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), + DEVMETHOD(bus_release_resource, bus_generic_release_resource), + DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), + DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), + DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), + DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), + + { 0, 0 } +}; + + +static driver_t irongate_pcib_driver = { + "pcib", + irongate_pcib_methods, + 1, +}; + + +DRIVER_MODULE(pcib, irongate, irongate_pcib_driver, pcib_devclass, 0, 0); + + diff --git a/sys/alpha/pci/irongatereg.h b/sys/alpha/pci/irongatereg.h new file mode 100644 index 000000000000..0d10d1514717 --- /dev/null +++ b/sys/alpha/pci/irongatereg.h @@ -0,0 +1,43 @@ +/*- + * Copyright (c) 2000 Andrew Gallatin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * AMD-751 Chipset registers and constants. + * + */ + + +/* + * memory / i/o space macros + * + */ + +#define IRONGATE_MEM 0x10000000000UL +#define IRONGATE_IACK_SC 0x101F8000000UL +#define IRONGATE_IO 0x101FC000000UL +#define IRONGATE_CONF 0x101FE000000UL diff --git a/sys/alpha/pci/irongatevar.h b/sys/alpha/pci/irongatevar.h new file mode 100644 index 000000000000..31012d97f8d5 --- /dev/null +++ b/sys/alpha/pci/irongatevar.h @@ -0,0 +1,30 @@ +/*- + * Copyright (c) 2000 Andrew Gallatin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +extern void irongate_init(void); + diff --git a/sys/conf/files.alpha b/sys/conf/files.alpha index 91e461dbf875..d8608449aa5d 100644 --- a/sys/conf/files.alpha +++ b/sys/conf/files.alpha @@ -26,6 +26,7 @@ atkbdmap.h optional atkbd_dflt_keymap \ alpha/alpha/autoconf.c standard alpha/alpha/cpuconf.c standard alpha/alpha/atomic.s standard +alpha/alpha/api_up1000.c optional api_up1000 alpha/alpha/dec_kn8ae.c optional dec_kn8ae alpha/alpha/dec_eb164.c optional dec_eb164 alpha/alpha/dec_eb64plus.c optional dec_eb64plus @@ -129,6 +130,8 @@ alpha/pci/cia_pci.c optional dec_eb164 alpha/pci/cia_pci.c optional dec_kn20aa alpha/pci/cia_pci.c optional dec_st550 alpha/pci/cia_pci.c optional dec_1000a +alpha/pci/irongate.c optional api_up1000 +alpha/pci/irongate_pci.c optional api_up1000 alpha/pci/lca.c optional dec_axppci_33 alpha/pci/lca_pci.c optional dec_axppci_33 alpha/pci/pci_eb164_intr.s optional dec_eb164 diff --git a/sys/conf/options.alpha b/sys/conf/options.alpha index f0c1a4a5e00b..8260cb08a45e 100644 --- a/sys/conf/options.alpha +++ b/sys/conf/options.alpha @@ -15,6 +15,7 @@ DEC_AXPPCI_33 opt_cpu.h DEC_3000_300 opt_cpu.h DEC_3000_500 opt_cpu.h DEC_1000A opt_cpu.h +API_UP1000 opt_cpu.h PPC_PROBE_CHIPSET opt_ppc.h PPC_DEBUG opt_ppc.h