Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.
Submitted by: Thomas Skibo <ThomasSkibo (at) sbcglobal.net> Tested by: wkoszek (ZedBoard) Reviewed by: wkoszek, freebsd-arm@ (no objections raised)
This commit is contained in:
Wojciech A. Koszek
parent
1bf9f7c1c5
commit
735c7fe55e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=249999
@ -1,6 +1,6 @@
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# $FreeBSD$
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MAN= mge.4 npe.4
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MAN= mge.4 npe.4 devcfg.4
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MLINKS= mge.4 if_mge.4
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MLINKS+=npe.4 if_npe.4
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84
share/man/man4/man4.arm/devcfg.4
Normal file
84
share/man/man4/man4.arm/devcfg.4
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@ -0,0 +1,84 @@
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.\"
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.\" Copyright (c) 2013 Thomas Skibo
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. The name of the author may not be used to endorse or promote products
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.\" derived from this software without specific prior written permission.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd February 28, 2013
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.Dt DEVCFG 4
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.Os
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.Sh NAME
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.Nm devcfg
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.Nd Zynq PL device config interface
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.Sh SYNOPSIS
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.Cd device devcfg
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.Sh DESCRIPTION
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The special file
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.Pa /dev/devcfg
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can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
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.Pp
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On the first write to the character device at file offset 0, the devcfg driver
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asserts the top-level PL reset signals, disables the PS-PL level shifters,
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and clears the PL configuration. Write data is sent to
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the PCAP (processor configuration access port). When the PL asserts the
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DONE signal, the devcfg driver will enable the level shifters and release
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the top-level PL reset signals.
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.Pp
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The PL (FPGA) can be configured by writing the bitstream to the
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character device like this:
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.Bd -literal -offset indent
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cat design.bit.bin > /dev/devcfg
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.Ed
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.Pp
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The file should not be confused with the .bit file output by the FPGA
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design tools. It is the binary form of the configuration bitstream.
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The Xilinx
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.Pa promgen
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tool can do the conversion:
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.Bd -literal -offset indent
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promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
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.Ed
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.Sh SYSCTL VARIABLES
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The devcfg driver provides the following
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.Xr sysctl 8
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variables:
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.Bl -tag -width 12
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.It Va hw.fpga.pl_done
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.Pp
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This variable always reflects the status of the PL's DONE signal. A 1
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means the PL section has been properly programmed.
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.It Va hw.fpga.en_level_shifters
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.Pp
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This variable controls if the PS-PL level shifters are enabled after the
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PL section has been reconfigured. This variable is 1 by default but setting
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it to 0 allows the PL section to be programmed with configurations that
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don't interface to the PS section of the part. Changing this value has no
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effect on the level shifters until the next device reconfiguration.
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.Sh FILES
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/dev/devcfg Character device for
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.Nm
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driver.
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.Sh AUTHORS
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Thomas Skibo
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.Sh SEE ALSO
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Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585)
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@ -1480,7 +1480,8 @@ set_cpufuncs()
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cputype == CPU_ID_CORTEXA8R2 ||
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cputype == CPU_ID_CORTEXA8R3 ||
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cputype == CPU_ID_CORTEXA9R1 ||
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cputype == CPU_ID_CORTEXA9R2) {
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cputype == CPU_ID_CORTEXA9R2 ||
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cputype == CPU_ID_CORTEXA9R3) {
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cpufuncs = cortexa_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
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get_cachetype_cp15();
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@ -246,6 +246,8 @@ const struct cpuidtab cpuids[] = {
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generic_steppings },
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{ CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEXA, "Cortex A9-r2",
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generic_steppings },
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{ CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEXA, "Cortex A9-r3",
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generic_steppings },
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{ CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
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sa110_steppings },
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@ -152,6 +152,7 @@
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#define CPU_ID_CORTEXA8R3 0x413fc080
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#define CPU_ID_CORTEXA9R1 0x411fc090
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#define CPU_ID_CORTEXA9R2 0x412fc090
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#define CPU_ID_CORTEXA9R3 0x413fc090
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#define CPU_ID_SA110 0x4401a100
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#define CPU_ID_SA1100 0x4401a110
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#define CPU_ID_TI925T 0x54029250
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@ -1734,3 +1734,4 @@ DRIVER_MODULE(mmc, ti_mmchs, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, at91_mci, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, sdhci_bcm, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, sdhci_fdt, mmc_driver, mmc_devclass, NULL, NULL);
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@ -72,6 +72,7 @@ extern struct uart_class uart_sbbc_class __attribute__((weak));
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extern struct uart_class uart_z8530_class __attribute__((weak));
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extern struct uart_class uart_lpc_class __attribute__((weak));
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extern struct uart_class uart_pl011_class __attribute__((weak));
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extern struct uart_class uart_cdnc_class __attribute__((weak));
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#ifdef PC98
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struct uart_class *uart_pc98_getdev(u_long port);
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@ -109,6 +109,8 @@ uart_fdt_probe(device_t dev)
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sc->sc_class = &uart_imx_class;
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else if (ofw_bus_is_compatible(dev, "arm,pl011"))
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sc->sc_class = &uart_pl011_class;
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else if (ofw_bus_is_compatible(dev, "cadence,uart"))
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sc->sc_class = &uart_cdnc_class;
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else
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return (ENXIO);
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@ -196,6 +198,8 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
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class = &uart_ns8250_class;
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if (fdt_is_compatible(node, "arm,pl011"))
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class = &uart_pl011_class;
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if (fdt_is_compatible(node, "cadence,uart"))
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class = &uart_cdnc_class;
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di->bas.chan = 0;
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di->bas.regshft = (u_int)shift;
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