smartpqi: clean up empty lines in .c and .h files
This commit is contained in:
parent
75d41981c0
commit
7368632c18
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=365154
@ -76,7 +76,7 @@ static void get_transport_settings(struct pqisrc_softstate *softs,
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struct ccb_trans_settings_spi *spi = &cts->xport_specific.spi;
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DBG_FUNC("IN\n");
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cts->protocol = PROTO_SCSI;
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cts->protocol_version = SCSI_REV_SPC4;
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cts->transport = XPORT_SPI;
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@ -126,7 +126,7 @@ void os_remove_device(pqisrc_softstate_t *softs,
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struct cam_path *tmppath;
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DBG_FUNC("IN\n");
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if(softs->os_specific.sim_registered) {
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if (xpt_create_path(&tmppath, NULL,
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cam_sim_path(softs->os_specific.sim),
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@ -224,7 +224,6 @@ smartpqi_fix_ld_inquiry(pqisrc_softstate_t *softs, struct ccb_scsiio *csio)
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(cdb[1] & SI_EVPD) == 0 &&
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(csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN &&
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csio->dxfer_len >= SHORT_INQUIRY_LENGTH) {
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inq = (struct scsi_inquiry_data *)csio->data_ptr;
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device = softs->device_list[csio->ccb_h.target_id][csio->ccb_h.target_lun];
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@ -263,7 +262,7 @@ os_io_response_success(rcb_t *rcb)
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panic("rcb is null");
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csio = (struct ccb_scsiio *)&rcb->cm_ccb->csio;
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if (csio == NULL)
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panic("csio is null");
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@ -332,7 +331,6 @@ void os_raid_response_error(rcb_t *rcb, raid_path_error_info_elem_t *err_info)
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csio->ccb_h.status = CAM_SCSI_STATUS_ERROR
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| CAM_AUTOSNS_VALID
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| CAM_REQ_CMP_ERR;
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}
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break;
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@ -364,7 +362,6 @@ void os_raid_response_error(rcb_t *rcb, raid_path_error_info_elem_t *err_info)
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DBG_IO("OUT\n");
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}
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/*
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* Error response handling for aio.
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*/
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@ -564,7 +561,6 @@ static int pqi_map_request( rcb_t *rcb )
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rcb->status = REQUEST_PENDING;
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error = pqisrc_build_send_io(softs, rcb);
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}
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DBG_FUNC("OUT error = %d\n", error);
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@ -605,7 +601,6 @@ static void smartpqi_lunrescan_cb(struct cam_periph *periph, union ccb *ccb)
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xpt_free_ccb(ccb);
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}
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/*
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* Function to rescan the lun
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*/
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@ -717,7 +712,7 @@ static int pqisrc_io_start(struct cam_sim *sim, union ccb *ccb)
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pqi_scsi_dev_t *dvp;
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DBG_FUNC("IN\n");
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if( softs->device_list[ccb->ccb_h.target_id][ccb->ccb_h.target_lun] == NULL ) {
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ccb->ccb_h.status = CAM_DEV_NOT_THERE;
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DBG_INFO("Device = %d not there\n", ccb->ccb_h.target_id);
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@ -1172,14 +1167,13 @@ int register_sim(struct pqisrc_softstate *softs, int card_index)
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void deregister_sim(struct pqisrc_softstate *softs)
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{
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struct ccb_setasync csa;
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DBG_FUNC("IN\n");
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if (softs->os_specific.mtx_init) {
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mtx_lock(&softs->os_specific.cam_lock);
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}
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xpt_setup_ccb(&csa.ccb_h, softs->os_specific.path, 5);
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csa.ccb_h.func_code = XPT_SASYNC_CB;
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csa.event_enable = 0;
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@ -43,7 +43,7 @@ int pqisrc_submit_cmnd(pqisrc_softstate_t *softs,
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DBG_FUNC("IN\n");
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PQI_LOCK(&ib_q->lock);
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/* Check queue full */
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if ((ib_q->pi_local + 1) % ib_q->num_elem == *(ib_q->ci_virt_addr)) {
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DBG_WARN("OUT Q full\n");
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@ -77,7 +77,7 @@
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} \
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} \
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}
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#define FILL_QUEUE_ARRAY_ADDR(q,virt,dma) { \
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q->array_virt_addr = virt; \
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q->array_dma_addr = dma; \
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@ -105,7 +105,6 @@ enum INTR_TYPE {
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#define DMA_PHYS_LOW(mem) (((mem)->dma_addr) & 0x00000000ffffffff)
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#define DMA_PHYS_HIGH(mem) ((((mem)->dma_addr) & 0xffffffff00000000) >> 32)
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typedef enum REQUEST_STATUS {
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REQUEST_SUCCESS = 0,
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REQUEST_PENDING = -1,
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@ -135,7 +134,6 @@ typedef enum controller_state {
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PQI_BUS_RESET,
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}controller_state_t;
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#define PQISRC_MAX_MSIX_SUPPORTED 64
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/* SIS Specific */
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@ -187,8 +185,6 @@ typedef enum controller_state {
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#define PQISRC_MAX_ADMIN_IB_QUEUE_ELEM_NUM 16
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#define PQISRC_MAX_ADMIN_OB_QUEUE_ELEM_NUM 16
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#define PQI_MIN_OP_IB_QUEUE_ID 1
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#define PQI_OP_EVENT_QUEUE_ID 1
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#define PQI_MIN_OP_OB_QUEUE_ID 2
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@ -348,7 +344,6 @@ enum pqisrc_ctrl_mode{
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#define PQI_MANAGEMENT_CMD_RESP_TIMEOUT 3000
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#define PQISRC_EVENT_ACK_RESP_TIMEOUT 1000
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/* Supported Event types by controller */
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#define PQI_NUM_SUPPORTED_EVENTS 7
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@ -371,7 +366,6 @@ enum pqisrc_ctrl_mode{
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#define PQI_MAX_HEARTBEAT_REQUESTS 5
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/* Device flags */
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#define PQISRC_DFLAG_VALID (1 << 0)
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#define PQISRC_DFLAG_CONFIGURING (1 << 1)
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@ -409,7 +403,6 @@ enum pqisrc_ctrl_mode{
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#define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK_SET 0x02
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#define SOP_TASK_MANAGEMENT_LUN_RESET 0x8
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/* Additional CDB bytes */
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#define PQI_ADDITIONAL_CDB_BYTES_0 0 /* 16 byte CDB */
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#define PQI_ADDITIONAL_CDB_BYTES_4 1 /* 20 byte CDB */
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@ -471,7 +464,6 @@ enum pqisrc_ctrl_mode{
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#define VPD_PAGE (1 << 8)
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/* logical volume states */
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#define SA_LV_OK 0x0
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#define SA_LV_NOT_AVAILABLE 0xb
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@ -495,8 +487,6 @@ enum pqisrc_ctrl_mode{
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/* 0 = no limit */
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#define PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 0
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#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
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#define SA_CACHE_FLUSH 0x1
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@ -521,13 +511,11 @@ enum pqisrc_ctrl_mode{
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#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x4
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#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x2
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#define OBDR_SIG_OFFSET 43
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#define OBDR_TAPE_SIG "$DR-10"
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#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
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#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
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#define IOACCEL_STATUS_BYTE 4
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#define OFFLOAD_CONFIGURED_BIT 0x1
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#define OFFLOAD_ENABLED_BIT 0x2
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@ -546,7 +534,6 @@ enum pqisrc_ctrl_mode{
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#define TEST_UNIT_READY 0x00
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#define SCSI_VPD_HEADER_LENGTH 64
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#define PQI_MAX_MULTILUN 256
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#define PQI_MAX_LOGICALS 64
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#define PQI_MAX_PHYSICALS 1024
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@ -588,7 +575,6 @@ typedef enum pqisrc_device_status {
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#define BMIC_FLASH_FIRMWARE 0xf7
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#define BMIC_WRITE_HOST_WELLNESS 0xa5
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#define MASKED_DEVICE(lunid) ((lunid)[3] & 0xC0)
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#define BMIC_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3F)
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#define BMIC_GET_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
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@ -659,14 +645,12 @@ static inline void PUT_BE64(uint64_t val, uint8_t *p)
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PUT_BE32(val, p + 4);
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}
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#define OS_FREEBSD
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#define SIS_POLL_WAIT
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#define OS_ATTRIBUTE_PACKED __attribute__((__packed__))
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#define OS_ATTRIBUTE_ALIGNED(n) __attribute__((aligned(n)))
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/* Management Interface */
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#define CCISS_IOC_MAGIC 'C'
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#define SMARTPQI_IOCTL_BASE 'M'
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@ -699,7 +683,6 @@ typedef struct _driver_info
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typedef uint8_t *passthru_buf_type_t;
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#define PQISRC_DRIVER_MAJOR 1
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#define PQISRC_DRIVER_MINOR 0
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#define PQISRC_DRIVER_RELEASE 3
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@ -711,7 +694,7 @@ typedef uint8_t *passthru_buf_type_t;
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PQISRC_DRIVER_MINOR, \
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PQISRC_DRIVER_RELEASE, \
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PQISRC_DRIVER_REVISION)
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/* End Management interface */
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#ifdef ASSERT
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@ -724,7 +707,6 @@ typedef uint8_t *passthru_buf_type_t;
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} \
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}
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#define PQI_MAX_MSIX 64 /* vectors */
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#define PQI_MSI_CTX_SIZE sizeof(pqi_intr_ctx)+1
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#define IS_POLLING_REQUIRED(softs) if (cold) {\
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@ -764,7 +746,6 @@ typedef struct PCI_ACC_HANDLE {
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#define LEGACY_SIS_ODR_SHIFT 12 /* outbound doorbell shift */
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#define LEGACY_SIS_IDR_SHIFT 9 /* inbound doorbell shift */
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/*
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* PQI Register definitions for the smartraid adapters
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*/
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@ -792,9 +773,8 @@ typedef struct PCI_ACC_HANDLE {
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#define OS_BUSYWAIT(x) DELAY(x)
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#define OS_SLEEP(timeout) \
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DELAY(timeout);
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#define OS_HOST_WELLNESS_TIMEOUT (24 * 3600)
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#define OS_HOST_WELLNESS_TIMEOUT (24 * 3600)
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#define LE_16(x) htole16(x)
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#define LE_32(x) htole32(x)
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@ -806,7 +786,6 @@ typedef struct PCI_ACC_HANDLE {
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#define PQI_HWIF_SRCV 0
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#define PQI_HWIF_UNKNOWN -1
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#define SMART_STATE_SUSPEND (1<<0)
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#define SMART_STATE_UNUSED0 (1<<1)
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#define SMART_STATE_INTERRUPTS_ON (1<<2)
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@ -818,7 +797,6 @@ typedef struct PCI_ACC_HANDLE {
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#define PQI_SIM_REGISTERED (1<<2)
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#define PQI_MTX_INIT (1<<3)
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#define PQI_CMD_MAPPED (1<<2)
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/* Interrupt context to get oq_id */
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@ -947,7 +925,6 @@ static int logging_level = PQISRC_LOG_LEVEL;
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#define PQISRC_FLAGS_WARN 0x00000020
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#define PQISRC_FLAGS_ERROR 0x00000040
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#define DBG_INIT(fmt,args...) \
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do { \
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if (logging_level & PQISRC_FLAGS_INIT) { \
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@ -58,7 +58,7 @@ int pqisrc_alloc_tid(pqisrc_softstate_t *softs)
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DBG_ERR("Target ID exhausted\n");
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return INVALID_ELEM;
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}
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return softs->tid_pool.tid[softs->tid_pool.index--];
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}
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@ -68,7 +68,7 @@ void pqisrc_free_tid(pqisrc_softstate_t *softs, int tid)
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DBG_ERR("Target ID queue is full\n");
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return;
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}
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softs->tid_pool.index++;
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softs->tid_pool.tid[softs->tid_pool.index] = tid;
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}
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@ -126,7 +126,7 @@ int pqisrc_build_send_raid_request(pqisrc_softstate_t *softs, pqisrc_raid_req_t
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void *buff, size_t datasize, uint8_t cmd, uint16_t vpd_page, uint8_t *scsi3addr,
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raid_path_error_info_elem_t *error_info)
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{
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uint8_t *cdb;
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int ret = PQI_STATUS_SUCCESS;
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uint32_t tag = 0;
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@ -137,7 +137,7 @@ int pqisrc_build_send_raid_request(pqisrc_softstate_t *softs, pqisrc_raid_req_t
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ob_queue_t *ob_q = &softs->op_ob_q[PQI_DEFAULT_IB_QUEUE];
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rcb_t *rcb = NULL;
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DBG_FUNC("IN\n");
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memset(&device_mem, 0, sizeof(struct dma_mem));
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@ -149,7 +149,7 @@ int pqisrc_build_send_raid_request(pqisrc_softstate_t *softs, pqisrc_raid_req_t
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device_mem.align = PQISRC_DEFAULT_DMA_ALIGN;
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ret = os_dma_mem_alloc(softs, &device_mem);
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if (ret) {
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DBG_ERR("failed to allocate dma memory for device_mem return code %d\n", ret);
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return ret;
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@ -160,7 +160,6 @@ int pqisrc_build_send_raid_request(pqisrc_softstate_t *softs, pqisrc_raid_req_t
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sgd->addr = device_mem.dma_addr;
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sgd->len = datasize;
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sgd->flags = SG_FLAG_LAST;
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}
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/* Build raid path request */
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@ -278,7 +277,7 @@ int pqisrc_build_send_raid_request(pqisrc_softstate_t *softs, pqisrc_raid_req_t
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}
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os_dma_mem_free(softs, &device_mem);
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}
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ret = rcb->status;
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if (ret) {
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if(error_info) {
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@ -422,7 +421,6 @@ static int pqisrc_get_phys_log_device_list(pqisrc_softstate_t *softs,
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reportlun_data_ext_t *local_logdev_list;
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reportlun_data_ext_t *logdev_data;
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reportlun_header_t report_lun_header;
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DBG_FUNC("IN\n");
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@ -438,7 +436,6 @@ static int pqisrc_get_phys_log_device_list(pqisrc_softstate_t *softs,
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return ret;
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}
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logdev_data = *logical_dev_list;
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if (logdev_data) {
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@ -592,7 +589,7 @@ static uint8_t pqisrc_get_volume_offline_status(pqisrc_softstate_t *softs,
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uint8_t *buff = NULL;
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DBG_FUNC("IN\n");
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buff = os_mem_alloc(softs, 64);
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if (!buff)
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return PQI_STATUS_FAILURE;
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@ -621,7 +618,6 @@ static uint8_t pqisrc_get_volume_offline_status(pqisrc_softstate_t *softs,
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return status;
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}
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/* Determine offline status of a volume. Returns appropriate SA_LV_* status.*/
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static uint8_t pqisrc_get_dev_vol_status(pqisrc_softstate_t *softs,
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uint8_t *scsi3addr)
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@ -642,7 +638,7 @@ static uint8_t pqisrc_get_dev_vol_status(pqisrc_softstate_t *softs,
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memset(&request, 0, sizeof(request));
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ret = pqisrc_build_send_raid_request(softs, &request, NULL, 0,
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TEST_UNIT_READY, 0, scsi3addr, &error_info);
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if (ret)
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goto error;
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sense_data = error_info.data;
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@ -824,7 +820,7 @@ static void pqisrc_get_dev_ioaccel_status(pqisrc_softstate_t *softs,
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DBG_ERR("error in send scsi inquiry ret=%d\n", ret);
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goto err_out;
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}
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ioaccel_status = buff[IOACCEL_STATUS_BYTE];
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device->offload_config =
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!!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
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@ -835,7 +831,7 @@ static void pqisrc_get_dev_ioaccel_status(pqisrc_softstate_t *softs,
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if (pqisrc_get_device_raidmap(softs, device))
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device->offload_enabled_pending = false;
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}
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DBG_DISC("offload_config: 0x%x offload_enabled_pending: 0x%x \n",
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device->offload_config, device->offload_enabled_pending);
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@ -995,7 +991,6 @@ static int pqisrc_identify_physical_disk(pqisrc_softstate_t *softs,
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uint16_t bmic_device_index;
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pqisrc_raid_req_t request;
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DBG_FUNC("IN\n");
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memset(&request, 0, sizeof(request));
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@ -1046,7 +1041,6 @@ static void pqisrc_get_physical_device_info(pqisrc_softstate_t *softs,
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DBG_FUNC("OUT\n");
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}
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/* Function used to find the entry of the device in a list */
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static device_status_t pqisrc_scsi_find_entry(pqisrc_softstate_t *softs,
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pqi_scsi_dev_t *device_to_find,
|
||||
@ -1077,7 +1071,6 @@ static device_status_t pqisrc_scsi_find_entry(pqisrc_softstate_t *softs,
|
||||
return DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
|
||||
/* Update the newly added devices as existed device */
|
||||
static void pqisrc_exist_device_update(pqisrc_softstate_t *softs,
|
||||
pqi_scsi_dev_t *device_exist,
|
||||
@ -1241,7 +1234,6 @@ void pqisrc_remove_device(pqisrc_softstate_t *softs,
|
||||
DBG_FUNC("OUT\n");
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* When exposing new device to OS fails then adjst list according to the
|
||||
* mid scsi list
|
||||
@ -1331,7 +1323,7 @@ void pqisrc_device_mem_free(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
|
||||
}
|
||||
os_mem_free(softs, (char *)device,sizeof(*device));
|
||||
DBG_FUNC("OUT\n");
|
||||
|
||||
|
||||
}
|
||||
|
||||
/* OS should call this function to free the scsi device */
|
||||
@ -1347,7 +1339,6 @@ void pqisrc_free_device(pqisrc_softstate_t * softs,pqi_scsi_dev_t *device)
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* Update the newly added devices to the device list */
|
||||
static void pqisrc_update_device_list(pqisrc_softstate_t *softs,
|
||||
pqi_scsi_dev_t *new_device_list[], int num_new_devices)
|
||||
@ -1372,9 +1363,9 @@ static void pqisrc_update_device_list(pqisrc_softstate_t *softs,
|
||||
DBG_WARN("Out of memory \n");
|
||||
goto free_and_out;
|
||||
}
|
||||
|
||||
|
||||
OS_ACQUIRE_SPINLOCK(&softs->devlist_lock);
|
||||
|
||||
|
||||
for(i = 0; i < PQI_MAX_DEVICES; i++) {
|
||||
for(j = 0; j < PQI_MAX_MULTILUN; j++) {
|
||||
if(softs->device_list[i][j] == NULL)
|
||||
@ -1448,7 +1439,7 @@ static void pqisrc_update_device_list(pqisrc_softstate_t *softs,
|
||||
}
|
||||
|
||||
pqisrc_update_log_dev_qdepth(softs);
|
||||
|
||||
|
||||
for(i = 0; i < PQI_MAX_DEVICES; i++) {
|
||||
for(j = 0; j < PQI_MAX_MULTILUN; j++) {
|
||||
if(softs->device_list[i][j] == NULL)
|
||||
@ -1571,7 +1562,7 @@ int pqisrc_write_driver_version_to_host_wellness(pqisrc_softstate_t *softs)
|
||||
BMIC_WRITE_HOST_WELLNESS, 0, (uint8_t *)RAID_CTLR_LUNID, NULL);
|
||||
|
||||
os_mem_free(softs, (char *)host_wellness_driver_ver, data_length);
|
||||
|
||||
|
||||
DBG_FUNC("OUT");
|
||||
return rval;
|
||||
}
|
||||
@ -1613,10 +1604,10 @@ int pqisrc_write_current_time_to_host_wellness(pqisrc_softstate_t *softs)
|
||||
host_wellness_time->dont_write_tag[1] = 'W';
|
||||
host_wellness_time->end_tag[0] = 'Z';
|
||||
host_wellness_time->end_tag[1] = 'Z';
|
||||
|
||||
|
||||
rval = pqisrc_build_send_raid_request(softs, &request, host_wellness_time,data_length,
|
||||
BMIC_WRITE_HOST_WELLNESS, 0, (uint8_t *)RAID_CTLR_LUNID, NULL);
|
||||
|
||||
|
||||
os_mem_free(softs, (char *)host_wellness_time, data_length);
|
||||
|
||||
DBG_FUNC("OUT");
|
||||
@ -1645,7 +1636,6 @@ int pqisrc_scan_devices(pqisrc_softstate_t *softs)
|
||||
bmic_ident_physdev_t *bmic_phy_info = NULL;
|
||||
pqi_scsi_dev_t **new_device_list = NULL;
|
||||
pqi_scsi_dev_t *device = NULL;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
@ -1657,7 +1647,7 @@ int pqisrc_scan_devices(pqisrc_softstate_t *softs)
|
||||
|
||||
physical_cnt = BE_32(physical_dev_list->header.list_length)
|
||||
/ sizeof(physical_dev_list->lun_entries[0]);
|
||||
|
||||
|
||||
logical_cnt = BE_32(logical_dev_list->header.list_length)
|
||||
/ sizeof(logical_dev_list->lun_entries[0]);
|
||||
|
||||
@ -1695,7 +1685,6 @@ int pqisrc_scan_devices(pqisrc_softstate_t *softs)
|
||||
ndev_allocated = phy_log_dev_cnt;
|
||||
new_dev_cnt = 0;
|
||||
for (i = 0; i < phy_log_dev_cnt; i++) {
|
||||
|
||||
if (i < physical_cnt) {
|
||||
is_physical_device = true;
|
||||
lun_ext_entry = &physical_dev_list->lun_entries[i];
|
||||
@ -1803,7 +1792,7 @@ int pqisrc_scan_devices(pqisrc_softstate_t *softs)
|
||||
DBG_DISC("new_dev_cnt %d\n", new_dev_cnt);
|
||||
|
||||
pqisrc_update_device_list(softs, new_device_list, new_dev_cnt);
|
||||
|
||||
|
||||
err_out:
|
||||
if (new_device_list) {
|
||||
for (i = 0; i < ndev_allocated; i++) {
|
||||
@ -1824,7 +1813,7 @@ int pqisrc_scan_devices(pqisrc_softstate_t *softs)
|
||||
os_mem_free(softs, (char *)logical_dev_list, log_data_length);
|
||||
if (bmic_phy_info)
|
||||
os_mem_free(softs, (char *)bmic_phy_info, sizeof(*bmic_phy_info));
|
||||
|
||||
|
||||
DBG_FUNC("OUT \n");
|
||||
|
||||
return ret;
|
||||
@ -1839,7 +1828,7 @@ void pqisrc_cleanup_devices(pqisrc_softstate_t *softs)
|
||||
int i = 0,j = 0;
|
||||
pqi_scsi_dev_t *dvp = NULL;
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
for(i = 0; i < PQI_MAX_DEVICES; i++) {
|
||||
for(j = 0; j < PQI_MAX_MULTILUN; j++) {
|
||||
if (softs->device_list[i][j] == NULL)
|
||||
@ -1850,4 +1839,3 @@ void pqisrc_cleanup_devices(pqisrc_softstate_t *softs)
|
||||
}
|
||||
DBG_FUNC("OUT\n");
|
||||
}
|
||||
|
||||
|
@ -35,15 +35,15 @@ int
|
||||
pqisrc_rescan_devices(pqisrc_softstate_t *softs)
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
os_sema_lock(&softs->scan_lock);
|
||||
|
||||
|
||||
ret = pqisrc_scan_devices(softs);
|
||||
|
||||
os_sema_unlock(&softs->scan_lock);
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
|
||||
return ret;
|
||||
@ -62,7 +62,7 @@ static void
|
||||
pqisrc_acknowledge_event(pqisrc_softstate_t *softs,
|
||||
struct pqi_event *event)
|
||||
{
|
||||
|
||||
|
||||
pqi_event_acknowledge_request_t request;
|
||||
ib_queue_t *ib_q = &softs->op_raid_ib_q[0];
|
||||
int tmo = PQISRC_EVENT_ACK_RESP_TIMEOUT;
|
||||
@ -93,7 +93,7 @@ pqisrc_acknowledge_event(pqisrc_softstate_t *softs,
|
||||
DBG_ERR("wait for event acknowledge timed out\n");
|
||||
DBG_ERR("tmo : %d\n",tmo);
|
||||
}
|
||||
|
||||
|
||||
DBG_FUNC(" OUT\n");
|
||||
}
|
||||
|
||||
@ -109,7 +109,6 @@ pqisrc_ack_all_events(void *arg1)
|
||||
|
||||
DBG_FUNC(" IN\n");
|
||||
|
||||
|
||||
pending_event = &softs->pending_events[0];
|
||||
for (i=0; i < PQI_NUM_SUPPORTED_EVENTS; i++) {
|
||||
if (pending_event->pending == true) {
|
||||
@ -118,13 +117,13 @@ pqisrc_ack_all_events(void *arg1)
|
||||
}
|
||||
pending_event++;
|
||||
}
|
||||
|
||||
|
||||
/* Rescan devices except for heartbeat event */
|
||||
if ((pqisrc_rescan_devices(softs)) != PQI_STATUS_SUCCESS) {
|
||||
DBG_ERR(" Failed to Re-Scan devices\n ");
|
||||
}
|
||||
DBG_FUNC(" OUT\n");
|
||||
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
@ -173,16 +172,16 @@ pqisrc_process_event_intr_src(pqisrc_softstate_t *softs,int obq_id)
|
||||
ob_queue_t *event_q;
|
||||
struct pqi_event *pending_event;
|
||||
boolean_t need_delayed_work = false;
|
||||
|
||||
|
||||
DBG_FUNC(" IN\n");
|
||||
|
||||
|
||||
OS_ATOMIC64_INC(softs, num_intrs);
|
||||
|
||||
|
||||
event_q = &softs->event_q;
|
||||
obq_ci = event_q->ci_local;
|
||||
obq_pi = *(event_q->pi_virt_addr);
|
||||
DBG_INFO("Initial Event_q ci : %d Event_q pi : %d\n", obq_ci, obq_pi);
|
||||
|
||||
|
||||
while(1) {
|
||||
int event_index;
|
||||
DBG_INFO("queue_id : %d ci : %d pi : %d\n",obq_id, obq_ci, obq_pi);
|
||||
@ -223,7 +222,6 @@ pqisrc_process_event_intr_src(pqisrc_softstate_t *softs,int obq_id)
|
||||
|
||||
DBG_FUNC("OUT");
|
||||
return PQI_STATUS_SUCCESS;
|
||||
|
||||
|
||||
}
|
||||
|
||||
@ -236,7 +234,7 @@ int pqisrc_submit_management_req(pqisrc_softstate_t *softs,
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
ib_queue_t *op_ib_q = &softs->op_raid_ib_q[0];
|
||||
rcb_t *rcb = NULL;
|
||||
|
||||
|
||||
DBG_FUNC(" IN\n");
|
||||
|
||||
/* Get the tag */
|
||||
@ -267,7 +265,7 @@ int pqisrc_submit_management_req(pqisrc_softstate_t *softs,
|
||||
pqisrc_put_tag(&softs->taglist,request->request_id);
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
|
||||
|
||||
err_cmd:
|
||||
os_reset_rcb(rcb);
|
||||
pqisrc_put_tag(&softs->taglist,request->request_id);
|
||||
@ -285,9 +283,9 @@ pqi_event_configure(pqisrc_softstate_t *softs ,
|
||||
dma_mem_t *buff)
|
||||
{
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
|
||||
|
||||
DBG_FUNC(" IN\n");
|
||||
|
||||
|
||||
request->header.comp_feature = 0x00;
|
||||
request->header.iu_length = sizeof(pqi_event_config_request_t) -
|
||||
PQI_REQUEST_HEADER_LENGTH; /* excluding IU header length */
|
||||
@ -304,7 +302,6 @@ pqi_event_configure(pqisrc_softstate_t *softs ,
|
||||
ret = pqisrc_submit_management_req(softs,request);
|
||||
if(ret)
|
||||
goto err_out;
|
||||
|
||||
|
||||
DBG_FUNC(" OUT\n");
|
||||
return ret;
|
||||
@ -328,14 +325,14 @@ int pqisrc_report_event_config(pqisrc_softstate_t *softs)
|
||||
/*bytes to be allocaed for report event config data-in buffer */
|
||||
uint32_t alloc_size = sizeof(pqi_event_config_t) ;
|
||||
memset(&request, 0 , sizeof(request));
|
||||
|
||||
|
||||
DBG_FUNC(" IN\n");
|
||||
|
||||
|
||||
memset(&buf_report_event, 0, sizeof(struct dma_mem));
|
||||
buf_report_event.tag = "pqi_report_event_buf" ;
|
||||
buf_report_event.size = alloc_size;
|
||||
buf_report_event.align = PQISRC_DEFAULT_DMA_ALIGN;
|
||||
|
||||
|
||||
/* allocate memory */
|
||||
ret = os_dma_mem_alloc(softs, &buf_report_event);
|
||||
if (ret) {
|
||||
@ -346,13 +343,13 @@ int pqisrc_report_event_config(pqisrc_softstate_t *softs)
|
||||
DBG_INFO("buf_report_event.virt_addr = %p \n",(void*)buf_report_event.virt_addr);
|
||||
|
||||
request.header.iu_type = PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG;
|
||||
|
||||
|
||||
/* Event configuration */
|
||||
ret=pqi_event_configure(softs,&request,&buf_report_event);
|
||||
if(ret)
|
||||
goto free_mem;
|
||||
|
||||
|
||||
|
||||
event_config_p = (pqi_event_config_t*)buf_report_event.virt_addr;
|
||||
softs->event_config.num_event_descriptors = MIN(event_config_p->num_event_descriptors,
|
||||
PQI_MAX_EVENT_DESCRIPTORS) ;
|
||||
@ -415,7 +412,6 @@ int pqisrc_set_event_config(pqisrc_softstate_t *softs)
|
||||
|
||||
event_config_p->num_event_descriptors = softs->event_config.num_event_descriptors;
|
||||
|
||||
|
||||
for (i=0; i < softs->event_config.num_event_descriptors ; i++){
|
||||
event_config_p->descriptors[i].event_type =
|
||||
softs->event_config.descriptors[i].event_type;
|
||||
@ -424,7 +420,6 @@ int pqisrc_set_event_config(pqisrc_softstate_t *softs)
|
||||
else
|
||||
event_config_p->descriptors[i].oq_id = 0; /* Not supported this event. */
|
||||
|
||||
|
||||
}
|
||||
/* Event configuration */
|
||||
ret = pqi_event_configure(softs,&request,&buf_set_event);
|
||||
@ -435,7 +430,7 @@ int pqisrc_set_event_config(pqisrc_softstate_t *softs)
|
||||
|
||||
DBG_FUNC(" OUT\n");
|
||||
return ret;
|
||||
|
||||
|
||||
free_mem:
|
||||
os_dma_mem_free(softs, &buf_set_event);
|
||||
err_out:
|
||||
|
@ -47,18 +47,18 @@ void pqisrc_configure_legacy_intx(pqisrc_softstate_t *softs, boolean_t enable_in
|
||||
{
|
||||
uint32_t intx_mask;
|
||||
uint32_t *reg_addr = NULL;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
if (enable_intx)
|
||||
reg_addr = &softs->pqi_reg->legacy_intr_mask_clr;
|
||||
else
|
||||
reg_addr = &softs->pqi_reg->legacy_intr_mask_set;
|
||||
|
||||
|
||||
intx_mask = PCI_MEM_GET32(softs, reg_addr, PQI_LEGACY_INTR_MASK_CLR);
|
||||
intx_mask |= PQISRC_LEGACY_INTX_MASK;
|
||||
PCI_MEM_PUT32(softs, reg_addr, PQI_LEGACY_INTR_MASK_CLR ,intx_mask);
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
}
|
||||
|
||||
@ -150,12 +150,11 @@ void pqisrc_heartbeat_timer_handler(pqisrc_softstate_t *softs)
|
||||
* Conditional variable management routine for internal commands.
|
||||
*/
|
||||
int pqisrc_wait_on_condition(pqisrc_softstate_t *softs, rcb_t *rcb){
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
uint32_t loop_cnt = 0;
|
||||
|
||||
|
||||
while (rcb->req_pending == true) {
|
||||
OS_SLEEP(500); /* Micro sec */
|
||||
|
||||
@ -170,13 +169,12 @@ int pqisrc_wait_on_condition(pqisrc_softstate_t *softs, rcb_t *rcb){
|
||||
ret = PQI_STATUS_TIMEOUT;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
if (pqisrc_ctrl_offline(softs)) {
|
||||
DBG_ERR("Controller is Offline");
|
||||
ret = PQI_STATUS_FAILURE;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
rcb->req_pending = true;
|
||||
|
||||
|
@ -78,12 +78,9 @@
|
||||
#include <vm/vm.h>
|
||||
#include <vm/pmap.h>
|
||||
|
||||
|
||||
|
||||
#include "smartpqi_defines.h"
|
||||
#include "smartpqi_structures.h"
|
||||
#include "smartpqi_prototypes.h"
|
||||
#include "smartpqi_ioctl.h"
|
||||
|
||||
|
||||
#endif // _PQI_INCLUDES_H
|
||||
|
@ -34,7 +34,7 @@
|
||||
static int pqisrc_report_pqi_capability(pqisrc_softstate_t *softs)
|
||||
{
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
gen_adm_req_iu_t admin_req;
|
||||
@ -64,7 +64,7 @@ static int pqisrc_report_pqi_capability(pqisrc_softstate_t *softs)
|
||||
DBG_ERR("Failed to allocate capability DMA buffer : %d\n", ret);
|
||||
goto err_dma_alloc;
|
||||
}
|
||||
|
||||
|
||||
admin_req.fn_code = PQI_FUNCTION_REPORT_DEV_CAP;
|
||||
admin_req.req_type.general_func.buf_size = pqi_cap_dma_buf.size;
|
||||
admin_req.req_type.general_func.sg_desc.length = pqi_cap_dma_buf.size;
|
||||
@ -107,7 +107,6 @@ static int pqisrc_report_pqi_capability(pqisrc_softstate_t *softs)
|
||||
DBG_INIT("softs->max_ib_iu_length_per_fw: %d\n", softs->max_ib_iu_length_per_fw);
|
||||
DBG_INIT("softs->ib_spanning_supported: %d\n", softs->ib_spanning_supported);
|
||||
DBG_INIT("softs->ob_spanning_supported: %d\n", softs->ob_spanning_supported);
|
||||
|
||||
|
||||
os_mem_free(softs, (void *)capability,
|
||||
REPORT_PQI_DEV_CAP_DATA_BUF_SIZE);
|
||||
@ -132,7 +131,7 @@ static int pqisrc_report_pqi_capability(pqisrc_softstate_t *softs)
|
||||
*/
|
||||
void pqisrc_free_rcb(pqisrc_softstate_t *softs, int req_count)
|
||||
{
|
||||
|
||||
|
||||
uint32_t num_req;
|
||||
size_t size;
|
||||
int i;
|
||||
@ -147,7 +146,6 @@ void pqisrc_free_rcb(pqisrc_softstate_t *softs, int req_count)
|
||||
DBG_FUNC("OUT\n");
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Allocate memory for rcb and SG descriptors.
|
||||
*/
|
||||
@ -181,7 +179,7 @@ static int pqisrc_allocate_rcb(pqisrc_softstate_t *softs)
|
||||
goto err_out;
|
||||
}
|
||||
softs->rcb = rcb;
|
||||
|
||||
|
||||
/* Allocate sg dma memory for sg chain */
|
||||
sg_buf_size = softs->pqi_cap.max_sg_elem *
|
||||
sizeof(sgt_t);
|
||||
@ -227,7 +225,7 @@ void pqisrc_decide_opq_config(pqisrc_softstate_t *softs)
|
||||
|
||||
DBG_INIT("softs->intr_count : %d softs->num_cpus_online : %d",
|
||||
softs->intr_count, softs->num_cpus_online);
|
||||
|
||||
|
||||
if (softs->intr_count == 1 || softs->num_cpus_online == 1) {
|
||||
/* Share the event and Operational queue. */
|
||||
softs->num_op_obq = 1;
|
||||
@ -247,7 +245,7 @@ void pqisrc_decide_opq_config(pqisrc_softstate_t *softs)
|
||||
*/
|
||||
if (softs->intr_count > 1)
|
||||
softs->share_opq_and_eventq = false;
|
||||
|
||||
|
||||
DBG_INIT("softs->num_op_obq : %d\n",softs->num_op_obq);
|
||||
|
||||
softs->num_op_raid_ibq = softs->num_op_obq;
|
||||
@ -270,11 +268,11 @@ void pqisrc_decide_opq_config(pqisrc_softstate_t *softs)
|
||||
Max.Outstanding IO and Max.Spanning element */
|
||||
total_iq_elements = (softs->max_outstanding_io *
|
||||
(softs->max_ib_iu_length / softs->ibq_elem_size));
|
||||
|
||||
|
||||
softs->num_elem_per_op_ibq = total_iq_elements / softs->num_op_raid_ibq;
|
||||
softs->num_elem_per_op_ibq = MIN(softs->num_elem_per_op_ibq,
|
||||
softs->pqi_dev_cap.max_iq_elements);
|
||||
|
||||
|
||||
softs->num_elem_per_op_obq = softs->max_outstanding_io / softs->num_op_obq;
|
||||
softs->num_elem_per_op_obq = MIN(softs->num_elem_per_op_obq,
|
||||
softs->pqi_dev_cap.max_oq_elements);
|
||||
@ -298,7 +296,7 @@ void pqisrc_decide_opq_config(pqisrc_softstate_t *softs)
|
||||
int pqisrc_configure_op_queues(pqisrc_softstate_t *softs)
|
||||
{
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
|
||||
|
||||
/* Get the PQI capability,
|
||||
REPORT PQI DEVICE CAPABILITY request */
|
||||
ret = pqisrc_report_pqi_capability(softs);
|
||||
@ -313,7 +311,7 @@ int pqisrc_configure_op_queues(pqisrc_softstate_t *softs)
|
||||
|
||||
/* Decide the Op queue configuration */
|
||||
pqisrc_decide_opq_config(softs);
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
|
||||
@ -364,7 +362,6 @@ int pqisrc_check_pqimode(pqisrc_softstate_t *softs)
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
|
||||
tmo = PQISRC_PQIMODE_READY_TIMEOUT;
|
||||
/* Check the PQI device status register */
|
||||
COND_WAIT(LE_32(PCI_MEM_GET32(softs, &softs->pqi_reg->pqi_dev_status, PQI_DEV_STATUS)) &
|
||||
@ -417,7 +414,6 @@ int pqisrc_process_config_table(pqisrc_softstate_t *softs)
|
||||
softs->pqi_cap.conf_tab_off,
|
||||
(uint8_t*)conf_table, config_table_size);
|
||||
|
||||
|
||||
if (memcmp(conf_table->sign, PQI_CONF_TABLE_SIGNATURE,
|
||||
sizeof(conf_table->sign)) != 0) {
|
||||
DBG_ERR("Invalid PQI config signature\n");
|
||||
@ -427,7 +423,6 @@ int pqisrc_process_config_table(pqisrc_softstate_t *softs)
|
||||
section_off = LE_32(conf_table->first_section_off);
|
||||
|
||||
while (section_off) {
|
||||
|
||||
if (section_off+ sizeof(*section_hdr) >= config_table_size) {
|
||||
DBG_ERR("PQI config table section offset (%u) beyond \
|
||||
end of config table (config table length: %u)\n",
|
||||
@ -505,7 +500,7 @@ int pqi_reset(pqisrc_softstate_t *softs)
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
if (true == softs->ctrl_in_pqi_mode) {
|
||||
|
||||
|
||||
if (softs->pqi_reset_quiesce_allowed) {
|
||||
val = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
|
||||
LEGACY_SIS_IDBR);
|
||||
@ -555,7 +550,7 @@ int pqisrc_pqi_init(pqisrc_softstate_t *softs)
|
||||
|
||||
PQI_SAVE_CTRL_MODE(softs, CTRL_PQI_MODE);
|
||||
softs->ctrl_in_pqi_mode = true;
|
||||
|
||||
|
||||
/* Get the No. of Online CPUs,NUMA/Processor config from OS */
|
||||
ret = os_get_processor_config(softs);
|
||||
if (ret) {
|
||||
@ -563,7 +558,7 @@ int pqisrc_pqi_init(pqisrc_softstate_t *softs)
|
||||
ret);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
|
||||
softs->intr_type = INTR_TYPE_NONE;
|
||||
|
||||
/* Get the interrupt count, type, priority available from OS */
|
||||
@ -682,7 +677,7 @@ int pqisrc_wait_for_cmnd_complete(pqisrc_softstate_t *softs)
|
||||
{
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
int tmo = PQI_CMND_COMPLETE_TMO;
|
||||
|
||||
|
||||
COND_WAIT((softs->taglist.num_elem == softs->max_outstanding_io), tmo);
|
||||
if (!tmo) {
|
||||
DBG_ERR("Pending commands %x!!!",softs->taglist.num_elem);
|
||||
@ -695,7 +690,7 @@ void pqisrc_complete_internal_cmds(pqisrc_softstate_t *softs)
|
||||
{
|
||||
int tag = 0;
|
||||
rcb_t *rcb;
|
||||
|
||||
|
||||
for (tag = 1; tag <= softs->max_outstanding_io; tag++) {
|
||||
rcb = &softs->rcb[tag];
|
||||
if(rcb->req_pending && is_internal_req(rcb)) {
|
||||
@ -713,13 +708,13 @@ void pqisrc_pqi_uninit(pqisrc_softstate_t *softs)
|
||||
int i, ret;
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
/* Wait for any rescan to finish */
|
||||
pqisrc_wait_for_rescan_complete(softs);
|
||||
|
||||
/* Wait for commands to complete */
|
||||
ret = pqisrc_wait_for_cmnd_complete(softs);
|
||||
|
||||
|
||||
/* Complete all pending commands. */
|
||||
if(ret != PQI_STATUS_SUCCESS) {
|
||||
pqisrc_complete_internal_cmds(softs);
|
||||
@ -749,7 +744,7 @@ void pqisrc_pqi_uninit(pqisrc_softstate_t *softs)
|
||||
os_dma_mem_free(softs, &softs->op_ibq_dma_mem);
|
||||
os_dma_mem_free(softs, &softs->op_obq_dma_mem);
|
||||
os_dma_mem_free(softs, &softs->event_q_dma_mem);
|
||||
|
||||
|
||||
/* Free rcb */
|
||||
pqisrc_free_rcb(softs, softs->max_outstanding_io + 1);
|
||||
|
||||
@ -848,11 +843,10 @@ int pqisrc_init(pqisrc_softstate_t *softs)
|
||||
goto err_lock;
|
||||
}
|
||||
softs->devlist_lockcreated = true;
|
||||
|
||||
|
||||
OS_ATOMIC64_SET(softs, num_intrs, 0);
|
||||
softs->prev_num_intrs = softs->num_intrs;
|
||||
|
||||
|
||||
/* Get the PQI configuration table to read heart-beat counter*/
|
||||
if (PQI_NEW_HEARTBEAT_MECHANISM(softs)) {
|
||||
ret = pqisrc_process_config_table(softs);
|
||||
@ -864,7 +858,7 @@ int pqisrc_init(pqisrc_softstate_t *softs)
|
||||
|
||||
if (PQI_NEW_HEARTBEAT_MECHANISM(softs))
|
||||
softs->prev_heartbeat_count = CTRLR_HEARTBEAT_CNT(softs) - OS_FW_HEARTBEAT_TIMER_INTERVAL;
|
||||
|
||||
|
||||
/* Init device list */
|
||||
for(i = 0; i < PQI_MAX_DEVICES; i++)
|
||||
for(j = 0; j < PQI_MAX_MULTILUN; j++)
|
||||
@ -945,13 +939,13 @@ int pqisrc_flush_cache( pqisrc_softstate_t *softs,
|
||||
void pqisrc_uninit(pqisrc_softstate_t *softs)
|
||||
{
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
pqisrc_pqi_uninit(softs);
|
||||
|
||||
pqisrc_sis_uninit(softs);
|
||||
|
||||
os_destroy_semaphore(&softs->scan_lock);
|
||||
|
||||
|
||||
os_destroy_intr(softs);
|
||||
|
||||
pqisrc_cleanup_devices(softs);
|
||||
|
@ -28,7 +28,6 @@
|
||||
|
||||
#include "smartpqi_includes.h"
|
||||
|
||||
|
||||
/*
|
||||
* Function to get processor count
|
||||
*/
|
||||
@ -37,7 +36,7 @@ int os_get_processor_config(pqisrc_softstate_t *softs)
|
||||
DBG_FUNC("IN\n");
|
||||
softs->num_cpus_online = mp_ncpus;
|
||||
DBG_FUNC("OUT\n");
|
||||
|
||||
|
||||
return PQI_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
@ -118,7 +117,7 @@ static void shared_ithread_routine(void *arg)
|
||||
pqi_intr_ctx_t *intr_ctx = (pqi_intr_ctx_t *)arg;
|
||||
pqisrc_softstate_t *softs = device_get_softc(intr_ctx->pqi_dev);
|
||||
int oq_id = intr_ctx->oq_id;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
pqisrc_process_response_queue(softs, oq_id);
|
||||
@ -137,7 +136,7 @@ static void common_ithread_routine(void *arg)
|
||||
int oq_id = intr_ctx->oq_id;
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
pqisrc_process_response_queue(softs, oq_id);
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
@ -371,7 +370,7 @@ void deregister_pqi_msix(pqisrc_softstate_t *softs)
|
||||
int i = 0;
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
os_mem_free(softs, (char*)softs->os_specific.msi_ctx, sizeof(pqi_intr_ctx_t) * msix_count);
|
||||
softs->os_specific.msi_ctx = NULL;
|
||||
|
||||
@ -412,7 +411,7 @@ int os_destroy_intr(pqisrc_softstate_t *softs)
|
||||
pci_release_msi(dev);
|
||||
softs->os_specific.msi_enabled = FALSE;
|
||||
}
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
|
||||
return PQI_STATUS_SUCCESS;
|
||||
|
@ -57,7 +57,7 @@ static int smartpqi_open(struct cdev *cdev, int flags, int devtype,
|
||||
struct thread *td)
|
||||
{
|
||||
int error = PQI_STATUS_SUCCESS;
|
||||
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
@ -120,7 +120,6 @@ static void smartpqi_get_pci_info_ioctl(caddr_t udata, struct cdev *cdev)
|
||||
DBG_FUNC("OUT\n");
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* ioctl entry point for user
|
||||
*/
|
||||
@ -235,7 +234,7 @@ pqisrc_passthru_ioctl(struct pqisrc_softstate *softs, void *arg, int mode)
|
||||
|
||||
if (pqisrc_ctrl_offline(softs))
|
||||
return PQI_STATUS_FAILURE;
|
||||
|
||||
|
||||
if (!arg)
|
||||
return (PQI_STATUS_FAILURE);
|
||||
|
||||
@ -270,7 +269,7 @@ pqisrc_passthru_ioctl(struct pqisrc_softstate *softs, void *arg, int mode)
|
||||
|
||||
DBG_INFO("ioctl_dma_buf.dma_addr = %p\n",(void*)ioctl_dma_buf.dma_addr);
|
||||
DBG_INFO("ioctl_dma_buf.virt_addr = %p\n",(void*)ioctl_dma_buf.virt_addr);
|
||||
|
||||
|
||||
drv_buf = (char *)ioctl_dma_buf.virt_addr;
|
||||
if (iocommand->Request.Type.Direction & PQIIOCTL_WRITE) {
|
||||
if ((ret = os_copy_from_user(softs, (void *)drv_buf, (void *)iocommand->buf,
|
||||
@ -280,7 +279,7 @@ pqisrc_passthru_ioctl(struct pqisrc_softstate *softs, void *arg, int mode)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
request.header.iu_type = PQI_IU_TYPE_RAID_PATH_IO_REQUEST;
|
||||
request.header.iu_length = offsetof(pqisrc_raid_req_t, sg_descriptors[1]) -
|
||||
PQI_REQUEST_HEADER_LENGTH;
|
||||
@ -288,7 +287,7 @@ pqisrc_passthru_ioctl(struct pqisrc_softstate *softs, void *arg, int mode)
|
||||
sizeof(request.lun_number));
|
||||
memcpy(request.cdb, iocommand->Request.CDB, iocommand->Request.CDBLen);
|
||||
request.additional_cdb_bytes_usage = PQI_ADDITIONAL_CDB_BYTES_0;
|
||||
|
||||
|
||||
switch (iocommand->Request.Type.Direction) {
|
||||
case PQIIOCTL_NONE:
|
||||
request.data_direction = SOP_DATA_DIR_NONE;
|
||||
@ -341,7 +340,6 @@ pqisrc_passthru_ioctl(struct pqisrc_softstate *softs, void *arg, int mode)
|
||||
|
||||
memset(&iocommand->error_info, 0, sizeof(iocommand->error_info));
|
||||
|
||||
|
||||
if (rcb->status) {
|
||||
size_t sense_data_length;
|
||||
|
||||
@ -374,7 +372,6 @@ pqisrc_passthru_ioctl(struct pqisrc_softstate *softs, void *arg, int mode)
|
||||
|
||||
if (rcb->status == REQUEST_SUCCESS && iocommand->buf_size > 0 &&
|
||||
(iocommand->Request.Type.Direction & PQIIOCTL_READ)) {
|
||||
|
||||
if ((ret = os_copy_to_user(softs, (void*)iocommand->buf,
|
||||
(void*)drv_buf, iocommand->buf_size, mode)) != 0) {
|
||||
DBG_ERR("Failed to copy the response\n");
|
||||
|
@ -40,15 +40,12 @@
|
||||
#define PQIIOCTL_READ 0x02
|
||||
#define PQIIOCTL_BIDIRECTIONAL (PQIIOCTL_READ | PQIIOCTL_WRITE)
|
||||
|
||||
|
||||
/* Type defs used in the following structs */
|
||||
#define BYTE uint8_t
|
||||
#define WORD uint16_t
|
||||
#define HWORD uint16_t
|
||||
#define DWORD uint32_t
|
||||
|
||||
|
||||
|
||||
/* Command List Structure */
|
||||
typedef union _SCSI3Addr_struct {
|
||||
struct {
|
||||
@ -67,7 +64,7 @@ typedef union _SCSI3Addr_struct {
|
||||
BYTE Targ:6;
|
||||
BYTE Mode:2; /* b10 */
|
||||
} LogUnit;
|
||||
|
||||
|
||||
}OS_ATTRIBUTE_PACKED SCSI3Addr_struct;
|
||||
|
||||
typedef struct _PhysDevAddr_struct {
|
||||
@ -130,7 +127,6 @@ typedef struct _ErrorInfo_struct {
|
||||
|
||||
}OS_ATTRIBUTE_PACKED ErrorInfo_struct;
|
||||
|
||||
|
||||
typedef struct pqi_ioctl_passthruCmd_struct {
|
||||
LUNAddr_struct LUN_info;
|
||||
RequestBlock_struct Request;
|
||||
@ -140,5 +136,4 @@ typedef struct pqi_ioctl_passthruCmd_struct {
|
||||
|
||||
}OS_ATTRIBUTE_PACKED IOCTL_Command_struct;
|
||||
|
||||
|
||||
#endif /* _PQI_IOCTL_H_ */
|
||||
|
@ -133,7 +133,6 @@ struct pqi_ident
|
||||
{0x9005, 0x028f, 0x9005, 0x1201, PQI_HWIF_SRCV, "SmartRAID 3154-8i16e"},
|
||||
{0x9005, 0x028f, 0x9005, 0x1202, PQI_HWIF_SRCV, "SmartRAID 3154-8i8e"},
|
||||
{0x9005, 0x028f, 0x1bd4, 0x0047, PQI_HWIF_SRCV, "INSPUR RAID 8240-24i"},
|
||||
|
||||
{0, 0, 0, 0, 0, 0}
|
||||
};
|
||||
|
||||
@ -202,7 +201,6 @@ void pqisrc_save_controller_info(struct pqisrc_softstate *softs)
|
||||
softs->func_id = (uint32_t)pci_get_function(dev);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Allocate resources for our device, set up the bus interface.
|
||||
* Initialize the PQI related functionality, scan devices, register sim to
|
||||
@ -312,7 +310,7 @@ smartpqi_attach(device_t dev)
|
||||
|
||||
softs->os_specific.sim_registered = FALSE;
|
||||
softs->os_name = "FreeBSD ";
|
||||
|
||||
|
||||
/* Initialize the PQI library */
|
||||
error = pqisrc_init(softs);
|
||||
if (error) {
|
||||
@ -421,7 +419,7 @@ smartpqi_detach(device_t dev)
|
||||
pqisrc_uninit(softs);
|
||||
deregister_sim(softs);
|
||||
pci_release_msi(dev);
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return 0;
|
||||
}
|
||||
|
@ -123,7 +123,6 @@ void os_dma_mem_free(pqisrc_softstate_t *softs, struct dma_mem *dma_mem)
|
||||
/* DBG_FUNC("OUT\n"); */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Mem resource allocation wrapper function
|
||||
*/
|
||||
|
@ -39,7 +39,6 @@ void os_get_time(struct bmic_host_wellness_time *host_wellness_time)
|
||||
getnanotime(&ts);
|
||||
clock_ts_to_ct(&ts, &ct);
|
||||
|
||||
|
||||
/* Fill the time In BCD Format */
|
||||
host_wellness_time->hour= (uint8_t)bin2bcd(ct.hour);
|
||||
host_wellness_time->min = (uint8_t)bin2bcd(ct.min);
|
||||
@ -61,7 +60,6 @@ void os_wellness_periodic(void *data)
|
||||
struct pqisrc_softstate *softs = (struct pqisrc_softstate *)data;
|
||||
int ret = 0;
|
||||
|
||||
|
||||
/* update time to FW */
|
||||
if (!pqisrc_ctrl_offline(softs)){
|
||||
if( (ret = pqisrc_write_current_time_to_host_wellness(softs)) != 0 )
|
||||
@ -161,7 +159,6 @@ void inline os_sema_unlock(struct sema *sema)
|
||||
sema_wait(sema);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* string copy wrapper function
|
||||
*/
|
||||
|
@ -119,14 +119,11 @@ void pqisrc_process_raid_response_error(pqisrc_softstate_t *,
|
||||
rcb_t *, uint16_t);
|
||||
void pqisrc_process_response_queue(pqisrc_softstate_t *, int);
|
||||
|
||||
|
||||
/* pqi_request.c */
|
||||
int pqisrc_build_send_io(pqisrc_softstate_t *,rcb_t *);
|
||||
|
||||
|
||||
int pqisrc_send_scsi_cmd_raidbypass(pqisrc_softstate_t *softs,
|
||||
pqi_scsi_dev_t *device, rcb_t *rcb, uint8_t*);
|
||||
|
||||
|
||||
int pqisrc_send_tmf(pqisrc_softstate_t *, pqi_scsi_dev_t *,
|
||||
rcb_t *, int, int);
|
||||
@ -139,7 +136,6 @@ int pqisrc_set_event_config(pqisrc_softstate_t *);
|
||||
int pqisrc_process_event_intr_src(pqisrc_softstate_t *,int);
|
||||
void pqisrc_ack_all_events(void *arg);
|
||||
|
||||
|
||||
void pqisrc_event_worker(void *, int);
|
||||
int pqisrc_scsi_setup(struct pqisrc_softstate *);
|
||||
void pqisrc_scsi_cleanup(struct pqisrc_softstate *);
|
||||
@ -194,13 +190,11 @@ int pqisrc_process_task_management_response(pqisrc_softstate_t *,
|
||||
pqi_tmf_resp_t *);
|
||||
void pqisrc_wait_for_rescan_complete(pqisrc_softstate_t *softs);
|
||||
|
||||
|
||||
/* pqi_ioctl.c*/
|
||||
|
||||
int
|
||||
pqisrc_passthru_ioctl(struct pqisrc_softstate *, void *, int);
|
||||
|
||||
|
||||
/* Functions Prototypes */
|
||||
/* FreeBSD_mem.c */
|
||||
int os_dma_mem_alloc(pqisrc_softstate_t *,struct dma_mem *);
|
||||
@ -223,7 +217,7 @@ int os_copy_from_user(struct pqisrc_softstate *, void *,
|
||||
void *, int, int);
|
||||
int create_char_dev(struct pqisrc_softstate *, int);
|
||||
void destroy_char_dev(struct pqisrc_softstate *);
|
||||
|
||||
|
||||
/* FreeBSD_misc.c*/
|
||||
int os_init_spinlock(struct pqisrc_softstate *, struct mtx *, char *);
|
||||
void os_uninit_spinlock(struct mtx *);
|
||||
|
@ -39,7 +39,7 @@ int pqisrc_submit_admin_req(pqisrc_softstate_t *softs,
|
||||
ob_queue_t *ob_q = &softs->admin_ob_queue;
|
||||
ib_queue_t *ib_q = &softs->admin_ib_queue;
|
||||
int tmo = PQISRC_ADMIN_CMD_RESP_TIMEOUT;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
req->header.iu_type =
|
||||
@ -48,7 +48,7 @@ int pqisrc_submit_admin_req(pqisrc_softstate_t *softs,
|
||||
req->header.iu_length = PQI_STANDARD_IU_LENGTH;
|
||||
req->res1 = 0;
|
||||
req->work = 0;
|
||||
|
||||
|
||||
/* Get the tag */
|
||||
req->req_id = pqisrc_get_tag(&softs->taglist);
|
||||
if (INVALID_ELEM == req->req_id) {
|
||||
@ -57,7 +57,7 @@ int pqisrc_submit_admin_req(pqisrc_softstate_t *softs,
|
||||
goto err_out;
|
||||
}
|
||||
softs->rcb[req->req_id].tag = req->req_id;
|
||||
|
||||
|
||||
/* Submit the command to the admin ib queue */
|
||||
ret = pqisrc_submit_cmnd(softs, ib_q, req);
|
||||
if (ret != PQI_STATUS_SUCCESS) {
|
||||
@ -73,7 +73,7 @@ int pqisrc_submit_admin_req(pqisrc_softstate_t *softs,
|
||||
ret = PQI_STATUS_TIMEOUT;
|
||||
goto err_cmd;
|
||||
}
|
||||
|
||||
|
||||
/* Copy the response */
|
||||
memcpy(resp, ob_q->array_virt_addr + (ob_q->ci_local * ob_q->elem_size),
|
||||
sizeof(gen_adm_resp_iu_t));
|
||||
@ -82,7 +82,7 @@ int pqisrc_submit_admin_req(pqisrc_softstate_t *softs,
|
||||
ob_q->ci_local = (ob_q->ci_local + 1 ) % ob_q->num_elem;
|
||||
PCI_MEM_PUT32(softs, ob_q->ci_register_abs,
|
||||
ob_q->ci_register_offset, LE_32(ob_q->ci_local));
|
||||
|
||||
|
||||
/* Validate the response data */
|
||||
ASSERT(req->fn_code == resp->fn_code);
|
||||
ASSERT(resp->header.iu_type == PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE);
|
||||
@ -109,7 +109,6 @@ void pqisrc_get_admin_queue_config(pqisrc_softstate_t *softs)
|
||||
{
|
||||
uint64_t val = 0;
|
||||
|
||||
|
||||
val = LE_64(PCI_MEM_GET64(softs, &softs->pqi_reg->pqi_dev_adminq_cap, PQI_ADMINQ_CAP));
|
||||
|
||||
/* pqi_cap = (struct pqi_dev_adminq_cap *)&val;*/
|
||||
@ -118,7 +117,7 @@ void pqisrc_get_admin_queue_config(pqisrc_softstate_t *softs)
|
||||
/* Note : size in unit of 16 byte s*/
|
||||
softs->admin_ib_queue.elem_size = ((val & 0xFF0000) >> 16) * 16;
|
||||
softs->admin_ob_queue.elem_size = ((val & 0xFF000000) >> 24) * 16;
|
||||
|
||||
|
||||
DBG_FUNC(" softs->admin_ib_queue.num_elem : %d\n",
|
||||
softs->admin_ib_queue.num_elem);
|
||||
DBG_FUNC(" softs->admin_ib_queue.elem_size : %d\n",
|
||||
@ -153,7 +152,7 @@ int pqisrc_allocate_and_init_adminq(pqisrc_softstate_t *softs)
|
||||
|
||||
ib_array_size = (softs->admin_ib_queue.num_elem *
|
||||
softs->admin_ib_queue.elem_size);
|
||||
|
||||
|
||||
ob_array_size = (softs->admin_ob_queue.num_elem *
|
||||
softs->admin_ob_queue.elem_size);
|
||||
|
||||
@ -183,7 +182,7 @@ int pqisrc_allocate_and_init_adminq(pqisrc_softstate_t *softs)
|
||||
softs->admin_ob_queue.array_virt_addr = virt_addr + ib_array_size;
|
||||
softs->admin_ob_queue.array_dma_addr = dma_addr + ib_array_size;
|
||||
softs->admin_ob_queue.ci_local = 0;
|
||||
|
||||
|
||||
/* IB CI */
|
||||
softs->admin_ib_queue.ci_virt_addr =
|
||||
(uint32_t*)((uint8_t*)softs->admin_ob_queue.array_virt_addr
|
||||
@ -238,7 +237,7 @@ int pqisrc_create_delete_adminq(pqisrc_softstate_t *softs,
|
||||
tmo = PQISRC_ADMIN_QUEUE_CREATE_TIMEOUT;
|
||||
else
|
||||
tmo = PQISRC_ADMIN_QUEUE_DELETE_TIMEOUT;
|
||||
|
||||
|
||||
/* Wait for completion */
|
||||
COND_WAIT((PCI_MEM_GET64(softs, &softs->pqi_reg->admin_q_config, PQI_ADMINQ_CONFIG) ==
|
||||
PQI_ADMIN_QUEUE_CONF_FUNC_STATUS_IDLE), tmo);
|
||||
@ -299,7 +298,7 @@ int pqisrc_create_admin_queue(pqisrc_softstate_t *softs)
|
||||
DBG_ERR("Failed to Allocate Admin Q ret : %d\n", ret);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
|
||||
/* Write IB Q element array address */
|
||||
PCI_MEM_PUT64(softs, &softs->pqi_reg->admin_ibq_elem_array_addr,
|
||||
PQI_ADMIN_IBQ_ELEM_ARRAY_ADDR, LE_64(softs->admin_ib_queue.array_dma_addr));
|
||||
@ -316,7 +315,6 @@ int pqisrc_create_admin_queue(pqisrc_softstate_t *softs)
|
||||
PCI_MEM_PUT64(softs, &softs->pqi_reg->admin_obq_pi_addr,
|
||||
PQI_ADMIN_OBQ_PI_ADDR, LE_64(softs->admin_ob_queue.pi_dma_addr));
|
||||
|
||||
|
||||
/* Write Admin Q params pqi-r200a table 36 */
|
||||
|
||||
admin_q_param = softs->admin_ib_queue.num_elem |
|
||||
@ -333,7 +331,7 @@ int pqisrc_create_admin_queue(pqisrc_softstate_t *softs)
|
||||
DBG_ERR("Failed to Allocate Admin Q ret : %d\n", ret);
|
||||
goto err_q_create;
|
||||
}
|
||||
|
||||
|
||||
/* Admin queue created, get ci,pi offset */
|
||||
softs->admin_ib_queue.pi_register_offset =(PQISRC_PQI_REG_OFFSET +
|
||||
PCI_MEM_GET64(softs, &softs->pqi_reg->admin_ibq_pi_offset, PQI_ADMIN_IBQ_PI_OFFSET));
|
||||
@ -348,7 +346,7 @@ int pqisrc_create_admin_queue(pqisrc_softstate_t *softs)
|
||||
softs->admin_ob_queue.ci_register_offset);
|
||||
|
||||
os_strlcpy(softs->admin_ib_queue.lockname, "admin_ibqlock", LOCKNAME_SIZE);
|
||||
|
||||
|
||||
ret =OS_INIT_PQILOCK(softs, &softs->admin_ib_queue.lock,
|
||||
softs->admin_ib_queue.lockname);
|
||||
if(ret){
|
||||
@ -360,7 +358,7 @@ int pqisrc_create_admin_queue(pqisrc_softstate_t *softs)
|
||||
|
||||
/* Print admin q config details */
|
||||
pqisrc_print_adminq_config(softs);
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
|
||||
@ -385,7 +383,6 @@ int pqisrc_delete_op_queue(pqisrc_softstate_t *softs,
|
||||
gen_adm_req_iu_t admin_req;
|
||||
gen_adm_resp_iu_t admin_resp;
|
||||
|
||||
|
||||
memset(&admin_req, 0, sizeof(admin_req));
|
||||
memset(&admin_resp, 0, sizeof(admin_resp));
|
||||
|
||||
@ -397,10 +394,9 @@ int pqisrc_delete_op_queue(pqisrc_softstate_t *softs,
|
||||
admin_req.fn_code = PQI_FUNCTION_DELETE_OPERATIONAL_IQ;
|
||||
else
|
||||
admin_req.fn_code = PQI_FUNCTION_DELETE_OPERATIONAL_OQ;
|
||||
|
||||
|
||||
|
||||
ret = pqisrc_submit_admin_req(softs, &admin_req, &admin_resp);
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
#endif
|
||||
return ret;
|
||||
@ -421,7 +417,7 @@ void pqisrc_destroy_event_queue(pqisrc_softstate_t *softs)
|
||||
}
|
||||
softs->event_q.created = false;
|
||||
}
|
||||
|
||||
|
||||
/* Free the memory */
|
||||
os_dma_mem_free(softs, &softs->event_q_dma_mem);
|
||||
|
||||
@ -516,7 +512,7 @@ int pqisrc_destroy_admin_queue(pqisrc_softstate_t *softs)
|
||||
PQI_ADMIN_QUEUE_CONF_FUNC_DEL_Q_PAIR);
|
||||
#endif
|
||||
os_dma_mem_free(softs, &softs->admin_queue_dma_mem);
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
}
|
||||
@ -533,15 +529,15 @@ int pqisrc_change_op_ibq_queue_prop(pqisrc_softstate_t *softs,
|
||||
|
||||
memset(&admin_req, 0, sizeof(admin_req));
|
||||
memset(&admin_resp, 0, sizeof(admin_resp));
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
admin_req.fn_code = PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP;
|
||||
admin_req.req_type.change_op_iq_prop.qid = op_ib_q->q_id;
|
||||
admin_req.req_type.change_op_iq_prop.vend_specific = prop;
|
||||
|
||||
|
||||
ret = pqisrc_submit_admin_req(softs, &admin_req, &admin_resp);
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
}
|
||||
@ -611,9 +607,9 @@ int pqisrc_create_op_ibq(pqisrc_softstate_t *softs,
|
||||
admin_req.req_type.create_op_iq.iq_ci_addr = op_ib_q->ci_dma_addr;
|
||||
admin_req.req_type.create_op_iq.num_elem = op_ib_q->num_elem;
|
||||
admin_req.req_type.create_op_iq.elem_len = op_ib_q->elem_size / 16;
|
||||
|
||||
|
||||
ret = pqisrc_submit_admin_req(softs, &admin_req, &admin_resp);
|
||||
|
||||
|
||||
if( PQI_STATUS_SUCCESS == ret) {
|
||||
op_ib_q->pi_register_offset =(PQISRC_PQI_REG_OFFSET +
|
||||
admin_resp.resp_type.create_op_iq.pi_offset);
|
||||
@ -640,7 +636,7 @@ int pqisrc_create_op_aio_ibq(pqisrc_softstate_t *softs,
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
ret = pqisrc_create_op_ibq(softs,op_aio_ib_q);
|
||||
if ( PQI_STATUS_SUCCESS == ret)
|
||||
ret = pqisrc_change_op_ibq_queue_prop(softs,
|
||||
@ -657,11 +653,11 @@ int pqisrc_create_op_raid_ibq(pqisrc_softstate_t *softs,
|
||||
ib_queue_t *op_raid_ib_q)
|
||||
{
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
ret = pqisrc_create_op_ibq(softs,op_raid_ib_q);
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
}
|
||||
@ -680,7 +676,6 @@ int pqisrc_alloc_and_create_event_queue(pqisrc_softstate_t *softs)
|
||||
uint32_t event_q_pi_virt_start_offset = 0;
|
||||
char *event_q_pi_virt_start_addr = NULL;
|
||||
ob_queue_t *event_q = NULL;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
@ -719,7 +714,7 @@ int pqisrc_alloc_and_create_event_queue(pqisrc_softstate_t *softs)
|
||||
dma_addr = softs->event_q_dma_mem.dma_addr;
|
||||
event_q_pi_dma_start_offset += dma_addr;
|
||||
event_q_pi_virt_start_addr = virt_addr + event_q_pi_virt_start_offset;
|
||||
|
||||
|
||||
event_q = &softs->event_q;
|
||||
ASSERT(!(dma_addr & PQI_ADDR_ALIGN_MASK_64));
|
||||
FILL_QUEUE_ARRAY_ADDR(event_q,virt_addr,dma_addr);
|
||||
@ -740,7 +735,7 @@ int pqisrc_alloc_and_create_event_queue(pqisrc_softstate_t *softs)
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
|
||||
|
||||
err_out_create:
|
||||
pqisrc_destroy_event_queue(softs);
|
||||
err_out:
|
||||
@ -795,7 +790,7 @@ int pqisrc_alloc_and_create_ib_queues(pqisrc_softstate_t *softs)
|
||||
ib_ci_virt_start_addr = virt_addr + ib_ci_virt_start_offset;
|
||||
|
||||
ASSERT(softs->num_op_raid_ibq == softs->num_op_aio_ibq);
|
||||
|
||||
|
||||
for (i = 0; i < softs->num_op_raid_ibq; i++) {
|
||||
/* OP RAID IB Q */
|
||||
op_ib_q = &softs->op_raid_ib_q[i];
|
||||
@ -854,7 +849,7 @@ int pqisrc_alloc_and_create_ib_queues(pqisrc_softstate_t *softs)
|
||||
goto err_out_create;
|
||||
}
|
||||
op_ib_q->created = true;
|
||||
|
||||
|
||||
virt_addr += ibq_size;
|
||||
dma_addr += ibq_size;
|
||||
}
|
||||
@ -896,7 +891,7 @@ int pqisrc_alloc_and_create_ob_queues(pqisrc_softstate_t *softs)
|
||||
* of 4, so that OB Queue element size (16) * num elements
|
||||
* will be multiple of 64.
|
||||
*/
|
||||
|
||||
|
||||
ALIGN_BOUNDARY(softs->num_elem_per_op_obq, 4);
|
||||
obq_size = softs->num_elem_per_op_obq * softs->obq_elem_size;
|
||||
alloc_size += num_op_obq * obq_size;
|
||||
@ -950,10 +945,10 @@ int pqisrc_alloc_and_create_ob_queues(pqisrc_softstate_t *softs)
|
||||
virt_addr += obq_size;
|
||||
dma_addr += obq_size;
|
||||
}
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
|
||||
|
||||
err_out_create:
|
||||
pqisrc_destroy_op_ob_queues(softs);
|
||||
err_out:
|
||||
|
@ -47,7 +47,7 @@ uint32_t pqisrc_embedded_sgl_count(uint32_t elem_alloted)
|
||||
DBG_FUNC(" OUT ");
|
||||
|
||||
return embedded_sgl_count;
|
||||
|
||||
|
||||
}
|
||||
|
||||
/* Subroutine to find out contiguous free elem in IU */
|
||||
@ -141,13 +141,12 @@ boolean_t pqisrc_build_sgl(sgt_t *sg_array, rcb_t *rcb, iu_header_t *iu_hdr,
|
||||
sg_chain[num_sg - 1].flags = SG_FLAG_LAST;
|
||||
num_sg = 1;
|
||||
partial = true;
|
||||
|
||||
}
|
||||
out:
|
||||
iu_hdr->iu_length = num_sg * sizeof(sgt_t);
|
||||
DBG_FUNC(" OUT ");
|
||||
return partial;
|
||||
|
||||
|
||||
}
|
||||
|
||||
/*Subroutine used to Build the RAID request */
|
||||
@ -156,7 +155,7 @@ pqisrc_build_raid_io(pqisrc_softstate_t *softs, rcb_t *rcb,
|
||||
pqisrc_raid_req_t *raid_req, uint32_t num_elem_alloted)
|
||||
{
|
||||
DBG_FUNC(" IN ");
|
||||
|
||||
|
||||
raid_req->header.iu_type = PQI_IU_TYPE_RAID_PATH_IO_REQUEST;
|
||||
raid_req->header.comp_feature = 0;
|
||||
raid_req->response_queue_id = OS_GET_IO_RESP_QID(softs, rcb);
|
||||
@ -187,7 +186,7 @@ pqisrc_build_raid_io(pqisrc_softstate_t *softs, rcb_t *rcb,
|
||||
for(i = 0; i < rcb->cmdlen ; i++)
|
||||
DBG_IO(" 0x%x \n ",raid_req->cdb[i]);
|
||||
#endif
|
||||
|
||||
|
||||
switch (rcb->cmdlen) {
|
||||
case 6:
|
||||
case 10:
|
||||
@ -214,14 +213,14 @@ pqisrc_build_raid_io(pqisrc_softstate_t *softs, rcb_t *rcb,
|
||||
PQI_ADDITIONAL_CDB_BYTES_16;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/* Frame SGL Descriptor */
|
||||
raid_req->partial = pqisrc_build_sgl(&raid_req->sg_descriptors[0], rcb,
|
||||
&raid_req->header, num_elem_alloted);
|
||||
|
||||
raid_req->header.iu_length +=
|
||||
offsetof(pqisrc_raid_req_t, sg_descriptors) - sizeof(iu_header_t);
|
||||
|
||||
|
||||
#if 0
|
||||
DBG_IO("raid_req->header.iu_type : 0x%x", raid_req->header.iu_type);
|
||||
DBG_IO("raid_req->response_queue_id :%d\n"raid_req->response_queue_id);
|
||||
@ -237,9 +236,9 @@ pqisrc_build_raid_io(pqisrc_softstate_t *softs, rcb_t *rcb,
|
||||
rcb->success_cmp_callback = pqisrc_process_io_response_success;
|
||||
rcb->error_cmp_callback = pqisrc_process_raid_response_error;
|
||||
rcb->resp_qid = raid_req->response_queue_id;
|
||||
|
||||
|
||||
DBG_FUNC(" OUT ");
|
||||
|
||||
|
||||
}
|
||||
|
||||
/*Subroutine used to Build the AIO request */
|
||||
@ -278,7 +277,7 @@ pqisrc_build_aio_io(pqisrc_softstate_t *softs, rcb_t *rcb,
|
||||
#endif
|
||||
memset(aio_req->lun,0,sizeof(aio_req->lun));
|
||||
memset(aio_req->res4,0,sizeof(aio_req->res4));
|
||||
|
||||
|
||||
if(rcb->encrypt_enable == true) {
|
||||
aio_req->encrypt_enable = true;
|
||||
aio_req->encrypt_key_index = LE_16(rcb->enc_info.data_enc_key_index);
|
||||
@ -290,7 +289,7 @@ pqisrc_build_aio_io(pqisrc_softstate_t *softs, rcb_t *rcb,
|
||||
aio_req->encrypt_twk_high = 0;
|
||||
aio_req->encrypt_twk_low = 0;
|
||||
}
|
||||
|
||||
|
||||
/* Frame SGL Descriptor */
|
||||
aio_req->partial = pqisrc_build_sgl(&aio_req->sg_desc[0], rcb,
|
||||
&aio_req->header, num_elem_alloted);
|
||||
@ -298,7 +297,7 @@ pqisrc_build_aio_io(pqisrc_softstate_t *softs, rcb_t *rcb,
|
||||
aio_req->num_sg = aio_req->header.iu_length / sizeof(sgt_t);
|
||||
|
||||
DBG_INFO("aio_req->num_sg :%d",aio_req->num_sg);
|
||||
|
||||
|
||||
aio_req->header.iu_length += offsetof(pqi_aio_req_t, sg_desc) -
|
||||
sizeof(iu_header_t);
|
||||
#if 0
|
||||
@ -315,7 +314,7 @@ pqisrc_build_aio_io(pqisrc_softstate_t *softs, rcb_t *rcb,
|
||||
DBG_IO("aio_req->sg_desc[0].len : 0%x \n", aio_req->sg_desc[0].len);
|
||||
DBG_IO("aio_req->sg_desc[0].flags : 0%x \n", aio_req->sg_desc[0].flags);
|
||||
#endif
|
||||
|
||||
|
||||
rcb->success_cmp_callback = pqisrc_process_io_response_success;
|
||||
rcb->error_cmp_callback = pqisrc_process_aio_response_error;
|
||||
rcb->resp_qid = aio_req->response_queue_id;
|
||||
@ -339,12 +338,11 @@ int pqisrc_build_send_io(pqisrc_softstate_t *softs,rcb_t *rcb)
|
||||
uint32_t num_elem_alloted = 0;
|
||||
pqi_scsi_dev_t *devp = rcb->dvp;
|
||||
uint8_t raidbypass_cdb[16];
|
||||
|
||||
|
||||
DBG_FUNC(" IN ");
|
||||
|
||||
|
||||
rcb->cdbp = OS_GET_CDBP(rcb);
|
||||
|
||||
|
||||
if(IS_AIO_PATH(devp)) {
|
||||
/** IO for Physical Drive **/
|
||||
/** Send in AIO PATH**/
|
||||
@ -367,10 +365,10 @@ int pqisrc_build_send_io(pqisrc_softstate_t *softs,rcb_t *rcb)
|
||||
rcb->cdbp = raidbypass_cdb;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
num_elem_needed = pqisrc_num_elem_needed(softs, OS_GET_IO_SG_COUNT(rcb));
|
||||
DBG_IO("num_elem_needed :%d",num_elem_needed);
|
||||
|
||||
|
||||
do {
|
||||
uint32_t num_elem_available;
|
||||
ib_q = (ib_q_array + qindex);
|
||||
@ -394,16 +392,16 @@ int pqisrc_build_send_io(pqisrc_softstate_t *softs,rcb_t *rcb)
|
||||
num_elem_needed = 1;
|
||||
}
|
||||
}while(TraverseCount < 2);
|
||||
|
||||
|
||||
DBG_IO("num_elem_alloted :%d",num_elem_alloted);
|
||||
if (num_elem_alloted == 0) {
|
||||
DBG_WARN("OUT: IB Queues were full\n");
|
||||
return PQI_STATUS_QFULL;
|
||||
}
|
||||
|
||||
|
||||
/* Get IB Queue Slot address to build IU */
|
||||
ib_iu = ib_q->array_virt_addr + (ib_q->pi_local * ib_q->elem_size);
|
||||
|
||||
|
||||
if(io_path == AIO_PATH) {
|
||||
/** Build AIO structure **/
|
||||
pqisrc_build_aio_io(softs, rcb, (pqi_aio_req_t*)ib_iu,
|
||||
@ -413,9 +411,9 @@ int pqisrc_build_send_io(pqisrc_softstate_t *softs,rcb_t *rcb)
|
||||
pqisrc_build_raid_io(softs, rcb, (pqisrc_raid_req_t*)ib_iu,
|
||||
num_elem_alloted);
|
||||
}
|
||||
|
||||
|
||||
rcb->req_pending = true;
|
||||
|
||||
|
||||
/* Update the local PI */
|
||||
ib_q->pi_local = (ib_q->pi_local + num_elem_alloted) % ib_q->num_elem;
|
||||
|
||||
@ -424,7 +422,7 @@ int pqisrc_build_send_io(pqisrc_softstate_t *softs,rcb_t *rcb)
|
||||
|
||||
/* Inform the fw about the new IU */
|
||||
PCI_MEM_PUT32(softs, ib_q->pi_register_abs, ib_q->pi_register_offset, ib_q->pi_local);
|
||||
|
||||
|
||||
PQI_UNLOCK(&ib_q->lock);
|
||||
DBG_FUNC(" OUT ");
|
||||
return PQI_STATUS_SUCCESS;
|
||||
@ -452,7 +450,6 @@ static inline void pqisrc_set_enc_info(
|
||||
enc_info->encrypt_tweak_lower = ((uint32_t)(first_block));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Attempt to perform offload RAID mapping for a logical volume I/O.
|
||||
*/
|
||||
@ -470,7 +467,6 @@ static inline void pqisrc_set_enc_info(
|
||||
/* Subroutine used to parse the scsi opcode and build the CDB for RAID bypass*/
|
||||
int check_for_scsi_opcode(uint8_t *cdb, boolean_t *is_write, uint64_t *fst_blk,
|
||||
uint32_t *blk_cnt) {
|
||||
|
||||
switch (cdb[0]) {
|
||||
case SCMD_WRITE_6:
|
||||
*is_write = true;
|
||||
@ -540,7 +536,7 @@ int pqisrc_send_scsi_cmd_raidbypass(pqisrc_softstate_t *softs,
|
||||
|
||||
/* Check for eligible opcode, get LBA and block count. */
|
||||
memcpy(cdb, OS_GET_CDBP(rcb), rcb->cmdlen);
|
||||
|
||||
|
||||
for(i = 0; i < rcb->cmdlen ; i++)
|
||||
DBG_IO(" CDB [ %d ] : %x\n",i,cdb[i]);
|
||||
if(check_for_scsi_opcode(cdb, &is_write,
|
||||
@ -740,10 +736,10 @@ int pqisrc_send_scsi_cmd_raidbypass(pqisrc_softstate_t *softs,
|
||||
}
|
||||
|
||||
rcb->cmdlen = cdb_length;
|
||||
|
||||
|
||||
|
||||
DBG_FUNC("OUT");
|
||||
|
||||
|
||||
return PQI_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
|
@ -92,9 +92,9 @@ void pqisrc_process_aio_response_error(pqisrc_softstate_t *softs,
|
||||
rcb_t *rcb, uint16_t err_idx)
|
||||
{
|
||||
aio_path_error_info_elem_t *err_info = NULL;
|
||||
|
||||
|
||||
DBG_FUNC("IN");
|
||||
|
||||
|
||||
err_info = (aio_path_error_info_elem_t*)
|
||||
softs->err_buf_dma_mem.virt_addr +
|
||||
err_idx;
|
||||
@ -103,7 +103,7 @@ void pqisrc_process_aio_response_error(pqisrc_softstate_t *softs,
|
||||
DBG_ERR("err_info structure is NULL err_idx :%x", err_idx);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
os_aio_response_error(rcb, err_info);
|
||||
|
||||
DBG_FUNC("OUT");
|
||||
@ -116,18 +116,18 @@ void pqisrc_process_raid_response_error(pqisrc_softstate_t *softs,
|
||||
rcb_t *rcb, uint16_t err_idx)
|
||||
{
|
||||
raid_path_error_info_elem_t *err_info = NULL;
|
||||
|
||||
|
||||
DBG_FUNC("IN");
|
||||
|
||||
|
||||
err_info = (raid_path_error_info_elem_t*)
|
||||
softs->err_buf_dma_mem.virt_addr +
|
||||
err_idx;
|
||||
|
||||
|
||||
if(err_info == NULL) {
|
||||
DBG_ERR("err_info structure is NULL err_idx :%x", err_idx);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
os_raid_response_error(rcb, err_info);
|
||||
|
||||
DBG_FUNC("OUT");
|
||||
@ -179,7 +179,7 @@ pqisrc_process_response_queue(pqisrc_softstate_t *softs, int oq_id)
|
||||
DBG_FUNC("IN");
|
||||
|
||||
OS_ATOMIC64_INC(softs, num_intrs);
|
||||
|
||||
|
||||
ob_q = &softs->op_ob_q[oq_id - 1]; /* zero for event Q */
|
||||
oq_ci = ob_q->ci_local;
|
||||
oq_pi = *(ob_q->pi_virt_addr);
|
||||
|
@ -80,7 +80,7 @@ void sis_disable_intx(pqisrc_softstate_t *softs)
|
||||
void sis_disable_interrupt(pqisrc_softstate_t *softs)
|
||||
{
|
||||
DBG_FUNC("IN");
|
||||
|
||||
|
||||
switch(softs->intr_type) {
|
||||
case INTR_TYPE_FIXED:
|
||||
pqisrc_configure_legacy_intx(softs,false);
|
||||
@ -94,7 +94,7 @@ void sis_disable_interrupt(pqisrc_softstate_t *softs)
|
||||
DBG_ERR("Inerrupt mode none!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
DBG_FUNC("OUT");
|
||||
}
|
||||
|
||||
@ -163,7 +163,6 @@ static int pqisrc_send_sis_cmd(pqisrc_softstate_t *softs,
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
/* Copy Command to mailbox */
|
||||
for (i = 0; i < 6; i++)
|
||||
PCI_MEM_PUT32(softs, &softs->ioa_reg->mb[i],
|
||||
|
@ -29,9 +29,6 @@
|
||||
#ifndef _PQI_STRUCTURES_H
|
||||
#define _PQI_STRUCTURES_H
|
||||
|
||||
|
||||
|
||||
|
||||
struct bmic_host_wellness_driver_version {
|
||||
uint8_t start_tag[4];
|
||||
uint8_t driver_version_tag[2];
|
||||
@ -41,7 +38,6 @@ struct bmic_host_wellness_driver_version {
|
||||
|
||||
}OS_ATTRIBUTE_PACKED;
|
||||
|
||||
|
||||
struct bmic_host_wellness_time {
|
||||
uint8_t start_tag[4];
|
||||
uint8_t time_tag[2];
|
||||
@ -59,7 +55,6 @@ struct bmic_host_wellness_time {
|
||||
|
||||
}OS_ATTRIBUTE_PACKED;
|
||||
|
||||
|
||||
/* As per PQI Spec pqi-2r00a , 6.2.2. */
|
||||
|
||||
/* device capability register , for admin q table 24 */
|
||||
@ -110,7 +105,7 @@ struct pqi_registers {
|
||||
* IOA controller registers
|
||||
* Mapped in PCIe BAR 0.
|
||||
*/
|
||||
|
||||
|
||||
struct ioa_registers {
|
||||
uint8_t res1[0x18];
|
||||
uint32_t host_to_ioa_db_mask_clr; /* 18h */
|
||||
@ -136,7 +131,6 @@ struct ioa_registers {
|
||||
uint32_t mb[8]; /* 1000h */
|
||||
}OS_ATTRIBUTE_PACKED;
|
||||
|
||||
|
||||
/* PQI Preferred settings */
|
||||
struct pqi_pref_settings {
|
||||
uint16_t max_cmd_size;
|
||||
@ -266,7 +260,6 @@ typedef struct iu_header
|
||||
uint16_t iu_length;
|
||||
}OS_ATTRIBUTE_PACKED iu_header_t;
|
||||
|
||||
|
||||
typedef struct general_admin_request /* REPORT_PQI_DEVICE_CAPABILITY, REPORT_MANUFACTURER_INFO, REPORT_OPERATIONAL_IQ, REPORT_OPERATIONAL_OQ all same layout. */
|
||||
{
|
||||
iu_header_t header; /* !< Bytes 0-3. */
|
||||
@ -330,7 +323,6 @@ typedef struct general_admin_request /* REPORT_PQI_DEVICE_CAPABILITY, REPORT_MAN
|
||||
|
||||
}OS_ATTRIBUTE_PACKED gen_adm_req_iu_t;
|
||||
|
||||
|
||||
typedef struct general_admin_response {
|
||||
iu_header_t header;
|
||||
uint16_t res1;
|
||||
@ -439,7 +431,6 @@ struct pqi_event {
|
||||
uint32_t additional_event_id;
|
||||
};
|
||||
|
||||
|
||||
typedef struct op_q_params
|
||||
{
|
||||
uint8_t fn_code;
|
||||
@ -450,7 +441,6 @@ typedef struct op_q_params
|
||||
|
||||
} OS_ATTRIBUTE_PACKED op_q_params;
|
||||
|
||||
|
||||
/* Driver will use this structure to interpret the error
|
||||
info element returned from a failed requests */
|
||||
typedef struct raid_path_error_info_elem {
|
||||
@ -536,7 +526,6 @@ typedef struct pqisrc_sg_desc{
|
||||
uint32_t flags;
|
||||
}sgt_t;
|
||||
|
||||
|
||||
typedef struct pqi_iu_layer_desc {
|
||||
uint8_t ib_spanning_supported : 1;
|
||||
uint8_t res1 : 7;
|
||||
@ -548,7 +537,6 @@ typedef struct pqi_iu_layer_desc {
|
||||
uint16_t max_ob_iu_len;
|
||||
}OS_ATTRIBUTE_PACKED pqi_iu_layer_desc_t;
|
||||
|
||||
|
||||
/* Response IU data */
|
||||
typedef struct pqi_device_capabilities {
|
||||
uint16_t length;
|
||||
@ -609,7 +597,6 @@ typedef struct pqi_aio_req {
|
||||
sgt_t sg_desc[4];
|
||||
}OS_ATTRIBUTE_PACKED pqi_aio_req_t;
|
||||
|
||||
|
||||
typedef struct pqisrc_raid_request {
|
||||
iu_header_t header;
|
||||
uint16_t response_queue_id; /* specifies the OQ where the response
|
||||
@ -637,7 +624,6 @@ typedef struct pqisrc_raid_request {
|
||||
sgt_t sg_descriptors[4];
|
||||
}OS_ATTRIBUTE_PACKED pqisrc_raid_req_t;
|
||||
|
||||
|
||||
typedef struct pqi_tmf_req {
|
||||
iu_header_t header;
|
||||
uint16_t resp_qid;
|
||||
@ -654,7 +640,6 @@ typedef struct pqi_tmf_req {
|
||||
uint8_t fence : 1;
|
||||
}OS_ATTRIBUTE_PACKED pqi_tmf_req_t;
|
||||
|
||||
|
||||
typedef struct pqi_tmf_resp {
|
||||
iu_header_t header;
|
||||
uint16_t resp_qid;
|
||||
@ -665,7 +650,6 @@ typedef struct pqi_tmf_resp {
|
||||
uint8_t resp_code;
|
||||
}pqi_tmf_resp_t;
|
||||
|
||||
|
||||
struct pqi_io_response {
|
||||
iu_header_t header;
|
||||
uint16_t queue_id;
|
||||
@ -675,14 +659,12 @@ struct pqi_io_response {
|
||||
uint8_t reserved[4];
|
||||
}OS_ATTRIBUTE_PACKED;
|
||||
|
||||
|
||||
struct pqi_enc_info {
|
||||
uint16_t data_enc_key_index;
|
||||
uint32_t encrypt_tweak_lower;
|
||||
uint32_t encrypt_tweak_upper;
|
||||
};
|
||||
|
||||
|
||||
typedef struct pqi_scsi_device {
|
||||
device_type_t devtype; /* as reported by INQUIRY commmand */
|
||||
uint8_t device_type; /* as reported by
|
||||
@ -728,7 +710,6 @@ typedef struct pqi_scsi_device {
|
||||
boolean_t invalid;
|
||||
}pqi_scsi_dev_t;
|
||||
|
||||
|
||||
struct sense_header_scsi { /* See SPC-3 section 4.5 */
|
||||
uint8_t response_code; /* permit: 0x0, 0x70, 0x71, 0x72, 0x73 */
|
||||
uint8_t sense_key;
|
||||
@ -740,15 +721,12 @@ struct sense_header_scsi { /* See SPC-3 section 4.5 */
|
||||
uint8_t additional_length; /* always 0 for fixed sense format */
|
||||
}OS_ATTRIBUTE_PACKED;
|
||||
|
||||
|
||||
|
||||
typedef struct report_lun_header {
|
||||
uint32_t list_length;
|
||||
uint8_t extended_response;
|
||||
uint8_t reserved[3];
|
||||
}OS_ATTRIBUTE_PACKED reportlun_header_t;
|
||||
|
||||
|
||||
typedef struct report_lun_ext_entry {
|
||||
uint8_t lunid[8];
|
||||
uint64_t wwid;
|
||||
@ -759,7 +737,6 @@ typedef struct report_lun_ext_entry {
|
||||
uint32_t ioaccel_handle;
|
||||
}OS_ATTRIBUTE_PACKED reportlun_ext_entry_t;
|
||||
|
||||
|
||||
typedef struct report_lun_data_ext {
|
||||
reportlun_header_t header;
|
||||
reportlun_ext_entry_t lun_entries[1];
|
||||
@ -796,7 +773,6 @@ typedef struct raid_map {
|
||||
raidmap_data_t dev_data[RAID_MAP_MAX_ENTRIES];
|
||||
}OS_ATTRIBUTE_PACKED pqisrc_raid_map_t;
|
||||
|
||||
|
||||
typedef struct bmic_ident_ctrl {
|
||||
uint8_t conf_ld_count;
|
||||
uint32_t conf_sign;
|
||||
|
@ -85,7 +85,7 @@ int pqisrc_init_taglist(pqisrc_softstate_t *softs, pqi_taglist_t *taglist,
|
||||
{
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
int i = 0;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
taglist->max_elem = max_elem;
|
||||
@ -99,7 +99,7 @@ int pqisrc_init_taglist(pqisrc_softstate_t *softs, pqi_taglist_t *taglist,
|
||||
ret = PQI_STATUS_FAILURE;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
|
||||
os_strlcpy(taglist->lockname, "tag_lock", LOCKNAME_SIZE);
|
||||
ret = os_init_spinlock(softs, &taglist->lock, taglist->lockname);
|
||||
if(ret){
|
||||
@ -114,7 +114,7 @@ int pqisrc_init_taglist(pqisrc_softstate_t *softs, pqi_taglist_t *taglist,
|
||||
softs->rcb[i].tag = INVALID_ELEM;
|
||||
pqisrc_put_tag(taglist, i);
|
||||
}
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
|
||||
@ -155,14 +155,14 @@ int pqisrc_init_taglist(pqisrc_softstate_t *softs, lockless_stack_t *stack,
|
||||
{
|
||||
int ret = PQI_STATUS_SUCCESS;
|
||||
int index = 0;
|
||||
|
||||
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
/* indices 1 to max_elem are considered as valid tags */
|
||||
stack->num_elements = max_elem + 1;
|
||||
stack->head.data = 0;
|
||||
DBG_INFO("Stack head address :%p\n",&stack->head);
|
||||
|
||||
|
||||
/*Allocate memory for stack*/
|
||||
stack->next_index_array = (uint32_t*)os_mem_alloc(softs,
|
||||
(stack->num_elements * sizeof(uint32_t)));
|
||||
@ -177,7 +177,7 @@ int pqisrc_init_taglist(pqisrc_softstate_t *softs, lockless_stack_t *stack,
|
||||
softs->rcb[index].tag = INVALID_ELEM;
|
||||
pqisrc_put_tag(stack, index);
|
||||
}
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return ret;
|
||||
err_out:
|
||||
@ -191,14 +191,14 @@ int pqisrc_init_taglist(pqisrc_softstate_t *softs, lockless_stack_t *stack,
|
||||
void pqisrc_destroy_taglist(pqisrc_softstate_t *softs, lockless_stack_t *stack)
|
||||
{
|
||||
DBG_FUNC("IN\n");
|
||||
|
||||
|
||||
/* de-allocate stack memory */
|
||||
if (stack->next_index_array) {
|
||||
os_mem_free(softs,(char*)stack->next_index_array,
|
||||
(stack->num_elements * sizeof(uint32_t)));
|
||||
stack->next_index_array = NULL;
|
||||
}
|
||||
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
}
|
||||
|
||||
@ -217,7 +217,7 @@ void pqisrc_put_tag(lockless_stack_t *stack, uint32_t index)
|
||||
DBG_ERR("Pushed Invalid index\n"); /* stack full */
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if ( stack->next_index_array[index] != 0) {
|
||||
ASSERT(false);
|
||||
DBG_ERR("Index already present as tag in the stack\n");
|
||||
|
Loading…
Reference in New Issue
Block a user