bhyve: base pci_nvme_ioreq size on advertised MDTS
NVMe controllers advertise their Max Data Transfer Size (MDTS) to limit the number of page descriptors in an I/O request. Take advantage of this and size the struct pci_nvme_ioreq accordingly. Ensuring these values match both future-proofs the code and allows removing some complexity which only exists to handle this possibility. Tested by: Jason Tubnor MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D24891
This commit is contained in:
Chuck Tuffli
parent
206edceb73
commit
73cd73c0b8
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=362757
@ -99,9 +99,16 @@ static int nvme_debug = 0;
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#define NVME_QUEUES 16
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#define NVME_MAX_QENTRIES 2048
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/* Memory Page size Minimum reported in CAP register */
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#define NVME_MPSMIN 0
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/* MPSMIN converted to bytes */
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#define NVME_MPSMIN_BYTES (1 << (12 + NVME_MPSMIN))
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#define NVME_PRP2_ITEMS (PAGE_SIZE/sizeof(uint64_t))
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#define NVME_MAX_BLOCKIOVS 512
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#define NVME_MDTS 9
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/* Note the + 1 allows for the initial descriptor to not be page aligned */
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#define NVME_MAX_IOVEC ((1 << NVME_MDTS) + 1)
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#define NVME_MAX_DATA_SIZE ((1 << NVME_MDTS) * NVME_MPSMIN_BYTES)
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/* This is a synthetic status code to indicate there is no status */
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#define NVME_NO_STATUS 0xffff
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@ -186,6 +193,18 @@ struct pci_nvme_blockstore {
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uint32_t deallocate:1;
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};
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/*
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* Calculate the number of additional page descriptors for guest IO requests
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* based on the advertised Max Data Transfer (MDTS) and given the number of
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* default iovec's in a struct blockif_req.
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*
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* Note the + 1 allows for the initial descriptor to not be page aligned.
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*/
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#define MDTS_PAD_SIZE \
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NVME_MAX_IOVEC > BLOCKIF_IOV_MAX ? \
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NVME_MAX_IOVEC - BLOCKIF_IOV_MAX : \
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0
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struct pci_nvme_ioreq {
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struct pci_nvme_softc *sc;
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STAILQ_ENTRY(pci_nvme_ioreq) link;
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@ -200,17 +219,9 @@ struct pci_nvme_ioreq {
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uint64_t prev_gpaddr;
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size_t prev_size;
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/*
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* lock if all iovs consumed (big IO);
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* complete transaction before continuing
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*/
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pthread_mutex_t mtx;
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pthread_cond_t cv;
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struct blockif_req io_req;
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/* pad to fit up to 512 page descriptors from guest IO request */
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struct iovec iovpadding[NVME_MAX_BLOCKIOVS-BLOCKIF_IOV_MAX];
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struct iovec iovpadding[MDTS_PAD_SIZE];
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};
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enum nvme_dsm_type {
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@ -279,7 +290,6 @@ struct pci_nvme_softc {
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};
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static void pci_nvme_io_partial(struct blockif_req *br, int err);
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static struct pci_nvme_ioreq *pci_nvme_get_ioreq(struct pci_nvme_softc *);
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static void pci_nvme_release_ioreq(struct pci_nvme_softc *, struct pci_nvme_ioreq *);
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static void pci_nvme_io_done(struct blockif_req *, int);
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@ -433,7 +443,7 @@ pci_nvme_init_ctrldata(struct pci_nvme_softc *sc)
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cd->mic = 0;
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cd->mdts = 9; /* max data transfer size (2^mdts * CAP.MPSMIN) */
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cd->mdts = NVME_MDTS; /* max data transfer size (2^mdts * CAP.MPSMIN) */
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cd->ver = 0x00010300;
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@ -1461,81 +1471,46 @@ pci_nvme_append_iov_req(struct pci_nvme_softc *sc, struct pci_nvme_ioreq *req,
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{
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int iovidx;
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if (req != NULL) {
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/* concatenate contig block-iovs to minimize number of iovs */
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if ((req->prev_gpaddr + req->prev_size) == gpaddr) {
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iovidx = req->io_req.br_iovcnt - 1;
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if (req == NULL)
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return (-1);
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req->io_req.br_iov[iovidx].iov_base =
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paddr_guest2host(req->sc->nsc_pi->pi_vmctx,
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req->prev_gpaddr, size);
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req->prev_size += size;
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req->io_req.br_resid += size;
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req->io_req.br_iov[iovidx].iov_len = req->prev_size;
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} else {
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pthread_mutex_lock(&req->mtx);
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iovidx = req->io_req.br_iovcnt;
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if (iovidx == NVME_MAX_BLOCKIOVS) {
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int err = 0;
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DPRINTF("large I/O, doing partial req");
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iovidx = 0;
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req->io_req.br_iovcnt = 0;
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req->io_req.br_callback = pci_nvme_io_partial;
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if (!do_write)
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err = blockif_read(sc->nvstore.ctx,
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&req->io_req);
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else
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err = blockif_write(sc->nvstore.ctx,
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&req->io_req);
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/* wait until req completes before cont */
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if (err == 0)
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pthread_cond_wait(&req->cv, &req->mtx);
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}
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if (iovidx == 0) {
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req->io_req.br_offset = lba;
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req->io_req.br_resid = 0;
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req->io_req.br_param = req;
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}
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req->io_req.br_iov[iovidx].iov_base =
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paddr_guest2host(req->sc->nsc_pi->pi_vmctx,
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gpaddr, size);
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req->io_req.br_iov[iovidx].iov_len = size;
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req->prev_gpaddr = gpaddr;
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req->prev_size = size;
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req->io_req.br_resid += size;
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req->io_req.br_iovcnt++;
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pthread_mutex_unlock(&req->mtx);
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}
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} else {
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/* RAM buffer: read/write directly */
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void *p = sc->nvstore.ctx;
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void *gptr;
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if ((lba + size) > sc->nvstore.size) {
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WPRINTF("%s write would overflow RAM", __func__);
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return (-1);
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}
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p = (void *)((uintptr_t)p + (uintptr_t)lba);
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gptr = paddr_guest2host(sc->nsc_pi->pi_vmctx, gpaddr, size);
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if (do_write)
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memcpy(p, gptr, size);
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else
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memcpy(gptr, p, size);
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if (req->io_req.br_iovcnt == NVME_MAX_IOVEC) {
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return (-1);
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}
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/* concatenate contig block-iovs to minimize number of iovs */
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if ((req->prev_gpaddr + req->prev_size) == gpaddr) {
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iovidx = req->io_req.br_iovcnt - 1;
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req->io_req.br_iov[iovidx].iov_base =
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paddr_guest2host(req->sc->nsc_pi->pi_vmctx,
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req->prev_gpaddr, size);
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req->prev_size += size;
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req->io_req.br_resid += size;
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req->io_req.br_iov[iovidx].iov_len = req->prev_size;
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} else {
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iovidx = req->io_req.br_iovcnt;
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if (iovidx == 0) {
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req->io_req.br_offset = lba;
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req->io_req.br_resid = 0;
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req->io_req.br_param = req;
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}
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req->io_req.br_iov[iovidx].iov_base =
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paddr_guest2host(req->sc->nsc_pi->pi_vmctx,
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gpaddr, size);
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req->io_req.br_iov[iovidx].iov_len = size;
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req->prev_gpaddr = gpaddr;
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req->prev_size = size;
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req->io_req.br_resid += size;
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req->io_req.br_iovcnt++;
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}
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return (0);
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}
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@ -1633,16 +1608,6 @@ pci_nvme_io_done(struct blockif_req *br, int err)
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pci_nvme_release_ioreq(req->sc, req);
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}
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static void
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pci_nvme_io_partial(struct blockif_req *br, int err)
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{
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struct pci_nvme_ioreq *req = br->br_param;
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DPRINTF("%s error %d %s", __func__, err, strerror(err));
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pthread_cond_signal(&req->cv);
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}
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/*
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* Implements the Flush command. The specification states:
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* If a volatile write cache is not present, Flush commands complete
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@ -1800,9 +1765,14 @@ nvme_opc_write_read(struct pci_nvme_softc *sc,
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lba = ((uint64_t)cmd->cdw11 << 32) | cmd->cdw10;
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nblocks = (cmd->cdw12 & 0xFFFF) + 1;
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offset = lba * nvstore->sectsz;
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bytes = nblocks * nvstore->sectsz;
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if (bytes > NVME_MAX_DATA_SIZE) {
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WPRINTF("%s command would exceed MDTS", __func__);
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pci_nvme_status_genc(status, NVME_SC_INVALID_FIELD);
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goto out;
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}
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offset = lba * nvstore->sectsz;
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if ((offset + bytes) > nvstore->size) {
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WPRINTF("%s command would exceed LBA range", __func__);
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pci_nvme_status_genc(status, NVME_SC_LBA_OUT_OF_RANGE);
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@ -2479,8 +2449,6 @@ pci_nvme_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
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sc->ioreqs = calloc(sc->ioslots, sizeof(struct pci_nvme_ioreq));
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for (int i = 0; i < sc->ioslots; i++) {
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STAILQ_INSERT_TAIL(&sc->ioreqs_free, &sc->ioreqs[i], link);
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pthread_mutex_init(&sc->ioreqs[i].mtx, NULL);
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pthread_cond_init(&sc->ioreqs[i].cv, NULL);
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}
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pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0A0A);
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