Sorted register numbers together with the correspoding register bits.
Merged comments to match (put them at the right of the #defines instead of duplicating them). Sorted the resulting sections on UART type and register bank. Added a comment for each bank.
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=120119
@ -35,28 +35,20 @@
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*/
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/*
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* NS16550 UART registers
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* NS8250... UART registers.
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*/
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#define com_data 0 /* data register (R/W) */
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#define com_dlbl 0 /* divisor latch low (W) */
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#define com_dlbh 1 /* divisor latch high (W) */
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#define com_ier 1 /* interrupt enable (W) */
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#define com_iir 2 /* interrupt identification (R) */
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#define com_fifo 2 /* FIFO control (W) */
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#define com_lctl 3 /* line control register (R/W) */
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#define com_cfcr 3 /* line control register (R/W) */
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#define com_mcr 4 /* modem control register (R/W) */
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#define com_lsr 5 /* line status register (R/W) */
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#define com_msr 6 /* modem status register (R/W) */
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#define com_scr 7 /* scratch register for 16450 up (R/W) */
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/* interrupt enable register */
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/* 8250 registers #[0-6]. */
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#define com_data 0 /* data register (R/W) */
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#define com_ier 1 /* interrupt enable register (W) */
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#define IER_ERXRDY 0x1
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#define IER_ETXRDY 0x2
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#define IER_ERLS 0x4
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#define IER_EMSC 0x8
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/* interrupt identification register */
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#define com_iir 2 /* interrupt identification register (R) */
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#define IIR_IMASK 0xf
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#define IIR_RXTOUT 0xc
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#define IIR_RLS 0x6
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@ -66,17 +58,8 @@
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#define IIR_MLSC 0x0
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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/* fifo control register */
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#define FIFO_ENABLE 0x01
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#define FIFO_RCV_RST 0x02
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#define FIFO_XMT_RST 0x04
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#define FIFO_DMA_MODE 0x08
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#define FIFO_RX_LOW 0x00
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#define FIFO_RX_MEDL 0x40
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#define FIFO_RX_MEDH 0x80
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#define FIFO_RX_HIGH 0xc0
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/* character format control register (aka line control register) */
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#define com_lctl 3 /* line control register (R/W) */
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#define com_cfcr 3 /* character format control register (R/W) */
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#define CFCR_DLAB 0x80
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#define CFCR_SBREAK 0x40
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#define CFCR_PZERO 0x30
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@ -89,17 +72,17 @@
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#define CFCR_7BITS 0x02
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#define CFCR_6BITS 0x01
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#define CFCR_5BITS 0x00
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#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
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#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
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/* modem control register */
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#define MCR_PRESCALE 0x80 /* only available on 16650 up */
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#define com_mcr 4 /* modem control register (R/W) */
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#define MCR_PRESCALE 0x80 /* only available on 16650 up */
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#define MCR_LOOPBACK 0x10
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#define MCR_IENABLE 0x08
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#define MCR_DRS 0x04
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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/* line status register */
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#define com_lsr 5 /* line status register (R/W) */
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#define LSR_RCV_FIFO 0x80
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#define LSR_TSRE 0x40
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#define LSR_TXRDY 0x20
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@ -110,7 +93,7 @@
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#define LSR_RXRDY 0x01
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#define LSR_RCV_MASK 0x1f
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/* modem status register */
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#define com_msr 6 /* modem status register (R/W) */
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#define MSR_DCD 0x80
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#define MSR_RI 0x40
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#define MSR_DSR 0x20
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@ -120,9 +103,28 @@
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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/* enhanced feature register (only available on 16650 up) */
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#define com_efr com_fifo
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#define EFR_EFE 0x10 /* enhanced functions enable */
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/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */
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#define com_dlbl 0 /* divisor latch low (W) */
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#define com_dlbh 1 /* divisor latch high (W) */
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/* 16450 register #7. Not multiplexed. */
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#define com_scr 7 /* scratch register (R/W) */
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/* 16550 register #2. Not multiplexed. */
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#define com_fifo 2 /* FIFO control register (W) */
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#define FIFO_ENABLE 0x01
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#define FIFO_RCV_RST 0x02
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#define FIFO_XMT_RST 0x04
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#define FIFO_DMA_MODE 0x08
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#define FIFO_RX_LOW 0x00
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#define FIFO_RX_MEDL 0x40
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#define FIFO_RX_MEDH 0x80
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#define FIFO_RX_HIGH 0xc0
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/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */
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#define com_efr com_fifo /* enhanced feature register (R/W) */
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#define EFR_EFE 0x10 /* enhanced functions enable */
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#ifdef PC98
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/* Hardware extension mode register for RSB-2000/3000. */
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