Convert A10 interrupt controller to INTRNG
Reviewed by: skra Approved by: cognet (mentor) Differential Revision: https://reviews.freebsd.org/D5573
This commit is contained in:
Emmanuel Vadot
parent
4e7e2cad09
commit
75bf4f5a11
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=298625
430
sys/arm/allwinner/a10/a10_intc.c
Normal file
430
sys/arm/allwinner/a10/a10_intc.c
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@ -0,0 +1,430 @@
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/*-
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* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/types.h>
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#include <sys/bus.h>
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#include <sys/cpuset.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/param.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/smp.h>
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#include <sys/systm.h>
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#ifdef INTRNG
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#include <sys/sched.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#ifdef INTRNG
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#include "pic_if.h"
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#endif
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/**
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* Interrupt controller registers
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*
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*/
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#define SW_INT_VECTOR_REG 0x00
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#define SW_INT_BASE_ADR_REG 0x04
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#define SW_INT_PROTECTION_REG 0x08
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#define SW_INT_NMI_CTRL_REG 0x0c
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#define SW_INT_IRQ_PENDING_REG0 0x10
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#define SW_INT_IRQ_PENDING_REG1 0x14
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#define SW_INT_IRQ_PENDING_REG2 0x18
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#define SW_INT_FIQ_PENDING_REG0 0x20
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#define SW_INT_FIQ_PENDING_REG1 0x24
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#define SW_INT_FIQ_PENDING_REG2 0x28
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#define SW_INT_SELECT_REG0 0x30
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#define SW_INT_SELECT_REG1 0x34
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#define SW_INT_SELECT_REG2 0x38
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#define SW_INT_ENABLE_REG0 0x40
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#define SW_INT_ENABLE_REG1 0x44
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#define SW_INT_ENABLE_REG2 0x48
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#define SW_INT_MASK_REG0 0x50
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#define SW_INT_MASK_REG1 0x54
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#define SW_INT_MASK_REG2 0x58
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#define SW_INT_IRQNO_ENMI 0
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#define A10_INTR_MAX_NIRQS 81
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#define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4))
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#define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4))
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#define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4))
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#define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4))
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#define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4))
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#ifdef INTRNG
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struct a10_intr_irqsrc {
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struct intr_irqsrc isrc;
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u_int irq;
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};
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#endif
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struct a10_aintc_softc {
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device_t sc_dev;
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struct resource * aintc_res;
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bus_space_tag_t aintc_bst;
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bus_space_handle_t aintc_bsh;
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struct mtx mtx;
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#ifdef INTRNG
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struct a10_intr_irqsrc isrcs[A10_INTR_MAX_NIRQS];
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#endif
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};
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#define aintc_read_4(sc, reg) \
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bus_space_read_4(sc->aintc_bst, sc->aintc_bsh, reg)
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#define aintc_write_4(sc, reg, val) \
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bus_space_write_4(sc->aintc_bst, sc->aintc_bsh, reg, val)
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static __inline void
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a10_intr_eoi(struct a10_aintc_softc *sc, u_int irq)
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{
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if (irq != SW_INT_IRQNO_ENMI)
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return;
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mtx_lock_spin(&sc->mtx);
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aintc_write_4(sc, SW_INT_IRQ_PENDING_REG(0),
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(1 << SW_INT_IRQNO_ENMI));
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mtx_unlock_spin(&sc->mtx);
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}
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static void
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a10_intr_unmask(struct a10_aintc_softc *sc, u_int irq)
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{
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uint32_t bit, block, value;
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bit = (irq % 32);
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block = (irq / 32);
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mtx_lock_spin(&sc->mtx);
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value = aintc_read_4(sc, SW_INT_ENABLE_REG(block));
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value |= (1 << bit);
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aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);
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value = aintc_read_4(sc, SW_INT_MASK_REG(block));
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value &= ~(1 << bit);
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aintc_write_4(sc, SW_INT_MASK_REG(block), value);
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mtx_unlock_spin(&sc->mtx);
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}
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static void
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a10_intr_mask(struct a10_aintc_softc *sc, u_int irq)
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{
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uint32_t bit, block, value;
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bit = (irq % 32);
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block = (irq / 32);
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mtx_lock_spin(&sc->mtx);
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value = aintc_read_4(sc, SW_INT_ENABLE_REG(block));
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value &= ~(1 << bit);
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aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);
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value = aintc_read_4(sc, SW_INT_MASK_REG(block));
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value |= (1 << bit);
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aintc_write_4(sc, SW_INT_MASK_REG(block), value);
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mtx_unlock_spin(&sc->mtx);
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}
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static int
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a10_pending_irq(struct a10_aintc_softc *sc)
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{
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uint32_t value;
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int i, b;
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for (i = 0; i < 3; i++) {
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value = aintc_read_4(sc, SW_INT_IRQ_PENDING_REG(i));
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if (value == 0)
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continue;
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for (b = 0; b < 32; b++)
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if (value & (1 << b)) {
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return (i * 32 + b);
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}
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}
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return (-1);
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}
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#ifndef INTRNG
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static struct a10_aintc_softc *a10_aintc_sc = NULL;
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int
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arm_get_next_irq(int last_irq)
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{
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return (a10_pending_irq(a10_aintc_sc));
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}
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void
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arm_mask_irq(uintptr_t irq)
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{
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a10_intr_mask(a10_aintc_sc, irq);
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}
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void
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arm_unmask_irq(uintptr_t irq)
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{
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a10_intr_unmask(a10_aintc_sc, irq);
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a10_intr_eoi(a10_aintc_sc, irq);
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}
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#else /* INTRNG */
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static int
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a10_intr(void *arg)
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{
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struct a10_aintc_softc *sc = arg;
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u_int irq;
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irq = a10_pending_irq(sc);
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if (irq == -1 || irq > A10_INTR_MAX_NIRQS) {
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device_printf(sc->sc_dev, "Spurious interrupt %d\n", irq);
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return (FILTER_HANDLED);
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}
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while (irq != -1) {
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if (irq > A10_INTR_MAX_NIRQS) {
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device_printf(sc->sc_dev, "Spurious interrupt %d\n",
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irq);
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return (FILTER_HANDLED);
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}
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if (intr_isrc_dispatch(&sc->isrcs[irq].isrc,
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curthread->td_intr_frame) != 0) {
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a10_intr_mask(sc, irq);
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a10_intr_eoi(sc, irq);
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device_printf(sc->sc_dev,
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"Stray interrupt %d disabled\n", irq);
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}
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arm_irq_memory_barrier(irq);
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irq = a10_pending_irq(sc);
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}
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return (FILTER_HANDLED);
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}
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static int
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a10_intr_pic_attach(struct a10_aintc_softc *sc)
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{
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int error;
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uint32_t irq;
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const char *name;
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intptr_t xref;
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name = device_get_nameunit(sc->sc_dev);
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for (irq = 0; irq < A10_INTR_MAX_NIRQS; irq++) {
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sc->isrcs[irq].irq = irq;
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error = intr_isrc_register(&sc->isrcs[irq].isrc,
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sc->sc_dev, 0, "%s,%u", name, irq);
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if (error != 0)
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return (error);
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}
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xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev));
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error = intr_pic_register(sc->sc_dev, xref);
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if (error != 0)
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return (error);
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return (intr_pic_claim_root(sc->sc_dev, xref, a10_intr, sc, 0));
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}
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static void
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a10_intr_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct a10_aintc_softc *sc;
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u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq;
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sc = device_get_softc(dev);
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arm_irq_memory_barrier(irq);
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a10_intr_unmask(sc, irq);
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}
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static void
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a10_intr_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct a10_aintc_softc *sc;
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u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq;
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sc = device_get_softc(dev);
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a10_intr_mask(sc, irq);
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}
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static int
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a10_intr_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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struct a10_aintc_softc *sc;
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if (data->type != INTR_MAP_DATA_FDT || data->fdt.ncells != 1 ||
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data->fdt.cells[0] >= A10_INTR_MAX_NIRQS)
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return (EINVAL);
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sc = device_get_softc(dev);
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*isrcp = &sc->isrcs[data->fdt.cells[0]].isrc;
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return (0);
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}
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static void
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a10_intr_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct a10_aintc_softc *sc = device_get_softc(dev);
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u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq;
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a10_intr_mask(sc, irq);
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a10_intr_eoi(sc, irq);
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}
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static void
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a10_intr_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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a10_intr_enable_intr(dev, isrc);
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}
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static void
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a10_intr_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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struct a10_aintc_softc *sc = device_get_softc(dev);
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u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq;
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a10_intr_eoi(sc, irq);
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}
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#endif /* INTRNG */
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static int
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a10_aintc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ic"))
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return (ENXIO);
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device_set_desc(dev, "A10 AINTC Interrupt Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a10_aintc_attach(device_t dev)
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{
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struct a10_aintc_softc *sc = device_get_softc(dev);
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int rid = 0;
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int i;
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sc->sc_dev = dev;
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#ifndef INTRNG
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if (a10_aintc_sc)
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goto error;
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a10_aintc_sc = sc;
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#endif
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sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&rid, RF_ACTIVE);
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if (!sc->aintc_res) {
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device_printf(dev, "could not allocate resource\n");
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goto error;
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}
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sc->aintc_bst = rman_get_bustag(sc->aintc_res);
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sc->aintc_bsh = rman_get_bushandle(sc->aintc_res);
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mtx_init(&sc->mtx, "A10 AINTC lock", "", MTX_SPIN);
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/* Disable & clear all interrupts */
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for (i = 0; i < 3; i++) {
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aintc_write_4(sc, SW_INT_ENABLE_REG(i), 0);
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aintc_write_4(sc, SW_INT_MASK_REG(i), 0xffffffff);
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}
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/* enable protection mode*/
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aintc_write_4(sc, SW_INT_PROTECTION_REG, 0x01);
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/* config the external interrupt source type*/
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aintc_write_4(sc, SW_INT_NMI_CTRL_REG, 0x00);
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#ifdef INTRNG
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if (a10_intr_pic_attach(sc) != 0) {
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device_printf(dev, "could not attach PIC\n");
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return (ENXIO);
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}
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#endif
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return (0);
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error:
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bus_release_resource(dev, SYS_RES_MEMORY, rid,
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sc->aintc_res);
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return (ENXIO);
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}
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static device_method_t a10_aintc_methods[] = {
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DEVMETHOD(device_probe, a10_aintc_probe),
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DEVMETHOD(device_attach, a10_aintc_attach),
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#ifdef INTRNG
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/* Interrupt controller interface */
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DEVMETHOD(pic_disable_intr, a10_intr_disable_intr),
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DEVMETHOD(pic_enable_intr, a10_intr_enable_intr),
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DEVMETHOD(pic_map_intr, a10_intr_map_intr),
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DEVMETHOD(pic_post_filter, a10_intr_post_filter),
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DEVMETHOD(pic_post_ithread, a10_intr_post_ithread),
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DEVMETHOD(pic_pre_ithread, a10_intr_pre_ithread),
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#endif
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{ 0, 0 }
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};
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static driver_t a10_aintc_driver = {
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"aintc",
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a10_aintc_methods,
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sizeof(struct a10_aintc_softc),
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};
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static devclass_t a10_aintc_devclass;
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EARLY_DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0,
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BUS_PASS_INTERRUPT + BUS_PASS_ORDER_FIRST);
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@ -1,222 +0,0 @@
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/*-
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* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
|
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* All rights reserved.
|
||||
*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/ktr.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/rman.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/intr.h>
|
||||
|
||||
#include <dev/fdt/fdt_common.h>
|
||||
#include <dev/ofw/openfirm.h>
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
#include <dev/ofw/ofw_bus_subr.h>
|
||||
|
||||
/**
|
||||
* Interrupt controller registers
|
||||
*
|
||||
*/
|
||||
#define SW_INT_VECTOR_REG 0x00
|
||||
#define SW_INT_BASE_ADR_REG 0x04
|
||||
#define SW_INT_PROTECTION_REG 0x08
|
||||
#define SW_INT_NMI_CTRL_REG 0x0c
|
||||
|
||||
#define SW_INT_IRQ_PENDING_REG0 0x10
|
||||
#define SW_INT_IRQ_PENDING_REG1 0x14
|
||||
#define SW_INT_IRQ_PENDING_REG2 0x18
|
||||
|
||||
#define SW_INT_FIQ_PENDING_REG0 0x20
|
||||
#define SW_INT_FIQ_PENDING_REG1 0x24
|
||||
#define SW_INT_FIQ_PENDING_REG2 0x28
|
||||
|
||||
#define SW_INT_SELECT_REG0 0x30
|
||||
#define SW_INT_SELECT_REG1 0x34
|
||||
#define SW_INT_SELECT_REG2 0x38
|
||||
|
||||
#define SW_INT_ENABLE_REG0 0x40
|
||||
#define SW_INT_ENABLE_REG1 0x44
|
||||
#define SW_INT_ENABLE_REG2 0x48
|
||||
|
||||
#define SW_INT_MASK_REG0 0x50
|
||||
#define SW_INT_MASK_REG1 0x54
|
||||
#define SW_INT_MASK_REG2 0x58
|
||||
|
||||
#define SW_INT_IRQNO_ENMI 0
|
||||
|
||||
#define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4))
|
||||
#define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4))
|
||||
#define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4))
|
||||
#define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4))
|
||||
#define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4))
|
||||
|
||||
static struct ofw_compat_data compat_data[] = {
|
||||
{"allwinner,sun4i-a10-ic", 1},
|
||||
{"allwinner,sun7i-a20-sc-nmi", 1},
|
||||
{NULL, 0}
|
||||
};
|
||||
|
||||
struct a10_aintc_softc {
|
||||
device_t sc_dev;
|
||||
struct resource * aintc_res;
|
||||
bus_space_tag_t aintc_bst;
|
||||
bus_space_handle_t aintc_bsh;
|
||||
uint8_t ver;
|
||||
};
|
||||
|
||||
static struct a10_aintc_softc *a10_aintc_sc = NULL;
|
||||
|
||||
#define aintc_read_4(reg) \
|
||||
bus_space_read_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg)
|
||||
#define aintc_write_4(reg, val) \
|
||||
bus_space_write_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg, val)
|
||||
|
||||
static int
|
||||
a10_aintc_probe(device_t dev)
|
||||
{
|
||||
|
||||
if (!ofw_bus_status_okay(dev))
|
||||
return (ENXIO);
|
||||
|
||||
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
|
||||
return (ENXIO);
|
||||
device_set_desc(dev, "A10 AINTC Interrupt Controller");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
|
||||
static int
|
||||
a10_aintc_attach(device_t dev)
|
||||
{
|
||||
struct a10_aintc_softc *sc = device_get_softc(dev);
|
||||
int rid = 0;
|
||||
int i;
|
||||
|
||||
sc->sc_dev = dev;
|
||||
|
||||
if (a10_aintc_sc)
|
||||
return (ENXIO);
|
||||
|
||||
sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
|
||||
if (!sc->aintc_res) {
|
||||
device_printf(dev, "could not allocate resource\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
sc->aintc_bst = rman_get_bustag(sc->aintc_res);
|
||||
sc->aintc_bsh = rman_get_bushandle(sc->aintc_res);
|
||||
|
||||
a10_aintc_sc = sc;
|
||||
|
||||
/* Disable & clear all interrupts */
|
||||
for (i = 0; i < 3; i++) {
|
||||
aintc_write_4(SW_INT_ENABLE_REG(i), 0);
|
||||
aintc_write_4(SW_INT_MASK_REG(i), 0xffffffff);
|
||||
}
|
||||
/* enable protection mode*/
|
||||
aintc_write_4(SW_INT_PROTECTION_REG, 0x01);
|
||||
|
||||
/* config the external interrupt source type*/
|
||||
aintc_write_4(SW_INT_NMI_CTRL_REG, 0x00);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t a10_aintc_methods[] = {
|
||||
DEVMETHOD(device_probe, a10_aintc_probe),
|
||||
DEVMETHOD(device_attach, a10_aintc_attach),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t a10_aintc_driver = {
|
||||
"aintc",
|
||||
a10_aintc_methods,
|
||||
sizeof(struct a10_aintc_softc),
|
||||
};
|
||||
|
||||
static devclass_t a10_aintc_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0,
|
||||
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_FIRST);
|
||||
|
||||
int
|
||||
arm_get_next_irq(int last_irq)
|
||||
{
|
||||
uint32_t value;
|
||||
int i, b;
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
value = aintc_read_4(SW_INT_IRQ_PENDING_REG(i));
|
||||
for (b = 0; b < 32; b++)
|
||||
if (value & (1 << b)) {
|
||||
return (i * 32 + b);
|
||||
}
|
||||
}
|
||||
|
||||
return (-1);
|
||||
}
|
||||
|
||||
void
|
||||
arm_mask_irq(uintptr_t nb)
|
||||
{
|
||||
uint32_t bit, block, value;
|
||||
|
||||
bit = (nb % 32);
|
||||
block = (nb / 32);
|
||||
|
||||
value = aintc_read_4(SW_INT_ENABLE_REG(block));
|
||||
value &= ~(1 << bit);
|
||||
aintc_write_4(SW_INT_ENABLE_REG(block), value);
|
||||
|
||||
value = aintc_read_4(SW_INT_MASK_REG(block));
|
||||
value |= (1 << bit);
|
||||
aintc_write_4(SW_INT_MASK_REG(block), value);
|
||||
}
|
||||
|
||||
void
|
||||
arm_unmask_irq(uintptr_t nb)
|
||||
{
|
||||
uint32_t bit, block, value;
|
||||
|
||||
bit = (nb % 32);
|
||||
block = (nb / 32);
|
||||
|
||||
value = aintc_read_4(SW_INT_ENABLE_REG(block));
|
||||
value |= (1 << bit);
|
||||
aintc_write_4(SW_INT_ENABLE_REG(block), value);
|
||||
|
||||
value = aintc_read_4(SW_INT_MASK_REG(block));
|
||||
value &= ~(1 << bit);
|
||||
aintc_write_4(SW_INT_MASK_REG(block), value);
|
||||
|
||||
if(nb == SW_INT_IRQNO_ENMI) /* must clear pending bit when enabled */
|
||||
aintc_write_4(SW_INT_IRQ_PENDING_REG(0), (1 << SW_INT_IRQNO_ENMI));
|
||||
}
|
||||
@ -1,5 +1,5 @@
|
||||
# $FreeBSD$
|
||||
|
||||
arm/allwinner/a10/a10_intc.c standard
|
||||
arm/allwinner/a10_padconf.c standard
|
||||
arm/allwinner/aintc.c standard
|
||||
arm/allwinner/timer.c standard
|
||||
|
||||
@ -23,6 +23,8 @@ ident A10
|
||||
include "std.armv6"
|
||||
include "../allwinner/std.a10"
|
||||
|
||||
options INTRNG
|
||||
|
||||
options SOC_ALLWINNER_A10
|
||||
|
||||
options HZ=100
|
||||
|
||||
Loading…
Reference in New Issue
Block a user