drm/i915: Reduce diff with Linux 3.8
There is no functional change. The goal is to ease the future update to Linux 3.8's i915 driver. MFC after: 2 months
This commit is contained in:
parent
99ebb75d84
commit
75fcfd2d4b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=291431
@ -133,10 +133,10 @@ typedef struct _drm_i915_sarea {
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* over the lifetime of the client, though it doesn't in our current
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* implementation.
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*/
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unsigned int front_bo_handle;
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unsigned int back_bo_handle;
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unsigned int third_bo_handle;
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unsigned int depth_bo_handle;
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__u32 front_bo_handle;
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__u32 back_bo_handle;
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__u32 third_bo_handle;
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__u32 depth_bo_handle;
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} drm_i915_sarea_t;
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/* due to userspace building against these headers we need some compat here */
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@ -421,7 +421,7 @@ typedef struct drm_i915_mmio {
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} drm_i915_mmio_t;
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typedef struct drm_i915_hws_addr {
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uint64_t addr;
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__u64 addr;
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} drm_i915_hws_addr_t;
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/*
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@ -461,12 +461,12 @@ struct drm_i915_gem_init {
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* Beginning offset in the GTT to be managed by the DRM memory
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* manager.
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*/
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uint64_t gtt_start;
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__u64 gtt_start;
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/**
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* Ending offset in the GTT to be managed by the DRM memory
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* manager.
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*/
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uint64_t gtt_end;
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__u64 gtt_end;
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};
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struct drm_i915_gem_create {
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@ -475,82 +475,82 @@ struct drm_i915_gem_create {
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*
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* The (page-aligned) allocated size for the object will be returned.
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*/
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uint64_t size;
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__u64 size;
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/**
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* Returned handle for the object.
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*
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* Object handles are nonzero.
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*/
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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};
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struct drm_i915_gem_pread {
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/** Handle for the object being read. */
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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/** Offset into the object to read from */
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uint64_t offset;
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__u64 offset;
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/** Length of data to read */
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uint64_t size;
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__u64 size;
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/** Pointer to write the data into. */
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uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
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__u64 data_ptr; /* void *, but pointers are not 32/64 compatible */
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};
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struct drm_i915_gem_pwrite {
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/** Handle for the object being written to. */
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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/** Offset into the object to write to */
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uint64_t offset;
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__u64 offset;
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/** Length of data to write */
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uint64_t size;
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__u64 size;
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/** Pointer to read the data from. */
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uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
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__u64 data_ptr; /* void *, but pointers are not 32/64 compatible */
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};
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struct drm_i915_gem_mmap {
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/** Handle for the object being mapped. */
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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/** Offset in the object to map. */
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uint64_t offset;
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__u64 offset;
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/**
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* Length of data to map.
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*
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* The value will be page-aligned.
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*/
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uint64_t size;
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__u64 size;
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/** Returned pointer the data was mapped at */
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uint64_t addr_ptr; /* void *, but pointers are not 32/64 compatible */
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__u64 addr_ptr; /* void *, but pointers are not 32/64 compatible */
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};
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struct drm_i915_gem_mmap_gtt {
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/** Handle for the object being mapped. */
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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/**
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* Fake offset to use for subsequent mmap call
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*
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* This is a fixed-size type for 32/64 compatibility.
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*/
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uint64_t offset;
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__u64 offset;
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};
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struct drm_i915_gem_set_domain {
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/** Handle for the object */
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uint32_t handle;
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__u32 handle;
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/** New read domains */
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uint32_t read_domains;
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__u32 read_domains;
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/** New write domain */
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uint32_t write_domain;
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__u32 write_domain;
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};
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struct drm_i915_gem_sw_finish {
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/** Handle for the object */
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uint32_t handle;
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__u32 handle;
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};
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struct drm_i915_gem_relocation_entry {
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@ -562,16 +562,16 @@ struct drm_i915_gem_relocation_entry {
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* a relocation list for state buffers and not re-write it per
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* exec using the buffer.
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*/
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uint32_t target_handle;
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__u32 target_handle;
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/**
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* Value to be added to the offset of the target buffer to make up
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* the relocation entry.
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*/
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uint32_t delta;
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__u32 delta;
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/** Offset in the buffer the relocation entry will be written into */
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uint64_t offset;
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__u64 offset;
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/**
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* Offset value of the target buffer that the relocation entry was last
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@ -581,12 +581,12 @@ struct drm_i915_gem_relocation_entry {
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* and writing the relocation. This value is written back out by
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* the execbuffer ioctl when the relocation is written.
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*/
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uint64_t presumed_offset;
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__u64 presumed_offset;
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/**
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* Target memory domains read by this operation.
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*/
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uint32_t read_domains;
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__u32 read_domains;
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/**
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* Target memory domains written by this operation.
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@ -595,7 +595,7 @@ struct drm_i915_gem_relocation_entry {
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* execbuffer operation, so that where there are conflicts,
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* the application will get -EINVAL back.
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*/
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uint32_t write_domain;
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__u32 write_domain;
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};
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/** @{
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@ -626,24 +626,24 @@ struct drm_i915_gem_exec_object {
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* User's handle for a buffer to be bound into the GTT for this
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* operation.
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*/
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uint32_t handle;
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__u32 handle;
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/** Number of relocations to be performed on this buffer */
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uint32_t relocation_count;
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__u32 relocation_count;
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/**
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* Pointer to array of struct drm_i915_gem_relocation_entry containing
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* the relocations to be performed in this buffer.
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*/
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uint64_t relocs_ptr;
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__u64 relocs_ptr;
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/** Required alignment in graphics aperture */
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uint64_t alignment;
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__u64 alignment;
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/**
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* Returned value of the updated offset of the object, for future
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* presumed_offset writes.
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*/
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uint64_t offset;
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__u64 offset;
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};
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struct drm_i915_gem_execbuffer {
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@ -657,17 +657,17 @@ struct drm_i915_gem_execbuffer {
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* a buffer is performing refer to buffers that have already appeared
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* in the validate list.
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*/
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uint64_t buffers_ptr;
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uint32_t buffer_count;
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__u64 buffers_ptr;
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__u32 buffer_count;
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/** Offset in the batchbuffer to start execution from. */
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uint32_t batch_start_offset;
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__u32 batch_start_offset;
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/** Bytes used in batchbuffer from batch_start_offset */
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uint32_t batch_len;
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uint32_t DR1;
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uint32_t DR4;
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uint32_t num_cliprects;
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uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */
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__u32 batch_len;
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__u32 DR1;
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__u32 DR4;
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__u32 num_cliprects;
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__u64 cliprects_ptr; /* struct drm_clip_rect *cliprects */
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};
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struct drm_i915_gem_exec_object2 {
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@ -675,47 +675,47 @@ struct drm_i915_gem_exec_object2 {
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* User's handle for a buffer to be bound into the GTT for this
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* operation.
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*/
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uint32_t handle;
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__u32 handle;
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/** Number of relocations to be performed on this buffer */
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uint32_t relocation_count;
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__u32 relocation_count;
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/**
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* Pointer to array of struct drm_i915_gem_relocation_entry containing
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* the relocations to be performed in this buffer.
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*/
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uint64_t relocs_ptr;
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__u64 relocs_ptr;
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/** Required alignment in graphics aperture */
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uint64_t alignment;
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__u64 alignment;
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/**
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* Returned value of the updated offset of the object, for future
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* presumed_offset writes.
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*/
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uint64_t offset;
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__u64 offset;
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#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
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uint64_t flags;
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uint64_t rsvd1; /* now used for context info */
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uint64_t rsvd2;
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__u64 flags;
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__u64 rsvd1; /* now used for context info */
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__u64 rsvd2;
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};
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struct drm_i915_gem_execbuffer2 {
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/**
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* List of gem_exec_object2 structs
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*/
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uint64_t buffers_ptr;
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uint32_t buffer_count;
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__u64 buffers_ptr;
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__u32 buffer_count;
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/** Offset in the batchbuffer to start execution from. */
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uint32_t batch_start_offset;
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__u32 batch_start_offset;
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/** Bytes used in batchbuffer from batch_start_offset */
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uint32_t batch_len;
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uint32_t DR1;
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uint32_t DR4;
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uint32_t num_cliprects;
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__u32 batch_len;
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__u32 DR1;
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__u32 DR4;
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__u32 num_cliprects;
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/** This is a struct drm_clip_rect *cliprects */
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uint64_t cliprects_ptr;
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__u64 cliprects_ptr;
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#define I915_EXEC_RING_MASK (7<<0)
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#define I915_EXEC_DEFAULT (0<<0)
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#define I915_EXEC_RENDER (1<<0)
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@ -732,9 +732,9 @@ struct drm_i915_gem_execbuffer2 {
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#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
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#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
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#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
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uint64_t flags;
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uint64_t rsvd1;
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uint64_t rsvd2;
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__u64 flags;
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__u64 rsvd1;
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__u64 rsvd2;
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};
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/** Resets the SO write offset registers for transform feedback on gen7. */
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@ -748,28 +748,28 @@ struct drm_i915_gem_execbuffer2 {
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struct drm_i915_gem_pin {
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/** Handle of the buffer to be pinned. */
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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/** alignment required within the aperture */
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uint64_t alignment;
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__u64 alignment;
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/** Returned GTT offset of the buffer. */
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uint64_t offset;
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__u64 offset;
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};
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struct drm_i915_gem_unpin {
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/** Handle of the buffer to be unpinned. */
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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};
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struct drm_i915_gem_busy {
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/** Handle of the buffer to check for busy */
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uint32_t handle;
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__u32 handle;
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/** Return busy status (1 if busy, 0 if idle) */
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uint32_t busy;
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__u32 busy;
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};
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#define I915_TILING_NONE 0
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@ -789,7 +789,7 @@ struct drm_i915_gem_busy {
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struct drm_i915_gem_set_tiling {
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/** Handle of the buffer to have its tiling state updated */
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uint32_t handle;
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__u32 handle;
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/**
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* Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
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@ -803,55 +803,55 @@ struct drm_i915_gem_set_tiling {
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*
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* Buffer contents become undefined when changing tiling_mode.
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*/
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uint32_t tiling_mode;
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__u32 tiling_mode;
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/**
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* Stride in bytes for the object when in I915_TILING_X or
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* I915_TILING_Y.
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*/
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uint32_t stride;
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__u32 stride;
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/**
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* Returned address bit 6 swizzling required for CPU access through
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* mmap mapping.
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*/
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uint32_t swizzle_mode;
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__u32 swizzle_mode;
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};
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struct drm_i915_gem_get_tiling {
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/** Handle of the buffer to get tiling state for. */
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uint32_t handle;
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__u32 handle;
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/**
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* Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
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* I915_TILING_Y).
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*/
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uint32_t tiling_mode;
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__u32 tiling_mode;
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/**
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* Returned address bit 6 swizzling required for CPU access through
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* mmap mapping.
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*/
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uint32_t swizzle_mode;
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__u32 swizzle_mode;
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};
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struct drm_i915_gem_get_aperture {
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/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
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uint64_t aper_size;
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__u64 aper_size;
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/**
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* Available space in the aperture used by i915_gem_execbuffer, in
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* bytes
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*/
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uint64_t aper_available_size;
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__u64 aper_available_size;
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};
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struct drm_i915_get_pipe_from_crtc_id {
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/** ID of CRTC being requested **/
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uint32_t crtc_id;
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/** ID of CRTC being requested **/
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__u32 crtc_id;
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/** pipe of requested CRTC **/
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uint32_t pipe;
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/** pipe of requested CRTC **/
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__u32 pipe;
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};
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#define I915_MADV_WILLNEED 0
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@ -860,15 +860,15 @@ struct drm_i915_get_pipe_from_crtc_id {
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struct drm_i915_gem_madvise {
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/** Handle of the buffer to change the backing store advice */
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uint32_t handle;
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__u32 handle;
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/* Advice: either the buffer will be needed again in the near future,
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* or wont be and could be discarded under memory pressure.
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*/
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uint32_t madv;
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__u32 madv;
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/** Whether the backing store still exists. */
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uint32_t retained;
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__u32 retained;
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};
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#define I915_OVERLAY_TYPE_MASK 0xff
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@ -896,44 +896,44 @@ struct drm_i915_gem_madvise {
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struct drm_intel_overlay_put_image {
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/* various flags and src format description */
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uint32_t flags;
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__u32 flags;
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/* source picture description */
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uint32_t bo_handle;
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__u32 bo_handle;
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/* stride values and offsets are in bytes, buffer relative */
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uint16_t stride_Y; /* stride for packed formats */
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uint16_t stride_UV;
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uint32_t offset_Y; /* offset for packet formats */
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uint32_t offset_U;
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uint32_t offset_V;
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__u16 stride_Y; /* stride for packed formats */
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__u16 stride_UV;
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__u32 offset_Y; /* offset for packet formats */
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__u32 offset_U;
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__u32 offset_V;
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/* in pixels */
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uint16_t src_width;
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uint16_t src_height;
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__u16 src_width;
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__u16 src_height;
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/* to compensate the scaling factors for partially covered surfaces */
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uint16_t src_scan_width;
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uint16_t src_scan_height;
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__u16 src_scan_width;
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__u16 src_scan_height;
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/* output crtc description */
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uint32_t crtc_id;
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uint16_t dst_x;
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uint16_t dst_y;
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uint16_t dst_width;
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uint16_t dst_height;
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__u32 crtc_id;
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__u16 dst_x;
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__u16 dst_y;
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__u16 dst_width;
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__u16 dst_height;
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};
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/* flags */
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#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
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#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
|
||||
struct drm_intel_overlay_attrs {
|
||||
uint32_t flags;
|
||||
uint32_t color_key;
|
||||
int32_t brightness;
|
||||
uint32_t contrast;
|
||||
uint32_t saturation;
|
||||
uint32_t gamma0;
|
||||
uint32_t gamma1;
|
||||
uint32_t gamma2;
|
||||
uint32_t gamma3;
|
||||
uint32_t gamma4;
|
||||
uint32_t gamma5;
|
||||
__u32 flags;
|
||||
__u32 color_key;
|
||||
__s32 brightness;
|
||||
__u32 contrast;
|
||||
__u32 saturation;
|
||||
__u32 gamma0;
|
||||
__u32 gamma1;
|
||||
__u32 gamma2;
|
||||
__u32 gamma3;
|
||||
__u32 gamma4;
|
||||
__u32 gamma5;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -961,22 +961,22 @@ struct drm_intel_overlay_attrs {
|
||||
#define I915_SET_COLORKEY_DESTINATION (1<<1)
|
||||
#define I915_SET_COLORKEY_SOURCE (1<<2)
|
||||
struct drm_intel_sprite_colorkey {
|
||||
uint32_t plane_id;
|
||||
uint32_t min_value;
|
||||
uint32_t channel_mask;
|
||||
uint32_t max_value;
|
||||
uint32_t flags;
|
||||
__u32 plane_id;
|
||||
__u32 min_value;
|
||||
__u32 channel_mask;
|
||||
__u32 max_value;
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_create {
|
||||
/* output: id of new context*/
|
||||
uint32_t ctx_id;
|
||||
uint32_t pad;
|
||||
__u32 ctx_id;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_destroy {
|
||||
uint32_t ctx_id;
|
||||
uint32_t pad;
|
||||
__u32 ctx_id;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
#endif /* _I915_DRM_H_ */
|
||||
|
Loading…
Reference in New Issue
Block a user