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Remove duplicate code. Reduce diff between amd64 and i386.

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This commit is contained in:
Jung-uk Kim 2012-12-01 00:56:19 +00:00
parent 5a5d90a268
commit 7609e73ca0
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=243737
2 changed files with 26 additions and 31 deletions
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13
sys/amd64/pci/pci_cfgreg.c
View File

@ -295,6 +295,13 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
return (1);
}
#define PCIE_VADDR(base, reg, bus, slot, func) \
((base) + \
((((bus) & 0xff) << 20) | \
(((slot) & 0x1f) << 15) | \
(((func) & 0x7) << 12) | \
((reg) & 0xfff)))
/*
* AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h
* have a requirement that all accesses to the memory mapped PCI configuration
@ -302,12 +309,6 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
* Since other vendors do not currently have any contradicting requirements
* the AMD access pattern is applied universally.
*/
#define PCIE_VADDR(base, reg, bus, slot, func) \
((base) + \
((((bus) & 0xff) << 20) | \
(((slot) & 0x1f) << 15) | \
(((func) & 0x7) << 12) | \
((reg) & 0xfff)))
static int
pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,

44
sys/i386/pci/pci_cfgreg.c
View File

@ -610,25 +610,29 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
}
#endif /* !XEN */
#define PCIE_PADDR(bar, reg, bus, slot, func) \
((bar) | \
(((bus) & 0xff) << 20) | \
#define PCIE_PADDR(base, reg, bus, slot, func) \
((base) + \
((((bus) & 0xff) << 20) | \
(((slot) & 0x1f) << 15) | \
(((func) & 0x7) << 12) | \
((reg) & 0xfff))
((reg) & 0xfff)))
/*
* Find an element in the cache that matches the physical page desired, or
* create a new mapping from the least recently used element.
* A very simple LRU algorithm is used here, does it need to be more
* efficient?
*/
static __inline struct pcie_cfg_elem *
pciereg_findelem(vm_paddr_t papage)
static __inline vm_offset_t
pciereg_findaddr(int bus, unsigned slot, unsigned func, unsigned reg)
{
struct pcie_cfg_list *pcielist;
struct pcie_cfg_elem *elem;
vm_paddr_t pa, papage;
pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
papage = pa & ~PAGE_MASK;
/*
* Find an element in the cache that matches the physical page desired,
* or create a new mapping from the least recently used element.
* A very simple LRU algorithm is used here, does it need to be more
* efficient?
*/
pcielist = &pcie_list[PCPU_GET(cpuid)];
TAILQ_FOREACH(elem, pcielist, elem) {
if (elem->papage == papage)
@ -649,7 +653,7 @@ pciereg_findelem(vm_paddr_t papage)
TAILQ_REMOVE(pcielist, elem, elem);
TAILQ_INSERT_HEAD(pcielist, elem, elem);
}
return (elem);
return (elem->vapage | (pa & PAGE_MASK));
}
/*
@ -664,9 +668,7 @@ static int
pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
unsigned bytes)
{
struct pcie_cfg_elem *elem;
vm_offset_t va;
vm_paddr_t pa, papage;
int data = -1;
if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
@ -674,10 +676,7 @@ pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
return (-1);
critical_enter();
pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
papage = pa & ~PAGE_MASK;
elem = pciereg_findelem(papage);
va = elem->vapage | (pa & PAGE_MASK);
va = pciereg_findaddr(bus, slot, func, reg);
switch (bytes) {
case 4:
@ -702,19 +701,14 @@ static void
pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
unsigned bytes)
{
struct pcie_cfg_elem *elem;
vm_offset_t va;
vm_paddr_t pa, papage;
if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
func > PCI_FUNCMAX || reg > PCIE_REGMAX)
return;
critical_enter();
pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
papage = pa & ~PAGE_MASK;
elem = pciereg_findelem(papage);
va = elem->vapage | (pa & PAGE_MASK);
va = pciereg_findaddr(bus, slot, func, reg);
switch (bytes) {
case 4: