Compatibility with IBM firmware.
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caf29fab8c
commit
761d31e8bf
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=230999
@ -178,7 +178,8 @@ cpcht_attach(device_t dev)
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if (OF_getprop(node, "reg", reg, sizeof(reg)) < 12)
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return (ENXIO);
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sc->pci_sc.sc_quirks = OFW_PCI_QUIRK_RANGES_ON_CHILDREN;
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if (OF_getproplen(node, "ranges") <= 0)
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sc->pci_sc.sc_quirks = OFW_PCI_QUIRK_RANGES_ON_CHILDREN;
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sc->sc_populated_slots = 0;
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sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1], reg[2]);
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@ -214,12 +215,13 @@ cpcht_configure_htbridge(device_t dev, phandle_t child)
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int ptr, nextptr;
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uint32_t vend, val;
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int i, nirq, irq;
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u_int f, s;
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u_int b, f, s;
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sc = device_get_softc(dev);
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if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
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return;
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b = OFW_PCI_PHYS_HI_BUS(pcir.phys_hi);
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s = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
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f = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
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@ -242,41 +244,41 @@ cpcht_configure_htbridge(device_t dev, phandle_t child)
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*/
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/* All the devices we are interested in have caps */
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if (!(PCIB_READ_CONFIG(dev, 0, s, f, PCIR_STATUS, 2)
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if (!(PCIB_READ_CONFIG(dev, b, s, f, PCIR_STATUS, 2)
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& PCIM_STATUS_CAPPRESENT))
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return;
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nextptr = PCIB_READ_CONFIG(dev, 0, s, f, PCIR_CAP_PTR, 1);
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nextptr = PCIB_READ_CONFIG(dev, b, s, f, PCIR_CAP_PTR, 1);
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while (nextptr != 0) {
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ptr = nextptr;
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nextptr = PCIB_READ_CONFIG(dev, 0, s, f,
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nextptr = PCIB_READ_CONFIG(dev, b, s, f,
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ptr + PCICAP_NEXTPTR, 1);
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/* Find the HT IRQ capabilities */
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if (PCIB_READ_CONFIG(dev, 0, s, f,
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if (PCIB_READ_CONFIG(dev, b, s, f,
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ptr + PCICAP_ID, 1) != PCIY_HT)
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continue;
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val = PCIB_READ_CONFIG(dev, 0, s, f, ptr + PCIR_HT_COMMAND, 2);
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val = PCIB_READ_CONFIG(dev, b, s, f, ptr + PCIR_HT_COMMAND, 2);
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if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_INTERRUPT)
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continue;
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/* Ask for the IRQ count */
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PCIB_WRITE_CONFIG(dev, 0, s, f, ptr + PCIR_HT_COMMAND, 0x1, 1);
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nirq = PCIB_READ_CONFIG(dev, 0, s, f, ptr + 4, 4);
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PCIB_WRITE_CONFIG(dev, b, s, f, ptr + PCIR_HT_COMMAND, 0x1, 1);
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nirq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4);
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nirq = ((nirq >> 16) & 0xff) + 1;
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device_printf(dev, "%d HT IRQs on device %d.%d\n", nirq, s, f);
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for (i = 0; i < nirq; i++) {
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PCIB_WRITE_CONFIG(dev, 0, s, f,
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PCIB_WRITE_CONFIG(dev, b, s, f,
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ptr + PCIR_HT_COMMAND, 0x10 + (i << 1), 1);
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irq = PCIB_READ_CONFIG(dev, 0, s, f, ptr + 4, 4);
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irq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4);
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/*
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* Mask this interrupt for now.
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*/
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PCIB_WRITE_CONFIG(dev, 0, s, f, ptr + 4,
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PCIB_WRITE_CONFIG(dev, b, s, f, ptr + 4,
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irq | HTAPIC_MASK, 4);
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irq = (irq >> 16) & 0xff;
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@ -285,10 +287,10 @@ cpcht_configure_htbridge(device_t dev, phandle_t child)
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sc->htirq_map[irq].ht_base = sc->sc_data +
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(((((s & 0x1f) << 3) | (f & 0x07)) << 8) | (ptr));
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PCIB_WRITE_CONFIG(dev, 0, s, f,
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PCIB_WRITE_CONFIG(dev, b, s, f,
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ptr + PCIR_HT_COMMAND, 0x11 + (i << 1), 1);
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sc->htirq_map[irq].eoi_data =
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PCIB_READ_CONFIG(dev, 0, s, f, ptr + 4, 4) |
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PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4) |
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0x80000000;
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/*
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@ -296,7 +298,7 @@ cpcht_configure_htbridge(device_t dev, phandle_t child)
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* in how we signal EOIs. Check if this device was
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* made by Apple, and act accordingly.
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*/
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vend = PCIB_READ_CONFIG(dev, 0, s, f,
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vend = PCIB_READ_CONFIG(dev, b, s, f,
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PCIR_DEVVENDOR, 4);
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if ((vend & 0xffff) == 0x106b)
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sc->htirq_map[irq].apple_eoi =
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