Make a start at an unaligned trap handler. Only integer loads and stores
are handled so far.
This commit is contained in:
Doug Rabson
parent
43aba0eadb
commit
76f7435e6e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=85199
@ -69,7 +69,7 @@
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#include <ddb/ddb.h>
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#endif
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static int unaligned_fixup(struct trapframe *framep, struct thread *td);
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extern int unaligned_fixup(struct trapframe *framep, struct thread *td);
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#ifdef WITNESS
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extern char *syscallnames[];
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@ -690,78 +690,3 @@ syscall(int code, u_int64_t *args, struct trapframe *framep)
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mtx_assert(&sched_lock, MA_NOTOWNED);
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mtx_assert(&Giant, MA_NOTOWNED);
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}
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extern int ia64_unaligned_print, ia64_unaligned_fix;
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extern int ia64_unaligned_sigbus;
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static int
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unaligned_fixup(struct trapframe *framep, struct thread *td)
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{
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vm_offset_t va = framep->tf_cr_ifa;
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int doprint, dofix, dosigbus;
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int signal, size = 0;
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unsigned long uac;
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struct proc *p;
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/*
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* Figure out what actions to take.
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*/
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if (td) {
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uac = td->td_md.md_flags & MDP_UAC_MASK;
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p = td->td_proc;
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} else {
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uac = 0;
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p = NULL;
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}
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doprint = ia64_unaligned_print && !(uac & MDP_UAC_NOPRINT);
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dofix = ia64_unaligned_fix && !(uac & MDP_UAC_NOFIX);
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dosigbus = ia64_unaligned_sigbus | (uac & MDP_UAC_SIGBUS);
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/*
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* See if the user can access the memory in question.
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* Even if it's an unknown opcode, SEGV if the access
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* should have failed.
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*/
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if (!useracc((caddr_t)va, size ? size : 1, VM_PROT_WRITE)) {
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signal = SIGSEGV;
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goto out;
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}
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/*
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* If we're supposed to be noisy, squawk now.
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*/
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if (doprint) {
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uprintf("pid %d (%s): unaligned access: va=0x%lx pc=0x%lx\n",
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p->p_pid, p->p_comm, va, td->td_frame->tf_cr_iip);
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}
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/*
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* If we should try to fix it and know how, give it a shot.
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*
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* We never allow bad data to be unknowingly used by the
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* user process. That is, if we decide not to fix up an
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* access we cause a SIGBUS rather than letting the user
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* process go on without warning.
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*
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* If we're trying to do a fixup, we assume that things
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* will be botched. If everything works out OK,
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* unaligned_{load,store}_* clears the signal flag.
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*/
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signal = SIGBUS;
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if (dofix && size != 0) {
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/*
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* XXX not done yet.
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*/
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}
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/*
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* Force SIGBUS if requested.
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*/
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if (dosigbus)
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signal = SIGBUS;
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out:
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return (signal);
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}
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618
sys/ia64/ia64/unaligned.c
Normal file
618
sys/ia64/ia64/unaligned.c
Normal file
@ -0,0 +1,618 @@
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/*-
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* Copyright (c) 2001 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <machine/frame.h>
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#include <machine/inst.h>
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#define sign_extend(imm, w) (((int64_t)(imm) << (64 - (w))) >> (64 - (w)))
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extern int ia64_unaligned_print, ia64_unaligned_fix;
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extern int ia64_unaligned_sigbus;
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int unaligned_fixup(struct trapframe *framep, struct thread *td);
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enum type {
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LD_SA,
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LD_S,
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LD_A,
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LD_C_CLR,
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LD_C_NC,
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LD
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};
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struct decoding {
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int isload; /* non-zero if load */
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enum type type; /* type of load or store */
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int basereg; /* address to load or store */
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int reg; /* register number to load or store */
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int width; /* number of bytes */
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int update; /* update value for basereg */
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int updateisreg; /* non-zero if update is a register */
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int fence; /* non-zero if fence needed */
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};
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static int
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unaligned_decode_M1(union ia64_instruction ins, struct decoding *d)
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{
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static enum type types[] = {
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LD, LD_S, LD_A, LD_SA, LD,
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LD, LD, LD_C_CLR, LD_C_NC, LD_C_CLR
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};
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d->isload = 1;
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d->type = types[ins.M1.x6 >> 2];
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d->basereg = ins.M1.r3;
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d->reg = ins.M1.r1;
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d->width = (1 << (ins.M1.x6 & 3));
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if ((ins.M1.x6 >= 0x14 && ins.M1.x6 <= 0x17)
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|| (ins.M1.x6 >= 0x28 && ins.M1.x6 <= 0x2b))
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d->fence = 1;
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return 1;
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}
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static int
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unaligned_decode_M2(union ia64_instruction ins, struct decoding *d)
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{
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static enum type types[] = {
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LD, LD_S, LD_A, LD_SA, LD,
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LD, LD, LD_C_CLR, LD_C_NC, LD_C_CLR
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};
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d->isload = 1;
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d->type = types[ins.M1.x6 >> 2];
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d->basereg = ins.M2.r3;
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d->reg = ins.M2.r1;
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d->width = (1 << (ins.M2.x6 & 3));
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d->update = ins.M2.r2;
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d->updateisreg = 1;
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if ((ins.M2.x6 >= 0x14 && ins.M2.x6 <= 0x17)
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|| (ins.M2.x6 >= 0x28 && ins.M2.x6 <= 0x2b))
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d->fence = 1;
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return 1;
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}
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static int
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unaligned_decode_M3(union ia64_instruction ins, struct decoding *d)
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{
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static enum type types[] = {
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LD, LD_S, LD_A, LD_SA, LD,
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LD, LD, LD_C_CLR, LD_C_NC, LD_C_CLR
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};
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d->isload = 1;
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d->type = types[ins.M1.x6 >> 2];
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d->basereg = ins.M3.r3;
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d->reg = ins.M3.r1;
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d->width = (1 << (ins.M3.x6 & 3));
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d->update = sign_extend((ins.M3.s << 8)
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| (ins.M3.i << 7)
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| ins.M3.imm7b, 9);
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if ((ins.M3.x6 >= 0x14 && ins.M3.x6 <= 0x17)
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|| (ins.M3.x6 >= 0x28 && ins.M3.x6 <= 0x2b))
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d->fence = 1;
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return 1;
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}
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static int
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unaligned_decode_M4(union ia64_instruction ins, struct decoding *d)
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{
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d->isload = 0;
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d->basereg = ins.M4.r3;
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d->reg = ins.M4.r2;
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d->width = (1 << (ins.M4.x6 & 3));
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if (ins.M4.x6 >= 0x34 && ins.M4.x6 <= 0x37)
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d->fence = 1;
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return 1;
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}
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static int
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unaligned_decode_M5(union ia64_instruction ins, struct decoding *d)
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{
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d->isload = 0;
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d->basereg = ins.M5.r3;
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d->reg = ins.M5.r2;
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d->width = (1 << (ins.M5.x6 & 3));
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d->update = sign_extend((ins.M5.s << 8)
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| (ins.M5.i << 7)
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| ins.M5.imm7a, 9);
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if (ins.M5.x6 >= 0x34 && ins.M5.x6 <= 0x37)
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d->fence = 1;
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return 1;
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}
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static int
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rse_slot(u_int64_t *bsp)
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{
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return ((u_int64_t) bsp >> 3) & 0x3f;
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}
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/*
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* Return the address of register regno (regno >= 32) given that bsp
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* points at the base of the register stack frame.
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*/
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static u_int64_t *
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rse_register_address(u_int64_t *bsp, int regno)
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{
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int off = regno - 32;
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u_int64_t rnats = (rse_slot(bsp) + off) / 63;
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u_int64_t *p = bsp + off + rnats;
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/*
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* We only really need this if the current bspstore
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* hasn't advanced past the user's register frame. Its
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* hardly worth trying to optimise though.
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*/
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__asm __volatile("flushrs");
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return p;
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}
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static u_int64_t *
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rse_previous_frame(u_int64_t *bsp, int sof)
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{
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int slot = rse_slot(bsp);
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int rnats = 0;
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int count = sof;
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while (count > slot) {
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count -= 63;
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rnats++;
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slot = 63;
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}
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return bsp - sof - rnats;
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}
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static u_int64_t *
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rse_current_frame(struct trapframe *framep, struct thread *td)
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{
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int sof = framep->tf_cr_ifs & 0x7f;
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u_int64_t *bsp = (u_int64_t *) (td->td_kstack + framep->tf_ndirty);
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return rse_previous_frame(bsp, sof);
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}
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static int
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read_register(struct trapframe *framep, struct thread *td,
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int reg, u_int64_t *valuep)
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{
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if (reg == 0) {
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*valuep = 0;
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return 0;
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} else if (reg < 32) {
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*valuep = framep->tf_r[reg - 1];
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return 0;
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} else {
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u_int64_t cfm = framep->tf_cr_ifs;
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int sof = cfm & 0x7f;
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int sor = 8*((cfm >> 14) & 15);
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int rrb_gr = (cfm >> 18) & 0x7f;
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u_int64_t *bsp = rse_current_frame(framep, td);
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if (reg - 32 > sof)
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return EINVAL;
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if (reg - 32 < sor) {
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if (reg - 32 + rrb_gr >= sor)
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reg = reg + rrb_gr - sor;
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else
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reg = reg + rrb_gr;
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}
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*valuep = *rse_register_address(bsp, reg);
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return 0;
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}
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return EINVAL;
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}
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static int
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write_register(struct trapframe *framep, struct thread *td,
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int reg, u_int64_t value)
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{
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if (reg == 0) {
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return EINVAL; /* can't happen */
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} else if (reg < 32) {
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framep->tf_r[reg - 1] = value;
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return 0;
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} else {
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u_int64_t cfm = framep->tf_cr_ifs;
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int sof = cfm & 0x7f;
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int sor = 8*((cfm >> 14) & 15);
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int rrb_gr = (cfm >> 18) & 0x7f;
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u_int64_t *bsp = rse_current_frame(framep, td);
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if (reg - 32 > sof)
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return EINVAL;
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if (reg - 32 < sor) {
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if (reg - 32 + rrb_gr >= sor)
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reg = reg + rrb_gr - sor;
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else
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reg = reg + rrb_gr;
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}
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*rse_register_address(bsp, reg) = value;
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return 0;
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}
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return EINVAL;
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}
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/*
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* Messy.
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*/
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static void
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invala_e(int reg)
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{
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switch (reg) {
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case 0: __asm __volatile("invala.e r0"); break;
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case 1: __asm __volatile("invala.e r1"); break;
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case 2: __asm __volatile("invala.e r2"); break;
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case 3: __asm __volatile("invala.e r3"); break;
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case 4: __asm __volatile("invala.e r4"); break;
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case 5: __asm __volatile("invala.e r5"); break;
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case 6: __asm __volatile("invala.e r6"); break;
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case 7: __asm __volatile("invala.e r7"); break;
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case 8: __asm __volatile("invala.e r8"); break;
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case 9: __asm __volatile("invala.e r9"); break;
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case 10: __asm __volatile("invala.e r10"); break;
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case 11: __asm __volatile("invala.e r11"); break;
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case 12: __asm __volatile("invala.e r12"); break;
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case 13: __asm __volatile("invala.e r13"); break;
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case 14: __asm __volatile("invala.e r14"); break;
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case 15: __asm __volatile("invala.e r15"); break;
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case 16: __asm __volatile("invala.e r16"); break;
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case 17: __asm __volatile("invala.e r17"); break;
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case 18: __asm __volatile("invala.e r18"); break;
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case 19: __asm __volatile("invala.e r19"); break;
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case 20: __asm __volatile("invala.e r20"); break;
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case 21: __asm __volatile("invala.e r21"); break;
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case 22: __asm __volatile("invala.e r22"); break;
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case 23: __asm __volatile("invala.e r23"); break;
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case 24: __asm __volatile("invala.e r24"); break;
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case 25: __asm __volatile("invala.e r25"); break;
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case 26: __asm __volatile("invala.e r26"); break;
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case 27: __asm __volatile("invala.e r27"); break;
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case 28: __asm __volatile("invala.e r28"); break;
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case 29: __asm __volatile("invala.e r29"); break;
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case 30: __asm __volatile("invala.e r30"); break;
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case 31: __asm __volatile("invala.e r31"); break;
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case 32: __asm __volatile("invala.e r32"); break;
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case 33: __asm __volatile("invala.e r33"); break;
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case 34: __asm __volatile("invala.e r34"); break;
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case 35: __asm __volatile("invala.e r35"); break;
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case 36: __asm __volatile("invala.e r36"); break;
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case 37: __asm __volatile("invala.e r37"); break;
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case 38: __asm __volatile("invala.e r38"); break;
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case 39: __asm __volatile("invala.e r39"); break;
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case 40: __asm __volatile("invala.e r40"); break;
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case 41: __asm __volatile("invala.e r41"); break;
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case 42: __asm __volatile("invala.e r42"); break;
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case 43: __asm __volatile("invala.e r43"); break;
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case 44: __asm __volatile("invala.e r44"); break;
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case 45: __asm __volatile("invala.e r45"); break;
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case 46: __asm __volatile("invala.e r46"); break;
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case 47: __asm __volatile("invala.e r47"); break;
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case 48: __asm __volatile("invala.e r48"); break;
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case 49: __asm __volatile("invala.e r49"); break;
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case 50: __asm __volatile("invala.e r50"); break;
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case 51: __asm __volatile("invala.e r51"); break;
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case 52: __asm __volatile("invala.e r52"); break;
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case 53: __asm __volatile("invala.e r53"); break;
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case 54: __asm __volatile("invala.e r54"); break;
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case 55: __asm __volatile("invala.e r55"); break;
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case 56: __asm __volatile("invala.e r56"); break;
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case 57: __asm __volatile("invala.e r57"); break;
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case 58: __asm __volatile("invala.e r58"); break;
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case 59: __asm __volatile("invala.e r59"); break;
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case 60: __asm __volatile("invala.e r60"); break;
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case 61: __asm __volatile("invala.e r61"); break;
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case 62: __asm __volatile("invala.e r62"); break;
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case 63: __asm __volatile("invala.e r63"); break;
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case 64: __asm __volatile("invala.e r64"); break;
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case 65: __asm __volatile("invala.e r65"); break;
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case 66: __asm __volatile("invala.e r66"); break;
|
||||
case 67: __asm __volatile("invala.e r67"); break;
|
||||
case 68: __asm __volatile("invala.e r68"); break;
|
||||
case 69: __asm __volatile("invala.e r69"); break;
|
||||
case 70: __asm __volatile("invala.e r70"); break;
|
||||
case 71: __asm __volatile("invala.e r71"); break;
|
||||
case 72: __asm __volatile("invala.e r72"); break;
|
||||
case 73: __asm __volatile("invala.e r73"); break;
|
||||
case 74: __asm __volatile("invala.e r74"); break;
|
||||
case 75: __asm __volatile("invala.e r75"); break;
|
||||
case 76: __asm __volatile("invala.e r76"); break;
|
||||
case 77: __asm __volatile("invala.e r77"); break;
|
||||
case 78: __asm __volatile("invala.e r78"); break;
|
||||
case 79: __asm __volatile("invala.e r79"); break;
|
||||
case 80: __asm __volatile("invala.e r80"); break;
|
||||
case 81: __asm __volatile("invala.e r81"); break;
|
||||
case 82: __asm __volatile("invala.e r82"); break;
|
||||
case 83: __asm __volatile("invala.e r83"); break;
|
||||
case 84: __asm __volatile("invala.e r84"); break;
|
||||
case 85: __asm __volatile("invala.e r85"); break;
|
||||
case 86: __asm __volatile("invala.e r86"); break;
|
||||
case 87: __asm __volatile("invala.e r87"); break;
|
||||
case 88: __asm __volatile("invala.e r88"); break;
|
||||
case 89: __asm __volatile("invala.e r89"); break;
|
||||
case 90: __asm __volatile("invala.e r90"); break;
|
||||
case 91: __asm __volatile("invala.e r91"); break;
|
||||
case 92: __asm __volatile("invala.e r92"); break;
|
||||
case 93: __asm __volatile("invala.e r93"); break;
|
||||
case 94: __asm __volatile("invala.e r94"); break;
|
||||
case 95: __asm __volatile("invala.e r95"); break;
|
||||
case 96: __asm __volatile("invala.e r96"); break;
|
||||
case 97: __asm __volatile("invala.e r97"); break;
|
||||
case 98: __asm __volatile("invala.e r98"); break;
|
||||
case 99: __asm __volatile("invala.e r99"); break;
|
||||
case 100: __asm __volatile("invala.e r100"); break;
|
||||
case 101: __asm __volatile("invala.e r101"); break;
|
||||
case 102: __asm __volatile("invala.e r102"); break;
|
||||
case 103: __asm __volatile("invala.e r103"); break;
|
||||
case 104: __asm __volatile("invala.e r104"); break;
|
||||
case 105: __asm __volatile("invala.e r105"); break;
|
||||
case 106: __asm __volatile("invala.e r106"); break;
|
||||
case 107: __asm __volatile("invala.e r107"); break;
|
||||
case 108: __asm __volatile("invala.e r108"); break;
|
||||
case 109: __asm __volatile("invala.e r109"); break;
|
||||
case 110: __asm __volatile("invala.e r110"); break;
|
||||
case 111: __asm __volatile("invala.e r111"); break;
|
||||
case 112: __asm __volatile("invala.e r112"); break;
|
||||
case 113: __asm __volatile("invala.e r113"); break;
|
||||
case 114: __asm __volatile("invala.e r114"); break;
|
||||
case 115: __asm __volatile("invala.e r115"); break;
|
||||
case 116: __asm __volatile("invala.e r116"); break;
|
||||
case 117: __asm __volatile("invala.e r117"); break;
|
||||
case 118: __asm __volatile("invala.e r118"); break;
|
||||
case 119: __asm __volatile("invala.e r119"); break;
|
||||
case 120: __asm __volatile("invala.e r120"); break;
|
||||
case 121: __asm __volatile("invala.e r121"); break;
|
||||
case 122: __asm __volatile("invala.e r122"); break;
|
||||
case 123: __asm __volatile("invala.e r123"); break;
|
||||
case 124: __asm __volatile("invala.e r124"); break;
|
||||
case 125: __asm __volatile("invala.e r125"); break;
|
||||
case 126: __asm __volatile("invala.e r126"); break;
|
||||
case 127: __asm __volatile("invala.e r127"); break;
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
unaligned_fixup(struct trapframe *framep, struct thread *td)
|
||||
{
|
||||
vm_offset_t va = framep->tf_cr_ifa;
|
||||
int doprint, dofix, dosigbus;
|
||||
int signal, size = 0;
|
||||
unsigned long uac;
|
||||
struct proc *p;
|
||||
u_int64_t low, high;
|
||||
struct ia64_bundle b;
|
||||
int slot;
|
||||
union ia64_instruction ins;
|
||||
int decoded;
|
||||
struct decoding dec;
|
||||
|
||||
/*
|
||||
* Figure out what actions to take.
|
||||
*/
|
||||
|
||||
if (td) {
|
||||
uac = td->td_md.md_flags & MDP_UAC_MASK;
|
||||
p = td->td_proc;
|
||||
} else {
|
||||
uac = 0;
|
||||
p = NULL;
|
||||
}
|
||||
|
||||
doprint = ia64_unaligned_print && !(uac & MDP_UAC_NOPRINT);
|
||||
dofix = ia64_unaligned_fix && !(uac & MDP_UAC_NOFIX);
|
||||
dosigbus = ia64_unaligned_sigbus | (uac & MDP_UAC_SIGBUS);
|
||||
|
||||
/*
|
||||
* If psr.ac is set, then clearly the user program *wants* to
|
||||
* fault.
|
||||
*/
|
||||
if (framep->tf_cr_ipsr & IA64_PSR_AC) {
|
||||
dofix = 0;
|
||||
dosigbus = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* See if the user can access the memory in question.
|
||||
* Even if it's an unknown opcode, SEGV if the access
|
||||
* should have failed.
|
||||
*/
|
||||
if (!useracc((caddr_t)va, size ? size : 1, VM_PROT_WRITE)) {
|
||||
signal = SIGSEGV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the instruction bundle and attempt to decode the
|
||||
* offending instruction.
|
||||
* XXX assume that the instruction is in an 'M' slot.
|
||||
*/
|
||||
copyin((const void *) framep->tf_cr_iip, &low, 8);
|
||||
copyin((const void *) (framep->tf_cr_iip + 8), &high, 8);
|
||||
ia64_unpack_bundle(low, high, &b);
|
||||
slot = (framep->tf_cr_ipsr >> 41) & 3;
|
||||
ins.ins = b.slot[slot];
|
||||
|
||||
decoded = 0;
|
||||
bzero(&dec, sizeof(dec));
|
||||
if (ins.M1.op == 4) {
|
||||
if (ins.M1.m == 0 && ins.M1.x == 0) {
|
||||
/* Table 4-29 */
|
||||
if (ins.M1.x6 < 0x30)
|
||||
decoded = unaligned_decode_M1(ins, &dec);
|
||||
else
|
||||
decoded = unaligned_decode_M4(ins, &dec);
|
||||
} else if (ins.M1.m == 1 && ins.M1.x == 0) {
|
||||
/* Table 4-30 */
|
||||
decoded = unaligned_decode_M2(ins, &dec);
|
||||
}
|
||||
} else if (ins.M1.op == 5) {
|
||||
/* Table 4-31 */
|
||||
if (ins.M1.x6 < 0x30)
|
||||
decoded = unaligned_decode_M3(ins, &dec);
|
||||
else
|
||||
decoded = unaligned_decode_M5(ins, &dec);
|
||||
}
|
||||
|
||||
/*
|
||||
* If we're supposed to be noisy, squawk now.
|
||||
*/
|
||||
if (doprint) {
|
||||
uprintf("pid %d (%s): unaligned access: va=0x%lx pc=0x%lx",
|
||||
p->p_pid, p->p_comm, va, framep->tf_cr_iip);
|
||||
if (decoded) {
|
||||
uprintf(" op=");
|
||||
if (dec.isload) {
|
||||
static char *ldops[] = {
|
||||
"ld%d.sa", "ld%d.s", "ld%d.a",
|
||||
"ld%d.c.clr", "ld%d.c.nc", "ld%d"
|
||||
};
|
||||
uprintf(ldops[dec.type], dec.width);
|
||||
uprintf(" r%d=[r%d]", dec.reg, dec.basereg);
|
||||
} else {
|
||||
uprintf("st%d [r%d]=r%d", dec.width,
|
||||
dec.basereg, dec.reg);
|
||||
}
|
||||
if (dec.updateisreg)
|
||||
uprintf(",r%d\n", dec.update);
|
||||
else if (dec.update)
|
||||
uprintf(",%d\n", dec.update);
|
||||
else
|
||||
uprintf("\n");
|
||||
} else {
|
||||
uprintf("\n");
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If we should try to fix it and know how, give it a shot.
|
||||
*
|
||||
* We never allow bad data to be unknowingly used by the
|
||||
* user process. That is, if we decide not to fix up an
|
||||
* access we cause a SIGBUS rather than letting the user
|
||||
* process go on without warning.
|
||||
*
|
||||
* If we're trying to do a fixup, we assume that things
|
||||
* will be botched. If everything works out OK,
|
||||
* unaligned_{load,store}_* clears the signal flag.
|
||||
*/
|
||||
signal = 0;
|
||||
if (dofix && decoded) {
|
||||
u_int64_t addr, update, value, isr;
|
||||
int error = 0;
|
||||
|
||||
isr = framep->tf_cr_isr;
|
||||
error = read_register(framep, td, dec.basereg, &addr);
|
||||
if (error) {
|
||||
signal = SIGBUS;
|
||||
goto out;
|
||||
}
|
||||
if (dec.updateisreg) {
|
||||
error = read_register(framep, td, dec.update, &update);
|
||||
if (error) {
|
||||
signal = SIGBUS;
|
||||
goto out;
|
||||
}
|
||||
} else {
|
||||
update = dec.update;
|
||||
}
|
||||
|
||||
/* Assume little-endian */
|
||||
if (dec.isload) {
|
||||
/*
|
||||
* Sanity checks.
|
||||
*/
|
||||
if (!(isr & IA64_ISR_R)
|
||||
|| (isr & (IA64_ISR_W|IA64_ISR_X|IA64_ISR_NA))) {
|
||||
printf("unaligned_fixup: unexpected cr.isr value\n");
|
||||
signal = SIGBUS;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (dec.type == LD_SA || dec.type == LD_A) {
|
||||
invala_e(dec.reg);
|
||||
goto out;
|
||||
}
|
||||
if (dec.type == LD_C_CLR)
|
||||
invala_e(dec.reg);
|
||||
if (dec.type == LD_S)
|
||||
/* XXX not quite sure what to do here */;
|
||||
|
||||
value = 0;
|
||||
if (!error && dec.fence)
|
||||
ia64_mf();
|
||||
error = copyin((const void *)addr, &value, dec.width);
|
||||
if (!error)
|
||||
error = write_register(framep, td, dec.reg,
|
||||
value);
|
||||
if (!error && update)
|
||||
error = write_register(framep, td, dec.basereg,
|
||||
addr + update);
|
||||
} else {
|
||||
error = read_register(framep, td, dec.reg, &value);
|
||||
if (!error)
|
||||
error = copyout(&value, (void *)addr,
|
||||
dec.width);
|
||||
if (!error && dec.fence)
|
||||
ia64_mf();
|
||||
if (!error && update)
|
||||
error = write_register(framep, td, dec.basereg,
|
||||
addr + update);
|
||||
}
|
||||
if (error) {
|
||||
signal = SIGBUS;
|
||||
} else {
|
||||
/*
|
||||
* Advance to the instruction following the
|
||||
* one which faulted.
|
||||
*/
|
||||
if ((framep->tf_cr_ipsr & IA64_PSR_RI)
|
||||
== IA64_PSR_RI_2) {
|
||||
framep->tf_cr_ipsr &= ~IA64_PSR_RI;
|
||||
framep->tf_cr_iip += 16;
|
||||
} else {
|
||||
framep->tf_cr_ipsr += IA64_PSR_RI_1;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
signal = SIGBUS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Force SIGBUS if requested.
|
||||
*/
|
||||
if (dosigbus)
|
||||
signal = SIGBUS;
|
||||
|
||||
out:
|
||||
return (signal);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user