- Refine pc98 supports.
- Use bus_space stuff. - Rename FDO_* -> FDC_* (obtained from NetBSD/pc98)
This commit is contained in:
Yoshihiro Takahashi
parent
cde2e82802
commit
77663c3006
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=79704
@ -76,23 +76,40 @@ struct fdc_data
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int fdu; /* the active drive */
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enum fdc_states state;
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int retry;
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#ifndef PC98
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int fdout; /* mirror of the w/o digital output reg */
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#endif
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u_int status[7]; /* copy of the registers */
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enum fdc_type fdct; /* chip version of FDC */
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int fdc_errs; /* number of logged errors */
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int dma_overruns; /* number of DMA overruns */
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struct bio_queue_head head;
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struct bio *bp; /* active buffer */
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#ifdef PC98
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struct resource *res_ioport, *res_fdsio, *res_fdemsio;
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struct resource *res_irq, *res_drq;
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int rid_ioport, rid_irq, rid_drq;
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#else
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struct resource *res_ioport, *res_ctl, *res_irq, *res_drq;
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int rid_ioport, rid_ctl, rid_irq, rid_drq;
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#endif
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int port_off;
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bus_space_tag_t portt;
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bus_space_handle_t porth;
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#ifdef PC98
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bus_space_tag_t sc_fdsiot;
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bus_space_handle_t sc_fdsioh;
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bus_space_tag_t sc_fdemsiot;
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bus_space_handle_t sc_fdemsioh;
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#else
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bus_space_tag_t ctlt;
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bus_space_handle_t ctlh;
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#endif
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void *fdc_intr;
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struct device *fdc_dev;
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#ifndef PC98
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void (*fdctl_wr)(struct fdc_data *fdc, u_int8_t v);
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#endif
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};
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/***********************************************************************\
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@ -180,6 +180,10 @@ static struct fd_type fd_types[NUMTYPES] =
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#endif
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};
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#ifdef PC98
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static bus_addr_t fdc_iat[] = {0, 2, 4};
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#endif
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#ifdef PC98
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#define DRVS_PER_CTLR 4 /* 4 floppies */
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#else
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@ -272,13 +276,8 @@ static inline u_short
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nrd_info(addr)
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nrd_t addr;
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{
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u_short tmp;
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nrd_addr(addr);
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outb(0x43f, 0x42);
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tmp = (short)inw(P_NRD_DATA);
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outb(0x43f, 0x40);
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return ((u_short)tmp);
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return (epson_inw(P_NRD_DATA));
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}
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#endif /* EPSON_NRDISK */
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@ -342,11 +341,13 @@ static int volatile fd_debug = 0;
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#define TRACE1(arg1, arg2)
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#endif /* FDC_DEBUG */
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#ifndef PC98
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static void
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fdout_wr(fdc_p fdc, u_int8_t v)
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{
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bus_space_write_1(fdc->portt, fdc->porth, FDOUT+fdc->port_off, v);
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}
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#endif
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static u_int8_t
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fdsts_rd(fdc_p fdc)
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@ -366,6 +367,14 @@ fddata_rd(fdc_p fdc)
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return bus_space_read_1(fdc->portt, fdc->porth, FDDATA+fdc->port_off);
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}
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#ifdef PC98
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static void
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fdctl_wr(fdc_p fdc, u_int8_t v)
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{
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bus_space_write_1(fdc->portt, fdc->porth, FDCTL, v);
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}
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#endif
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#ifndef PC98
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static void
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fdctl_wr_isa(fdc_p fdc, u_int8_t v)
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@ -635,9 +644,10 @@ static int pc98_trans_prev = 0;
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static void set_density(fdc_p fdc)
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{
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/* always motor on */
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outb(IO_FDPORT, (pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
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bus_space_write_1(fdc->sc_fdsiot, fdc->sc_fdsioh, 0,
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(pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
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DELAY(100);
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fdout_wr(fdc, FDO_RST | FDO_DMAE);
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fdctl_wr(fdc, FDC_RST | FDC_DMAE);
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/* in the case of note W, always inhibit 100ms timer */
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}
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@ -661,7 +671,7 @@ static int pc98_fd_check_ready(fdu_t fdu)
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DELAY(100);
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fd_in(fdc, &status);
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if ((status & NE7_ST3_RD)) {
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fdout_wr(fdc, FDO_DMAE | FDO_MTON);
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fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
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DELAY(10);
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return 0;
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}
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@ -675,7 +685,9 @@ fdc_alloc_resources(struct fdc_data *fdc)
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{
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device_t dev;
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int ispnp, ispcmcia;
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#ifdef PC98
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int rid;
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#endif
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dev = fdc->fdc_dev;
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ispnp = (fdc->flags & FDC_ISPNP) != 0;
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ispcmcia = (fdc->flags & FDC_ISPCMCIA) != 0;
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@ -683,10 +695,9 @@ fdc_alloc_resources(struct fdc_data *fdc)
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fdc->res_ioport = fdc->res_irq = fdc->res_drq = 0;
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#ifdef PC98
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fdc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
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&fdc->rid_ioport, 0ul, ~0ul,
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ispnp ? 1 : IO_FDCSIZE,
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RF_ACTIVE);
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fdc->res_ioport = isa_alloc_resourcev(dev, SYS_RES_IOPORT,
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&fdc->rid_ioport, fdc_iat,
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3, RF_ACTIVE);
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#else
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/*
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* On standard ISA, we don't just use an 8 port range
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@ -708,9 +719,32 @@ fdc_alloc_resources(struct fdc_data *fdc)
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device_printf(dev, "cannot reserve I/O port range\n");
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return ENXIO;
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}
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#ifdef PC98
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isa_load_resourcev(fdc->res_ioport, fdc_iat, 3);
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#endif
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fdc->portt = rman_get_bustag(fdc->res_ioport);
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fdc->porth = rman_get_bushandle(fdc->res_ioport);
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#ifdef PC98
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rid = 3;
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bus_set_resource(dev, SYS_RES_IOPORT, rid, IO_FDPORT, 1);
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fdc->res_fdsio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
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1, RF_ACTIVE);
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if (fdc->res_fdsio == 0)
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return ENXIO;
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fdc->sc_fdsiot = rman_get_bustag(fdc->res_fdsio);
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fdc->sc_fdsioh = rman_get_bushandle(fdc->res_fdsio);
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rid = 4;
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bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x4be, 1);
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fdc->res_fdemsio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
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1, RF_ACTIVE);
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if (fdc->res_fdemsio == 0)
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return ENXIO;
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fdc->sc_fdemsiot = rman_get_bustag(fdc->res_fdemsio);
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fdc->sc_fdemsioh = rman_get_bushandle(fdc->res_fdemsio);
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#endif
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#ifndef PC98
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if (!ispcmcia) {
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/*
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@ -803,6 +837,18 @@ fdc_release_resources(struct fdc_data *fdc)
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bus_release_resource(dev, SYS_RES_IOPORT, fdc->rid_ctl,
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fdc->res_ctl);
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}
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#endif
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#ifdef PC98
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if (fdc->res_fdsio != 0) {
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bus_deactivate_resource(dev, SYS_RES_IOPORT, 3,
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fdc->res_fdsio);
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bus_release_resource(dev, SYS_RES_IOPORT, 3, fdc->res_fdsio);
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}
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if (fdc->res_fdemsio != 0) {
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bus_deactivate_resource(dev, SYS_RES_IOPORT, 4,
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fdc->res_fdemsio);
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bus_release_resource(dev, SYS_RES_IOPORT, 4, fdc->res_fdemsio);
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}
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#endif
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if (fdc->res_ioport != 0) {
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bus_deactivate_resource(dev, SYS_RES_IOPORT, fdc->rid_ioport,
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@ -1371,8 +1417,10 @@ fd_probe(device_t dev)
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case FDT_144M:
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/* Check 3mode I/F */
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fd->pc98_trans = 0;
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outb(0x4be, (fd->fdu << 5) | 0x10);
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if (!(inb(0x4be) & 0x01)) {
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bus_space_write_1(fdc->sc_fdemsiot, fdc->sc_fdemsioh, 0,
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(fd->fdu << 5) | 0x10);
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if (!(bus_space_read_1(fdc->sc_fdemsiot, fdc->sc_fdemsioh, 0) &
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0x01)) {
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device_set_desc(dev, "1.44M FDD");
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fd->type = FD_1440;
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break;
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@ -1493,14 +1541,15 @@ DRIVER_MODULE(fd, fdc, fd_driver, fd_devclass, 0, 0);
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static void
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set_motor(struct fdc_data *fdc, int fdsu, int turnon)
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{
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#ifdef PC98
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bus_space_write_1(fdc->sc_fdsiot, fdc->sc_fdsioh, 0,
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(pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
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DELAY(10);
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fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
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#else
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int fdout = fdc->fdout;
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int needspecify = 0;
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#ifdef PC98
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outb(IO_FDPORT, (pc98_trans != 1 ? FDP_FDDEXC : 0)|FDP_PORTEXC);
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DELAY(10);
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fdout = FDO_DMAE|FDO_MTON;
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#else
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if(turnon) {
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fdout &= ~FDO_FDSEL;
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fdout |= (FDO_MOEN0 << fdsu) + fdsu;
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@ -1517,7 +1566,6 @@ set_motor(struct fdc_data *fdc, int fdsu, int turnon)
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needspecify = 1;
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fdout |= (FDO_FRST|FDO_FDMAEN);
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}
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#endif
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fdout_wr(fdc, fdout);
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fdc->fdout = fdout;
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@ -1544,6 +1592,7 @@ set_motor(struct fdc_data *fdc, int fdsu, int turnon)
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if (fdc->flags & FDC_HAS_FIFO)
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(void) enable_fifo(fdc);
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}
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#endif
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}
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static void
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@ -1607,11 +1656,11 @@ fdc_reset(fdc_p fdc)
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#ifdef PC98
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set_density(fdc);
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if (pc98_machine_type & M_EPSON_PC98)
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fdout_wr(fdc, 0xe8);
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fdctl_wr(fdc, FDC_RST | FDC_RDY | FDC_DD | FDC_MTON);
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else
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fdout_wr(fdc, 0xd8);
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fdctl_wr(fdc, FDC_RST | FDC_RDY | FDC_DMAE | FDC_MTON);
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DELAY(200);
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fdout_wr(fdc, 0x18);
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fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
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DELAY(10);
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#else
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fdout_wr(fdc, fdc->fdout & ~(FDO_FRST|FDO_FDMAEN));
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@ -2074,7 +2123,11 @@ fdstate(fdc_p fdc)
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}
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if (pc98_trans != fd->pc98_trans) {
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if (fd->type == FD_1440) {
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outb(0x4be, (fdu << 5) | 0x10 | (pc98_trans >> 1));
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bus_space_write_1(fdc->sc_fdemsiot,
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fdc->sc_fdemsioh,
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0,
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(fdu << 5) | 0x10 |
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(pc98_trans >> 1));
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outb(0x5f, 0);
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outb(0x5f, 0);
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}
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@ -44,24 +44,15 @@
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#ifdef PC98
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/* registers */
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#define FDSTS 0 /* NEC 765 Main Status Register (R) */
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#define FDDATA 2 /* NEC 765 Data Register (R/W) */
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#define FDOUT 4 /* Digital Output Register (W) */
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#define FDO_RST 0x80 /* FDC RESET */
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#define FDO_FRY 0x40 /* force READY */
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#define FDO_AIE 0x20 /* Attention Interrupt Enable */
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#define FDO_DD 0x20 /* FDD Mode Exchange 0:1M 1:640K */
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#define FDO_DMAE 0x10 /* enable floppy DMA */
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#define FDO_MTON 0x08 /* MOTOR ON (when EMTON=1)*/
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#define FDO_TMSK 0x04 /* TIMER MASK */
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#define FDO_TTRG 0x01 /* TIMER TRIGER */
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#define FDIN 4 /* Digital Input Register (R) */
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#define FDI_TYP0 0x04 /* FDD #1/#2 TYPE */
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#define FDI_TYP1 0x08 /* FDD #3/#4 TYPE */
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#define FDI_RDY 0x10 /* Ready */
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#define FDI_DMACH 0x20 /* DMA Channel */
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#define FDI_FINT0 0x40 /* Interrupt */
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#define FDI_FINT1 0x80 /* Interrupt */
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#define FDDATA 1 /* NEC 765 Data Register (R/W) */
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#define FDCTL 2 /* FD Control Register */
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#define FDC_RST 0x80 /* FDC RESET */
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#define FDC_RDY 0x40 /* force READY */
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#define FDC_DD 0x20 /* FDD Mode Exchange 0:1M 1:640K */
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#define FDC_DMAE 0x10 /* enable floppy DMA */
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#define FDC_MTON 0x08 /* MOTOR ON (when EMTON=1)*/
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#define FDC_TMSK 0x04 /* TIMER MASK */
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#define FDC_TTRG 0x01 /* TIMER TRIGER */
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#define FDP_EMTON 0x04 /* enable MTON */
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#define FDP_FDDEXC 0x02 /* FDD Mode Exchange 1:1M 0:640K */
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@ -81,6 +72,7 @@
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#define FDSTS 4 /* NEC 765 Main Status Register (R) */
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#define FDDATA 5 /* NEC 765 Data Register (R/W) */
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#define FDCTL 7 /* Control Register (W) */
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#endif /* PC98 */
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#ifndef FDC_500KBPS
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# define FDC_500KBPS 0x00 /* 500KBPS MFM drive transfer rate */
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@ -89,7 +81,6 @@
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# define FDC_125KBPS 0x03 /* 125KBPS FM drive transfer rate */
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/* for some controllers 1MPBS instead */
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#endif /* FDC_500KBPS */
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#endif /* PC98 */
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/*
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* this is the secret PIO data port (offset from base)
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@ -180,6 +180,10 @@ static struct fd_type fd_types[NUMTYPES] =
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#endif
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};
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#ifdef PC98
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static bus_addr_t fdc_iat[] = {0, 2, 4};
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#endif
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#ifdef PC98
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#define DRVS_PER_CTLR 4 /* 4 floppies */
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#else
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@ -272,13 +276,8 @@ static inline u_short
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nrd_info(addr)
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nrd_t addr;
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{
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u_short tmp;
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nrd_addr(addr);
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outb(0x43f, 0x42);
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tmp = (short)inw(P_NRD_DATA);
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outb(0x43f, 0x40);
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return ((u_short)tmp);
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return (epson_inw(P_NRD_DATA));
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}
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#endif /* EPSON_NRDISK */
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@ -342,11 +341,13 @@ static int volatile fd_debug = 0;
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#define TRACE1(arg1, arg2)
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#endif /* FDC_DEBUG */
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#ifndef PC98
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static void
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fdout_wr(fdc_p fdc, u_int8_t v)
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{
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bus_space_write_1(fdc->portt, fdc->porth, FDOUT+fdc->port_off, v);
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}
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#endif
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static u_int8_t
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fdsts_rd(fdc_p fdc)
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@ -366,6 +367,14 @@ fddata_rd(fdc_p fdc)
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return bus_space_read_1(fdc->portt, fdc->porth, FDDATA+fdc->port_off);
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}
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#ifdef PC98
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static void
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fdctl_wr(fdc_p fdc, u_int8_t v)
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{
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bus_space_write_1(fdc->portt, fdc->porth, FDCTL, v);
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}
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#endif
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#ifndef PC98
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static void
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fdctl_wr_isa(fdc_p fdc, u_int8_t v)
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@ -635,9 +644,10 @@ static int pc98_trans_prev = 0;
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static void set_density(fdc_p fdc)
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{
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/* always motor on */
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outb(IO_FDPORT, (pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
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bus_space_write_1(fdc->sc_fdsiot, fdc->sc_fdsioh, 0,
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(pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
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DELAY(100);
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fdout_wr(fdc, FDO_RST | FDO_DMAE);
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fdctl_wr(fdc, FDC_RST | FDC_DMAE);
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/* in the case of note W, always inhibit 100ms timer */
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}
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@ -661,7 +671,7 @@ static int pc98_fd_check_ready(fdu_t fdu)
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DELAY(100);
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fd_in(fdc, &status);
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if ((status & NE7_ST3_RD)) {
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fdout_wr(fdc, FDO_DMAE | FDO_MTON);
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fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
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DELAY(10);
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return 0;
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}
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@ -675,7 +685,9 @@ fdc_alloc_resources(struct fdc_data *fdc)
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{
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device_t dev;
|
||||
int ispnp, ispcmcia;
|
||||
|
||||
#ifdef PC98
|
||||
int rid;
|
||||
#endif
|
||||
dev = fdc->fdc_dev;
|
||||
ispnp = (fdc->flags & FDC_ISPNP) != 0;
|
||||
ispcmcia = (fdc->flags & FDC_ISPCMCIA) != 0;
|
||||
@ -683,10 +695,9 @@ fdc_alloc_resources(struct fdc_data *fdc)
|
||||
fdc->res_ioport = fdc->res_irq = fdc->res_drq = 0;
|
||||
|
||||
#ifdef PC98
|
||||
fdc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
|
||||
&fdc->rid_ioport, 0ul, ~0ul,
|
||||
ispnp ? 1 : IO_FDCSIZE,
|
||||
RF_ACTIVE);
|
||||
fdc->res_ioport = isa_alloc_resourcev(dev, SYS_RES_IOPORT,
|
||||
&fdc->rid_ioport, fdc_iat,
|
||||
3, RF_ACTIVE);
|
||||
#else
|
||||
/*
|
||||
* On standard ISA, we don't just use an 8 port range
|
||||
@ -708,9 +719,32 @@ fdc_alloc_resources(struct fdc_data *fdc)
|
||||
device_printf(dev, "cannot reserve I/O port range\n");
|
||||
return ENXIO;
|
||||
}
|
||||
#ifdef PC98
|
||||
isa_load_resourcev(fdc->res_ioport, fdc_iat, 3);
|
||||
#endif
|
||||
fdc->portt = rman_get_bustag(fdc->res_ioport);
|
||||
fdc->porth = rman_get_bushandle(fdc->res_ioport);
|
||||
|
||||
#ifdef PC98
|
||||
rid = 3;
|
||||
bus_set_resource(dev, SYS_RES_IOPORT, rid, IO_FDPORT, 1);
|
||||
fdc->res_fdsio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
|
||||
1, RF_ACTIVE);
|
||||
if (fdc->res_fdsio == 0)
|
||||
return ENXIO;
|
||||
fdc->sc_fdsiot = rman_get_bustag(fdc->res_fdsio);
|
||||
fdc->sc_fdsioh = rman_get_bushandle(fdc->res_fdsio);
|
||||
|
||||
rid = 4;
|
||||
bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x4be, 1);
|
||||
fdc->res_fdemsio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
|
||||
1, RF_ACTIVE);
|
||||
if (fdc->res_fdemsio == 0)
|
||||
return ENXIO;
|
||||
fdc->sc_fdemsiot = rman_get_bustag(fdc->res_fdemsio);
|
||||
fdc->sc_fdemsioh = rman_get_bushandle(fdc->res_fdemsio);
|
||||
#endif
|
||||
|
||||
#ifndef PC98
|
||||
if (!ispcmcia) {
|
||||
/*
|
||||
@ -803,6 +837,18 @@ fdc_release_resources(struct fdc_data *fdc)
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, fdc->rid_ctl,
|
||||
fdc->res_ctl);
|
||||
}
|
||||
#endif
|
||||
#ifdef PC98
|
||||
if (fdc->res_fdsio != 0) {
|
||||
bus_deactivate_resource(dev, SYS_RES_IOPORT, 3,
|
||||
fdc->res_fdsio);
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, 3, fdc->res_fdsio);
|
||||
}
|
||||
if (fdc->res_fdemsio != 0) {
|
||||
bus_deactivate_resource(dev, SYS_RES_IOPORT, 4,
|
||||
fdc->res_fdemsio);
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, 4, fdc->res_fdemsio);
|
||||
}
|
||||
#endif
|
||||
if (fdc->res_ioport != 0) {
|
||||
bus_deactivate_resource(dev, SYS_RES_IOPORT, fdc->rid_ioport,
|
||||
@ -1371,8 +1417,10 @@ fd_probe(device_t dev)
|
||||
case FDT_144M:
|
||||
/* Check 3mode I/F */
|
||||
fd->pc98_trans = 0;
|
||||
outb(0x4be, (fd->fdu << 5) | 0x10);
|
||||
if (!(inb(0x4be) & 0x01)) {
|
||||
bus_space_write_1(fdc->sc_fdemsiot, fdc->sc_fdemsioh, 0,
|
||||
(fd->fdu << 5) | 0x10);
|
||||
if (!(bus_space_read_1(fdc->sc_fdemsiot, fdc->sc_fdemsioh, 0) &
|
||||
0x01)) {
|
||||
device_set_desc(dev, "1.44M FDD");
|
||||
fd->type = FD_1440;
|
||||
break;
|
||||
@ -1493,14 +1541,15 @@ DRIVER_MODULE(fd, fdc, fd_driver, fd_devclass, 0, 0);
|
||||
static void
|
||||
set_motor(struct fdc_data *fdc, int fdsu, int turnon)
|
||||
{
|
||||
#ifdef PC98
|
||||
bus_space_write_1(fdc->sc_fdsiot, fdc->sc_fdsioh, 0,
|
||||
(pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
|
||||
DELAY(10);
|
||||
fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
|
||||
#else
|
||||
int fdout = fdc->fdout;
|
||||
int needspecify = 0;
|
||||
|
||||
#ifdef PC98
|
||||
outb(IO_FDPORT, (pc98_trans != 1 ? FDP_FDDEXC : 0)|FDP_PORTEXC);
|
||||
DELAY(10);
|
||||
fdout = FDO_DMAE|FDO_MTON;
|
||||
#else
|
||||
if(turnon) {
|
||||
fdout &= ~FDO_FDSEL;
|
||||
fdout |= (FDO_MOEN0 << fdsu) + fdsu;
|
||||
@ -1517,7 +1566,6 @@ set_motor(struct fdc_data *fdc, int fdsu, int turnon)
|
||||
needspecify = 1;
|
||||
fdout |= (FDO_FRST|FDO_FDMAEN);
|
||||
}
|
||||
#endif
|
||||
|
||||
fdout_wr(fdc, fdout);
|
||||
fdc->fdout = fdout;
|
||||
@ -1544,6 +1592,7 @@ set_motor(struct fdc_data *fdc, int fdsu, int turnon)
|
||||
if (fdc->flags & FDC_HAS_FIFO)
|
||||
(void) enable_fifo(fdc);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
@ -1607,11 +1656,11 @@ fdc_reset(fdc_p fdc)
|
||||
#ifdef PC98
|
||||
set_density(fdc);
|
||||
if (pc98_machine_type & M_EPSON_PC98)
|
||||
fdout_wr(fdc, 0xe8);
|
||||
fdctl_wr(fdc, FDC_RST | FDC_RDY | FDC_DD | FDC_MTON);
|
||||
else
|
||||
fdout_wr(fdc, 0xd8);
|
||||
fdctl_wr(fdc, FDC_RST | FDC_RDY | FDC_DMAE | FDC_MTON);
|
||||
DELAY(200);
|
||||
fdout_wr(fdc, 0x18);
|
||||
fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
|
||||
DELAY(10);
|
||||
#else
|
||||
fdout_wr(fdc, fdc->fdout & ~(FDO_FRST|FDO_FDMAEN));
|
||||
@ -2074,7 +2123,11 @@ fdstate(fdc_p fdc)
|
||||
}
|
||||
if (pc98_trans != fd->pc98_trans) {
|
||||
if (fd->type == FD_1440) {
|
||||
outb(0x4be, (fdu << 5) | 0x10 | (pc98_trans >> 1));
|
||||
bus_space_write_1(fdc->sc_fdemsiot,
|
||||
fdc->sc_fdemsioh,
|
||||
0,
|
||||
(fdu << 5) | 0x10 |
|
||||
(pc98_trans >> 1));
|
||||
outb(0x5f, 0);
|
||||
outb(0x5f, 0);
|
||||
}
|
||||
|
||||
@ -44,24 +44,15 @@
|
||||
#ifdef PC98
|
||||
/* registers */
|
||||
#define FDSTS 0 /* NEC 765 Main Status Register (R) */
|
||||
#define FDDATA 2 /* NEC 765 Data Register (R/W) */
|
||||
#define FDOUT 4 /* Digital Output Register (W) */
|
||||
#define FDO_RST 0x80 /* FDC RESET */
|
||||
#define FDO_FRY 0x40 /* force READY */
|
||||
#define FDO_AIE 0x20 /* Attention Interrupt Enable */
|
||||
#define FDO_DD 0x20 /* FDD Mode Exchange 0:1M 1:640K */
|
||||
#define FDO_DMAE 0x10 /* enable floppy DMA */
|
||||
#define FDO_MTON 0x08 /* MOTOR ON (when EMTON=1)*/
|
||||
#define FDO_TMSK 0x04 /* TIMER MASK */
|
||||
#define FDO_TTRG 0x01 /* TIMER TRIGER */
|
||||
|
||||
#define FDIN 4 /* Digital Input Register (R) */
|
||||
#define FDI_TYP0 0x04 /* FDD #1/#2 TYPE */
|
||||
#define FDI_TYP1 0x08 /* FDD #3/#4 TYPE */
|
||||
#define FDI_RDY 0x10 /* Ready */
|
||||
#define FDI_DMACH 0x20 /* DMA Channel */
|
||||
#define FDI_FINT0 0x40 /* Interrupt */
|
||||
#define FDI_FINT1 0x80 /* Interrupt */
|
||||
#define FDDATA 1 /* NEC 765 Data Register (R/W) */
|
||||
#define FDCTL 2 /* FD Control Register */
|
||||
#define FDC_RST 0x80 /* FDC RESET */
|
||||
#define FDC_RDY 0x40 /* force READY */
|
||||
#define FDC_DD 0x20 /* FDD Mode Exchange 0:1M 1:640K */
|
||||
#define FDC_DMAE 0x10 /* enable floppy DMA */
|
||||
#define FDC_MTON 0x08 /* MOTOR ON (when EMTON=1)*/
|
||||
#define FDC_TMSK 0x04 /* TIMER MASK */
|
||||
#define FDC_TTRG 0x01 /* TIMER TRIGER */
|
||||
|
||||
#define FDP_EMTON 0x04 /* enable MTON */
|
||||
#define FDP_FDDEXC 0x02 /* FDD Mode Exchange 1:1M 0:640K */
|
||||
@ -81,6 +72,7 @@
|
||||
#define FDSTS 4 /* NEC 765 Main Status Register (R) */
|
||||
#define FDDATA 5 /* NEC 765 Data Register (R/W) */
|
||||
#define FDCTL 7 /* Control Register (W) */
|
||||
#endif /* PC98 */
|
||||
|
||||
#ifndef FDC_500KBPS
|
||||
# define FDC_500KBPS 0x00 /* 500KBPS MFM drive transfer rate */
|
||||
@ -89,7 +81,6 @@
|
||||
# define FDC_125KBPS 0x03 /* 125KBPS FM drive transfer rate */
|
||||
/* for some controllers 1MPBS instead */
|
||||
#endif /* FDC_500KBPS */
|
||||
#endif /* PC98 */
|
||||
|
||||
/*
|
||||
* this is the secret PIO data port (offset from base)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user