- Refine pc98 supports.

- Use bus_space stuff.
- Rename FDO_* -> FDC_* (obtained from NetBSD/pc98)

sys/isa/fdc.h

@@ -76,23 +76,40 @@ struct fdc_data
 	int	fdu;		/* the active drive	*/
 	enum	fdc_states state;
 	int	retry;
+#ifndef PC98
 	int	fdout;		/* mirror of the w/o digital output reg */
+#endif
 	u_int	status[7];	/* copy of the registers */
 	enum	fdc_type fdct;	/* chip version of FDC */
 	int	fdc_errs;	/* number of logged errors */
 	int	dma_overruns;	/* number of DMA overruns */
 	struct	bio_queue_head head;
 	struct	bio *bp;	/* active buffer */
+#ifdef PC98
+	struct	resource *res_ioport, *res_fdsio, *res_fdemsio;
+	struct	resource *res_irq, *res_drq;
+	int	rid_ioport, rid_irq, rid_drq;
+#else
 	struct	resource *res_ioport, *res_ctl, *res_irq, *res_drq;
 	int	rid_ioport, rid_ctl, rid_irq, rid_drq;
+#endif
 	int	port_off;
 	bus_space_tag_t portt;
 	bus_space_handle_t porth;
+#ifdef PC98
+        bus_space_tag_t		sc_fdsiot;
+        bus_space_handle_t	sc_fdsioh;
+        bus_space_tag_t		sc_fdemsiot;
+        bus_space_handle_t	sc_fdemsioh;
+#else
 	bus_space_tag_t ctlt;
 	bus_space_handle_t ctlh;
+#endif
 	void	*fdc_intr;
 	struct	device *fdc_dev;
+#ifndef PC98
 	void	(*fdctl_wr)(struct fdc_data *fdc, u_int8_t v);
+#endif
 };
 
 /***********************************************************************\

sys/pc98/cbus/fdc.c

@@ -180,6 +180,10 @@ static struct fd_type fd_types[NUMTYPES] =
 #endif
 };
 
+#ifdef PC98
+static bus_addr_t fdc_iat[] = {0, 2, 4};
+#endif
+
 #ifdef PC98
 #define DRVS_PER_CTLR 4		/* 4 floppies */
 #else
@@ -272,13 +276,8 @@ static inline u_short
 nrd_info(addr)
 	nrd_t	addr;
 {
-	u_short	tmp;
-
 	nrd_addr(addr);
-	outb(0x43f, 0x42);
+	return (epson_inw(P_NRD_DATA));
-	tmp = (short)inw(P_NRD_DATA);
-	outb(0x43f, 0x40);
-	return ((u_short)tmp);
 }
 #endif /* EPSON_NRDISK */
 
@@ -342,11 +341,13 @@ static int volatile fd_debug = 0;
 #define TRACE1(arg1, arg2)
 #endif /* FDC_DEBUG */
 
+#ifndef PC98
 static void
 fdout_wr(fdc_p fdc, u_int8_t v)
 {
 	bus_space_write_1(fdc->portt, fdc->porth, FDOUT+fdc->port_off, v);
 }
+#endif
 
 static u_int8_t
 fdsts_rd(fdc_p fdc)
@@ -366,6 +367,14 @@ fddata_rd(fdc_p fdc)
 	return bus_space_read_1(fdc->portt, fdc->porth, FDDATA+fdc->port_off);
 }
 
+#ifdef PC98
+static void
+fdctl_wr(fdc_p fdc, u_int8_t v)
+{
+	bus_space_write_1(fdc->portt, fdc->porth, FDCTL, v);
+}
+#endif
+
 #ifndef PC98
 static void
 fdctl_wr_isa(fdc_p fdc, u_int8_t v)
@@ -635,9 +644,10 @@ static int pc98_trans_prev = 0;
 static void set_density(fdc_p fdc)
 {
 	/* always motor on */
-	outb(IO_FDPORT, (pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
+	bus_space_write_1(fdc->sc_fdsiot, fdc->sc_fdsioh, 0,
+			  (pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
 	DELAY(100);
-	fdout_wr(fdc, FDO_RST | FDO_DMAE);
+	fdctl_wr(fdc, FDC_RST | FDC_DMAE);
 	/* in the case of note W, always inhibit 100ms timer */
 }
 
@@ -661,7 +671,7 @@ static int pc98_fd_check_ready(fdu_t fdu)
 		DELAY(100);
 		fd_in(fdc, &status);
 		if ((status & NE7_ST3_RD)) {
-			fdout_wr(fdc, FDO_DMAE | FDO_MTON);
+			fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
 			DELAY(10);
 			return 0;
 		}
@@ -675,7 +685,9 @@ fdc_alloc_resources(struct fdc_data *fdc)
 {
 	device_t dev;
 	int ispnp, ispcmcia;
-
+#ifdef PC98
+	int rid;
+#endif
 	dev = fdc->fdc_dev;
 	ispnp = (fdc->flags & FDC_ISPNP) != 0;
 	ispcmcia = (fdc->flags & FDC_ISPCMCIA) != 0;
@@ -683,10 +695,9 @@ fdc_alloc_resources(struct fdc_data *fdc)
 	fdc->res_ioport = fdc->res_irq = fdc->res_drq = 0;
 
 #ifdef PC98
-	fdc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
+	fdc->res_ioport = isa_alloc_resourcev(dev, SYS_RES_IOPORT,
-					     &fdc->rid_ioport, 0ul, ~0ul, 
+					      &fdc->rid_ioport, fdc_iat,
-					     ispnp ? 1 : IO_FDCSIZE,
+					      3, RF_ACTIVE);
-					     RF_ACTIVE);
 #else
 	/*
 	 * On standard ISA, we don't just use an 8 port range
@@ -708,9 +719,32 @@ fdc_alloc_resources(struct fdc_data *fdc)
 		device_printf(dev, "cannot reserve I/O port range\n");
 		return ENXIO;
 	}
+#ifdef PC98
+	isa_load_resourcev(fdc->res_ioport, fdc_iat, 3);
+#endif
 	fdc->portt = rman_get_bustag(fdc->res_ioport);
 	fdc->porth = rman_get_bushandle(fdc->res_ioport);
 
+#ifdef PC98
+	rid = 3;
+	bus_set_resource(dev, SYS_RES_IOPORT, rid, IO_FDPORT, 1);
+	fdc->res_fdsio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
+					    1, RF_ACTIVE);
+	if (fdc->res_fdsio == 0)
+		return ENXIO;
+	fdc->sc_fdsiot = rman_get_bustag(fdc->res_fdsio);
+	fdc->sc_fdsioh = rman_get_bushandle(fdc->res_fdsio);
+
+	rid = 4;
+	bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x4be, 1);
+	fdc->res_fdemsio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
+					      1, RF_ACTIVE);
+	if (fdc->res_fdemsio == 0)
+		return ENXIO;
+	fdc->sc_fdemsiot = rman_get_bustag(fdc->res_fdemsio);
+	fdc->sc_fdemsioh = rman_get_bushandle(fdc->res_fdemsio);
+#endif
+
 #ifndef PC98
 	if (!ispcmcia) {
 		/*
@@ -803,6 +837,18 @@ fdc_release_resources(struct fdc_data *fdc)
 		bus_release_resource(dev, SYS_RES_IOPORT, fdc->rid_ctl,
 				     fdc->res_ctl);
 	}
+#endif
+#ifdef PC98
+	if (fdc->res_fdsio != 0) {
+		bus_deactivate_resource(dev, SYS_RES_IOPORT, 3,
+					fdc->res_fdsio);
+		bus_release_resource(dev, SYS_RES_IOPORT, 3, fdc->res_fdsio);
+	}
+	if (fdc->res_fdemsio != 0) {
+		bus_deactivate_resource(dev, SYS_RES_IOPORT, 4,
+					fdc->res_fdemsio);
+		bus_release_resource(dev, SYS_RES_IOPORT, 4, fdc->res_fdemsio);
+	}
 #endif
 	if (fdc->res_ioport != 0) {
 		bus_deactivate_resource(dev, SYS_RES_IOPORT, fdc->rid_ioport,
@@ -1371,8 +1417,10 @@ fd_probe(device_t dev)
 	case FDT_144M:
 		/* Check 3mode I/F */
 		fd->pc98_trans = 0;
-		outb(0x4be, (fd->fdu << 5) | 0x10);
+		bus_space_write_1(fdc->sc_fdemsiot, fdc->sc_fdemsioh, 0,
-		if (!(inb(0x4be) & 0x01)) {
+				  (fd->fdu << 5) | 0x10);
+		if (!(bus_space_read_1(fdc->sc_fdemsiot, fdc->sc_fdemsioh, 0) &
+		      0x01)) {
 			device_set_desc(dev, "1.44M FDD");
 			fd->type = FD_1440;
 			break;
@@ -1493,14 +1541,15 @@ DRIVER_MODULE(fd, fdc, fd_driver, fd_devclass, 0, 0);
 static void
 set_motor(struct fdc_data *fdc, int fdsu, int turnon)
 {
+#ifdef PC98
+	bus_space_write_1(fdc->sc_fdsiot, fdc->sc_fdsioh, 0,
+			  (pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
+	DELAY(10);
+	fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
+#else
 	int fdout = fdc->fdout;
 	int needspecify = 0;
 
-#ifdef PC98
-	outb(IO_FDPORT, (pc98_trans != 1 ? FDP_FDDEXC : 0)|FDP_PORTEXC);
-	DELAY(10);
-	fdout = FDO_DMAE|FDO_MTON;
-#else
 	if(turnon) {
 		fdout &= ~FDO_FDSEL;
 		fdout |= (FDO_MOEN0 << fdsu) + fdsu;
@@ -1517,7 +1566,6 @@ set_motor(struct fdc_data *fdc, int fdsu, int turnon)
 			needspecify = 1;
 		fdout |= (FDO_FRST|FDO_FDMAEN);
 	}
-#endif
 
 	fdout_wr(fdc, fdout);
 	fdc->fdout = fdout;
@@ -1544,6 +1592,7 @@ set_motor(struct fdc_data *fdc, int fdsu, int turnon)
 		if (fdc->flags & FDC_HAS_FIFO)
 			(void) enable_fifo(fdc);
 	}
+#endif
 }
 
 static void
@@ -1607,11 +1656,11 @@ fdc_reset(fdc_p fdc)
 #ifdef PC98
 	set_density(fdc);
 	if (pc98_machine_type & M_EPSON_PC98)
-		fdout_wr(fdc, 0xe8);
+		fdctl_wr(fdc, FDC_RST | FDC_RDY | FDC_DD | FDC_MTON);
 	else
-		fdout_wr(fdc, 0xd8);
+		fdctl_wr(fdc, FDC_RST | FDC_RDY | FDC_DMAE | FDC_MTON);
 	DELAY(200);
-	fdout_wr(fdc, 0x18);
+	fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
 	DELAY(10);
 #else
 	fdout_wr(fdc, fdc->fdout & ~(FDO_FRST|FDO_FDMAEN));
@@ -2074,7 +2123,11 @@ fdstate(fdc_p fdc)
 		}
 		if (pc98_trans != fd->pc98_trans) {
 			if (fd->type == FD_1440) {
-				outb(0x4be, (fdu << 5) | 0x10 | (pc98_trans >> 1));
+				bus_space_write_1(fdc->sc_fdemsiot,
+						  fdc->sc_fdemsioh,
+						  0,
+						  (fdu << 5) | 0x10 |
+						  (pc98_trans >> 1));
 				outb(0x5f, 0);
 				outb(0x5f, 0);
 			}

sys/pc98/cbus/fdcreg.h

@@ -44,24 +44,15 @@
 #ifdef PC98
 /* registers */
 #define	FDSTS	0	/* NEC 765 Main Status Register (R) */
-#define	FDDATA	2	/* NEC 765 Data Register (R/W) */
+#define	FDDATA	1	/* NEC 765 Data Register (R/W) */
-#define	FDOUT	4	/* Digital Output Register (W) */
+#define	FDCTL	2	/* FD Control Register */
-#define	FDO_RST		0x80	/*  FDC RESET */
+#define	FDC_RST		0x80	/*  FDC RESET */
-#define	FDO_FRY		0x40	/*  force READY */
+#define	FDC_RDY		0x40	/*  force READY */
-#define	FDO_AIE		0x20	/*  Attention Interrupt Enable */
+#define	FDC_DD		0x20	/*  FDD Mode Exchange 0:1M 1:640K */
-#define	FDO_DD		0x20	/*  FDD Mode Exchange 0:1M 1:640K */
+#define	FDC_DMAE	0x10	/*  enable floppy DMA */
-#define	FDO_DMAE	0x10	/*  enable floppy DMA */
+#define	FDC_MTON	0x08	/*  MOTOR ON (when EMTON=1)*/
-#define	FDO_MTON	0x08	/*  MOTOR ON (when EMTON=1)*/
+#define	FDC_TMSK	0x04	/*  TIMER MASK */
-#define	FDO_TMSK	0x04	/*  TIMER MASK */
+#define	FDC_TTRG	0x01	/*  TIMER TRIGER */
-#define	FDO_TTRG	0x01	/*  TIMER TRIGER */
-
-#define	FDIN	4	/* Digital Input Register (R) */
-#define	FDI_TYP0	0x04	/* FDD #1/#2 TYPE */
-#define	FDI_TYP1	0x08	/* FDD #3/#4 TYPE */
-#define	FDI_RDY		0x10	/* Ready */
-#define	FDI_DMACH	0x20	/* DMA Channel */
-#define	FDI_FINT0	0x40	/* Interrupt */
-#define	FDI_FINT1	0x80	/* Interrupt */
 
 #define	FDP_EMTON	0x04	/*  enable MTON */
 #define	FDP_FDDEXC	0x02	/*  FDD Mode Exchange 1:1M 0:640K */
@@ -81,6 +72,7 @@
 #define	FDSTS	4	/* NEC 765 Main Status Register (R) */
 #define	FDDATA	5	/* NEC 765 Data Register (R/W) */
 #define	FDCTL	7	/* Control Register (W) */
+#endif /* PC98 */
 
 #ifndef FDC_500KBPS
 #  define	FDC_500KBPS	0x00	/* 500KBPS MFM drive transfer rate */
@@ -89,7 +81,6 @@
 #  define	FDC_125KBPS	0x03	/* 125KBPS FM drive transfer rate */
 				/* for some controllers 1MPBS instead */
 #endif /* FDC_500KBPS */
-#endif /* PC98 */
 
 /*
  * this is the secret PIO data port (offset from base)

sys/pc98/pc98/fd.c

@@ -180,6 +180,10 @@ static struct fd_type fd_types[NUMTYPES] =
 #endif
 };
 
+#ifdef PC98
+static bus_addr_t fdc_iat[] = {0, 2, 4};
+#endif
+
 #ifdef PC98
 #define DRVS_PER_CTLR 4		/* 4 floppies */
 #else
@@ -272,13 +276,8 @@ static inline u_short
 nrd_info(addr)
 	nrd_t	addr;
 {
-	u_short	tmp;
-
 	nrd_addr(addr);
-	outb(0x43f, 0x42);
+	return (epson_inw(P_NRD_DATA));
-	tmp = (short)inw(P_NRD_DATA);
-	outb(0x43f, 0x40);
-	return ((u_short)tmp);
 }
 #endif /* EPSON_NRDISK */
 
@@ -342,11 +341,13 @@ static int volatile fd_debug = 0;
 #define TRACE1(arg1, arg2)
 #endif /* FDC_DEBUG */
 
+#ifndef PC98
 static void
 fdout_wr(fdc_p fdc, u_int8_t v)
 {
 	bus_space_write_1(fdc->portt, fdc->porth, FDOUT+fdc->port_off, v);
 }
+#endif
 
 static u_int8_t
 fdsts_rd(fdc_p fdc)
@@ -366,6 +367,14 @@ fddata_rd(fdc_p fdc)
 	return bus_space_read_1(fdc->portt, fdc->porth, FDDATA+fdc->port_off);
 }
 
+#ifdef PC98
+static void
+fdctl_wr(fdc_p fdc, u_int8_t v)
+{
+	bus_space_write_1(fdc->portt, fdc->porth, FDCTL, v);
+}
+#endif
+
 #ifndef PC98
 static void
 fdctl_wr_isa(fdc_p fdc, u_int8_t v)
@@ -635,9 +644,10 @@ static int pc98_trans_prev = 0;
 static void set_density(fdc_p fdc)
 {
 	/* always motor on */
-	outb(IO_FDPORT, (pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
+	bus_space_write_1(fdc->sc_fdsiot, fdc->sc_fdsioh, 0,
+			  (pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
 	DELAY(100);
-	fdout_wr(fdc, FDO_RST | FDO_DMAE);
+	fdctl_wr(fdc, FDC_RST | FDC_DMAE);
 	/* in the case of note W, always inhibit 100ms timer */
 }
 
@@ -661,7 +671,7 @@ static int pc98_fd_check_ready(fdu_t fdu)
 		DELAY(100);
 		fd_in(fdc, &status);
 		if ((status & NE7_ST3_RD)) {
-			fdout_wr(fdc, FDO_DMAE | FDO_MTON);
+			fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
 			DELAY(10);
 			return 0;
 		}
@@ -675,7 +685,9 @@ fdc_alloc_resources(struct fdc_data *fdc)
 {
 	device_t dev;
 	int ispnp, ispcmcia;
-
+#ifdef PC98
+	int rid;
+#endif
 	dev = fdc->fdc_dev;
 	ispnp = (fdc->flags & FDC_ISPNP) != 0;
 	ispcmcia = (fdc->flags & FDC_ISPCMCIA) != 0;
@@ -683,10 +695,9 @@ fdc_alloc_resources(struct fdc_data *fdc)
 	fdc->res_ioport = fdc->res_irq = fdc->res_drq = 0;
 
 #ifdef PC98
-	fdc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
+	fdc->res_ioport = isa_alloc_resourcev(dev, SYS_RES_IOPORT,
-					     &fdc->rid_ioport, 0ul, ~0ul, 
+					      &fdc->rid_ioport, fdc_iat,
-					     ispnp ? 1 : IO_FDCSIZE,
+					      3, RF_ACTIVE);
-					     RF_ACTIVE);
 #else
 	/*
 	 * On standard ISA, we don't just use an 8 port range
@@ -708,9 +719,32 @@ fdc_alloc_resources(struct fdc_data *fdc)
 		device_printf(dev, "cannot reserve I/O port range\n");
 		return ENXIO;
 	}
+#ifdef PC98
+	isa_load_resourcev(fdc->res_ioport, fdc_iat, 3);
+#endif
 	fdc->portt = rman_get_bustag(fdc->res_ioport);
 	fdc->porth = rman_get_bushandle(fdc->res_ioport);
 
+#ifdef PC98
+	rid = 3;
+	bus_set_resource(dev, SYS_RES_IOPORT, rid, IO_FDPORT, 1);
+	fdc->res_fdsio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
+					    1, RF_ACTIVE);
+	if (fdc->res_fdsio == 0)
+		return ENXIO;
+	fdc->sc_fdsiot = rman_get_bustag(fdc->res_fdsio);
+	fdc->sc_fdsioh = rman_get_bushandle(fdc->res_fdsio);
+
+	rid = 4;
+	bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x4be, 1);
+	fdc->res_fdemsio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
+					      1, RF_ACTIVE);
+	if (fdc->res_fdemsio == 0)
+		return ENXIO;
+	fdc->sc_fdemsiot = rman_get_bustag(fdc->res_fdemsio);
+	fdc->sc_fdemsioh = rman_get_bushandle(fdc->res_fdemsio);
+#endif
+
 #ifndef PC98
 	if (!ispcmcia) {
 		/*
@@ -803,6 +837,18 @@ fdc_release_resources(struct fdc_data *fdc)
 		bus_release_resource(dev, SYS_RES_IOPORT, fdc->rid_ctl,
 				     fdc->res_ctl);
 	}
+#endif
+#ifdef PC98
+	if (fdc->res_fdsio != 0) {
+		bus_deactivate_resource(dev, SYS_RES_IOPORT, 3,
+					fdc->res_fdsio);
+		bus_release_resource(dev, SYS_RES_IOPORT, 3, fdc->res_fdsio);
+	}
+	if (fdc->res_fdemsio != 0) {
+		bus_deactivate_resource(dev, SYS_RES_IOPORT, 4,
+					fdc->res_fdemsio);
+		bus_release_resource(dev, SYS_RES_IOPORT, 4, fdc->res_fdemsio);
+	}
 #endif
 	if (fdc->res_ioport != 0) {
 		bus_deactivate_resource(dev, SYS_RES_IOPORT, fdc->rid_ioport,
@@ -1371,8 +1417,10 @@ fd_probe(device_t dev)
 	case FDT_144M:
 		/* Check 3mode I/F */
 		fd->pc98_trans = 0;
-		outb(0x4be, (fd->fdu << 5) | 0x10);
+		bus_space_write_1(fdc->sc_fdemsiot, fdc->sc_fdemsioh, 0,
-		if (!(inb(0x4be) & 0x01)) {
+				  (fd->fdu << 5) | 0x10);
+		if (!(bus_space_read_1(fdc->sc_fdemsiot, fdc->sc_fdemsioh, 0) &
+		      0x01)) {
 			device_set_desc(dev, "1.44M FDD");
 			fd->type = FD_1440;
 			break;
@@ -1493,14 +1541,15 @@ DRIVER_MODULE(fd, fdc, fd_driver, fd_devclass, 0, 0);
 static void
 set_motor(struct fdc_data *fdc, int fdsu, int turnon)
 {
+#ifdef PC98
+	bus_space_write_1(fdc->sc_fdsiot, fdc->sc_fdsioh, 0,
+			  (pc98_trans != 1 ? FDP_FDDEXC : 0) | FDP_PORTEXC);
+	DELAY(10);
+	fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
+#else
 	int fdout = fdc->fdout;
 	int needspecify = 0;
 
-#ifdef PC98
-	outb(IO_FDPORT, (pc98_trans != 1 ? FDP_FDDEXC : 0)|FDP_PORTEXC);
-	DELAY(10);
-	fdout = FDO_DMAE|FDO_MTON;
-#else
 	if(turnon) {
 		fdout &= ~FDO_FDSEL;
 		fdout |= (FDO_MOEN0 << fdsu) + fdsu;
@@ -1517,7 +1566,6 @@ set_motor(struct fdc_data *fdc, int fdsu, int turnon)
 			needspecify = 1;
 		fdout |= (FDO_FRST|FDO_FDMAEN);
 	}
-#endif
 
 	fdout_wr(fdc, fdout);
 	fdc->fdout = fdout;
@@ -1544,6 +1592,7 @@ set_motor(struct fdc_data *fdc, int fdsu, int turnon)
 		if (fdc->flags & FDC_HAS_FIFO)
 			(void) enable_fifo(fdc);
 	}
+#endif
 }
 
 static void
@@ -1607,11 +1656,11 @@ fdc_reset(fdc_p fdc)
 #ifdef PC98
 	set_density(fdc);
 	if (pc98_machine_type & M_EPSON_PC98)
-		fdout_wr(fdc, 0xe8);
+		fdctl_wr(fdc, FDC_RST | FDC_RDY | FDC_DD | FDC_MTON);
 	else
-		fdout_wr(fdc, 0xd8);
+		fdctl_wr(fdc, FDC_RST | FDC_RDY | FDC_DMAE | FDC_MTON);
 	DELAY(200);
-	fdout_wr(fdc, 0x18);
+	fdctl_wr(fdc, FDC_DMAE | FDC_MTON);
 	DELAY(10);
 #else
 	fdout_wr(fdc, fdc->fdout & ~(FDO_FRST|FDO_FDMAEN));
@@ -2074,7 +2123,11 @@ fdstate(fdc_p fdc)
 		}
 		if (pc98_trans != fd->pc98_trans) {
 			if (fd->type == FD_1440) {
-				outb(0x4be, (fdu << 5) | 0x10 | (pc98_trans >> 1));
+				bus_space_write_1(fdc->sc_fdemsiot,
+						  fdc->sc_fdemsioh,
+						  0,
+						  (fdu << 5) | 0x10 |
+						  (pc98_trans >> 1));
 				outb(0x5f, 0);
 				outb(0x5f, 0);
 			}

sys/pc98/pc98/fdreg.h

@@ -44,24 +44,15 @@
 #ifdef PC98
 /* registers */
 #define	FDSTS	0	/* NEC 765 Main Status Register (R) */
-#define	FDDATA	2	/* NEC 765 Data Register (R/W) */
+#define	FDDATA	1	/* NEC 765 Data Register (R/W) */
-#define	FDOUT	4	/* Digital Output Register (W) */
+#define	FDCTL	2	/* FD Control Register */
-#define	FDO_RST		0x80	/*  FDC RESET */
+#define	FDC_RST		0x80	/*  FDC RESET */
-#define	FDO_FRY		0x40	/*  force READY */
+#define	FDC_RDY		0x40	/*  force READY */
-#define	FDO_AIE		0x20	/*  Attention Interrupt Enable */
+#define	FDC_DD		0x20	/*  FDD Mode Exchange 0:1M 1:640K */
-#define	FDO_DD		0x20	/*  FDD Mode Exchange 0:1M 1:640K */
+#define	FDC_DMAE	0x10	/*  enable floppy DMA */
-#define	FDO_DMAE	0x10	/*  enable floppy DMA */
+#define	FDC_MTON	0x08	/*  MOTOR ON (when EMTON=1)*/
-#define	FDO_MTON	0x08	/*  MOTOR ON (when EMTON=1)*/
+#define	FDC_TMSK	0x04	/*  TIMER MASK */
-#define	FDO_TMSK	0x04	/*  TIMER MASK */
+#define	FDC_TTRG	0x01	/*  TIMER TRIGER */
-#define	FDO_TTRG	0x01	/*  TIMER TRIGER */
-
-#define	FDIN	4	/* Digital Input Register (R) */
-#define	FDI_TYP0	0x04	/* FDD #1/#2 TYPE */
-#define	FDI_TYP1	0x08	/* FDD #3/#4 TYPE */
-#define	FDI_RDY		0x10	/* Ready */
-#define	FDI_DMACH	0x20	/* DMA Channel */
-#define	FDI_FINT0	0x40	/* Interrupt */
-#define	FDI_FINT1	0x80	/* Interrupt */
 
 #define	FDP_EMTON	0x04	/*  enable MTON */
 #define	FDP_FDDEXC	0x02	/*  FDD Mode Exchange 1:1M 0:640K */
@@ -81,6 +72,7 @@
 #define	FDSTS	4	/* NEC 765 Main Status Register (R) */
 #define	FDDATA	5	/* NEC 765 Data Register (R/W) */
 #define	FDCTL	7	/* Control Register (W) */
+#endif /* PC98 */
 
 #ifndef FDC_500KBPS
 #  define	FDC_500KBPS	0x00	/* 500KBPS MFM drive transfer rate */
@@ -89,7 +81,6 @@
 #  define	FDC_125KBPS	0x03	/* 125KBPS FM drive transfer rate */
 				/* for some controllers 1MPBS instead */
 #endif /* FDC_500KBPS */
-#endif /* PC98 */
 
 /*
  * this is the secret PIO data port (offset from base)