Fix up support for the AR8327.
* Even though I got the registers around "right", it seems I'm not tickling the MDIO access correctly for the internal PHY bus. Some of the switches are fine poking at the external PHY registers; others aren't. So, enable direct PHY bus access for the AR8327, and leave the existing code in place for the others. * Go and shuffle the register access around. Whilst here, restore the 2ms delay if changing page. * Comment out some of the stub printf()s; there's some upcoming work to add port VLAN support. Tested: * AP135 development board * Carambola2 - AR9331 SoC
This commit is contained in:
Adrian Chadd
parent
d3df8026cf
commit
78549b94cd
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=279767
@ -149,8 +149,10 @@ arswitch_probe(device_t dev)
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DPRINTF(dev, "chipname=%s, id=%08x\n", chipname, id);
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if (chipname != NULL) {
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snprintf(desc, sizeof(desc),
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"Atheros %s Ethernet Switch",
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chipname);
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"Atheros %s Ethernet Switch (ver %d rev %d)",
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chipname,
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sc->chip_ver,
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sc->chip_rev);
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device_set_desc_copy(dev, desc);
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return (BUS_PROBE_DEFAULT);
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}
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@ -177,9 +179,11 @@ arswitch_attach_phys(struct arswitch_softc *sc)
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err = mii_attach(sc->sc_dev, &sc->miibus[phy], sc->ifp[phy],
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arswitch_ifmedia_upd, arswitch_ifmedia_sts, \
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BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
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#if 0
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DPRINTF(sc->sc_dev, "%s attached to pseudo interface %s\n",
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device_get_nameunit(sc->miibus[phy]),
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sc->ifp[phy]->if_xname);
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#endif
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if (err != 0) {
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device_printf(sc->sc_dev,
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"attaching PHY %d failed\n",
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@ -304,6 +308,8 @@ arswitch_attach(device_t dev)
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sc->hal.arswitch_vlan_get_pvid = ar8xxx_get_pvid;
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sc->hal.arswitch_vlan_set_pvid = ar8xxx_set_pvid;
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sc->hal.arswitch_atu_flush = ar8xxx_atu_flush;
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sc->hal.arswitch_phy_read = arswitch_readphy_internal;
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sc->hal.arswitch_phy_write = arswitch_writephy_internal;
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/*
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* Attach switch related functions
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@ -320,8 +326,10 @@ arswitch_attach(device_t dev)
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ar8316_attach(sc);
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else if (AR8X16_IS_SWITCH(sc, AR8327))
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ar8327_attach(sc);
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else
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else {
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DPRINTF(dev, "%s: unknown switch (%d)?\n", __func__, sc->sc_switchtype);
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return (ENXIO);
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}
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/* Common defaults. */
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sc->info.es_nports = 5; /* XXX technically 6, but 6th not used */
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@ -348,14 +356,18 @@ arswitch_attach(device_t dev)
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sc->numphys = AR8X16_NUM_PHYS;
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/* Reset the switch. */
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if (arswitch_reset(dev))
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if (arswitch_reset(dev)) {
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DPRINTF(dev, "%s: arswitch_reset: failed\n", __func__);
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return (ENXIO);
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}
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err = sc->hal.arswitch_hw_setup(sc);
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DPRINTF(dev, "%s: hw_setup: err=%d\n", __func__, err);
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if (err != 0)
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return (err);
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err = sc->hal.arswitch_hw_global_setup(sc);
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DPRINTF(dev, "%s: hw_global_setup: err=%d\n", __func__, err);
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if (err != 0)
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return (err);
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@ -368,17 +380,20 @@ arswitch_attach(device_t dev)
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* Attach the PHYs and complete the bus enumeration.
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*/
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err = arswitch_attach_phys(sc);
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DPRINTF(dev, "%s: attach_phys: err=%d\n", __func__, err);
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if (err != 0)
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return (err);
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/* Default to ingress filters off. */
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err = arswitch_set_vlan_mode(sc, 0);
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DPRINTF(dev, "%s: set_vlan_mode: err=%d\n", __func__, err);
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if (err != 0)
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return (err);
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bus_generic_probe(dev);
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bus_enumerate_hinted_children(dev);
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err = bus_generic_attach(dev);
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DPRINTF(dev, "%s: bus_generic_attach: err=%d\n", __func__, err);
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if (err != 0)
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return (err);
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@ -803,6 +818,22 @@ arswitch_setvgroup(device_t dev, etherswitch_vlangroup_t *e)
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return (sc->hal.arswitch_vlan_setvgroup(sc, e));
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}
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static int
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arswitch_readphy(device_t dev, int phy, int reg)
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{
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struct arswitch_softc *sc = device_get_softc(dev);
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return (sc->hal.arswitch_phy_read(dev, phy, reg));
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}
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static int
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arswitch_writephy(device_t dev, int phy, int reg, int val)
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{
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struct arswitch_softc *sc = device_get_softc(dev);
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return (sc->hal.arswitch_phy_write(dev, phy, reg, val));
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}
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static device_method_t arswitch_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, arswitch_probe),
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@ -57,6 +57,9 @@
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#include <dev/etherswitch/arswitch/arswitchreg.h>
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#include <dev/etherswitch/arswitch/arswitchvar.h>
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#include <dev/etherswitch/arswitch/arswitch_reg.h>
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#include <dev/etherswitch/arswitch/arswitch_phy.h>
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#include <dev/etherswitch/arswitch/arswitch_vlans.h>
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#include <dev/etherswitch/arswitch/arswitch_8327.h>
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#include "mdio_if.h"
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@ -290,7 +293,7 @@ ar8327_fetch_pdata_port(struct arswitch_softc *sc,
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sbuf, &val) == 0)
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pcfg->rxpause = val;
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#if 0
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#if 1
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device_printf(sc->sc_dev,
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"%s: port %d: speed=%d, duplex=%d, txpause=%d, rxpause=%d\n",
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__func__,
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@ -562,6 +565,7 @@ ar8327_init_pdata(struct arswitch_softc *sc)
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/* SGMII config */
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bzero(&scfg, sizeof(scfg));
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if (ar8327_fetch_pdata_sgmii(sc, &scfg)) {
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device_printf(sc->sc_dev, "%s: SGMII cfg?\n", __func__);
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t = scfg.sgmii_ctrl;
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if (sc->chip_rev == 1)
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t |= AR8327_SGMII_CTRL_EN_PLL |
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@ -657,12 +661,16 @@ ar8327_hw_global_setup(struct arswitch_softc *sc)
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}
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/*
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* Port setup.
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* Port setup. Called at attach time.
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*/
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static void
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ar8327_port_init(struct arswitch_softc *sc, int port)
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{
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uint32_t t;
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int ports;
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/* For now, port can see all other ports */
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ports = 0x7f;
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if (port == AR8X16_PORT_CPU)
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t = sc->ar8327.port0_status;
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@ -696,7 +704,7 @@ ar8327_port_init(struct arswitch_softc *sc, int port)
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t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
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/* So this allows traffic to any port except ourselves */
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t |= (0x7f & ~(1 << port));
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t |= (ports & ~(1 << port));
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arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), t);
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}
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@ -705,16 +713,18 @@ ar8327_port_vlan_setup(struct arswitch_softc *sc, etherswitch_port_t *p)
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{
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/* XXX stub for now */
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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// device_printf(sc->sc_dev, "%s: called\n", __func__);
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return (0);
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}
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/*
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* Get the port VLAN configuration.
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*/
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static int
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ar8327_port_vlan_get(struct arswitch_softc *sc, etherswitch_port_t *p)
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{
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/* XXX stub for now */
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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// device_printf(sc->sc_dev, "%s: called\n", __func__);
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return (0);
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}
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@ -723,6 +733,13 @@ ar8327_reset_vlans(struct arswitch_softc *sc)
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{
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int i;
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uint32_t mode, t;
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int ports;
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ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
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ARSWITCH_LOCK(sc);
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/* Clear the existing VLAN configuration */
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memset(sc->vid, 0, sizeof(sc->vid));
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/*
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* Disable mirroring.
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@ -732,10 +749,21 @@ ar8327_reset_vlans(struct arswitch_softc *sc)
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(0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
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/*
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* For now, let's default to one portgroup, just so traffic
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* flows. All ports can see other ports.
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* XXX TODO: disable any Q-in-Q port configuration,
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* tagging, egress filters, etc.
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*/
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/*
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* For now, let's default to one portgroup, just so traffic
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* flows. All ports can see other ports. There are two CPU GMACs
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* (GMAC0, GMAC6), GMAC1..GMAC5 are external PHYs.
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*
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* (ETHERSWITCH_VLAN_PORT)
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*/
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ports = 0x7f;
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for (i = 0; i < AR8327_NUM_PORTS; i++) {
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/* set pvid = 1; there's only one vlangroup */
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t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
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t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
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@ -749,7 +777,7 @@ ar8327_reset_vlans(struct arswitch_softc *sc)
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arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(i), t);
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/* Ports can see other ports */
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t = (0x7f & ~(1 << i)); /* all ports besides us */
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t = (ports & ~(1 << i)); /* all ports besides us */
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t |= AR8327_PORT_LOOKUP_LEARN;
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/* in_port_only, forward */
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@ -769,12 +797,20 @@ ar8327_reset_vlans(struct arswitch_softc *sc)
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AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
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0);
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}
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ARSWITCH_UNLOCK(sc);
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}
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static int
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ar8327_vlan_getvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
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{
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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#if 0
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/* XXX for now, no dot1q vlans */
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if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q)
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return (EINVAL);
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return (ar8xxx_getvgroup(sc, vg));
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#endif
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return (0);
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}
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@ -782,7 +818,12 @@ static int
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ar8327_vlan_setvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
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{
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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#if 0
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/* XXX for now, no dot1q vlans */
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if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q)
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return (EINVAL);
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return (ar8xxx_setvgroup(sc, vg));
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#endif
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return (0);
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}
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@ -832,17 +873,29 @@ ar8327_attach(struct arswitch_softc *sc)
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sc->hal.arswitch_hw_global_setup = ar8327_hw_global_setup;
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sc->hal.arswitch_port_init = ar8327_port_init;
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sc->hal.arswitch_vlan_getvgroup = ar8327_vlan_getvgroup;
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sc->hal.arswitch_vlan_setvgroup = ar8327_vlan_setvgroup;
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sc->hal.arswitch_port_vlan_setup = ar8327_port_vlan_setup;
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sc->hal.arswitch_port_vlan_get = ar8327_port_vlan_get;
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sc->hal.arswitch_vlan_init_hw = ar8327_reset_vlans;
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sc->hal.arswitch_vlan_getvgroup = ar8327_vlan_getvgroup;
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sc->hal.arswitch_vlan_setvgroup = ar8327_vlan_setvgroup;
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sc->hal.arswitch_vlan_get_pvid = ar8327_get_pvid;
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sc->hal.arswitch_vlan_set_pvid = ar8327_set_pvid;
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sc->hal.arswitch_atu_flush = ar8327_atu_flush;
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/*
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* Reading the PHY via the MDIO interface currently doesn't
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* work correctly.
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*
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* So for now, just go direct to the PHY registers themselves.
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* This has always worked on external devices, but not internal
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* devices (AR934x, AR724x, AR933x.)
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*/
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sc->hal.arswitch_phy_read = arswitch_readphy_external;
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sc->hal.arswitch_phy_write = arswitch_writephy_external;
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/* Set the switch vlan capabilities. */
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sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q |
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ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOUBLE_TAG;
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@ -67,11 +67,46 @@ static SYSCTL_NODE(_debug, OID_AUTO, arswitch, CTLFLAG_RD, 0, "arswitch");
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#endif
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/*
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* access PHYs integrated into the switch chip through the switch's MDIO
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* Access PHYs integrated into the switch by going direct
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* to the PHY space itself, rather than through the switch
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* MDIO register.
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*/
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int
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arswitch_readphy_external(device_t dev, int phy, int reg)
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{
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int ret;
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struct arswitch_softc *sc;
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sc = device_get_softc(dev);
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ARSWITCH_LOCK(sc);
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ret = (MDIO_READREG(device_get_parent(dev), phy, reg));
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ARSWITCH_UNLOCK(sc);
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return (ret);
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}
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int
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arswitch_writephy_external(device_t dev, int phy, int reg, int data)
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{
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struct arswitch_softc *sc;
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sc = device_get_softc(dev);
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ARSWITCH_LOCK(sc);
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(void) MDIO_WRITEREG(device_get_parent(dev), phy,
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reg, data);
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ARSWITCH_UNLOCK(sc);
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return (0);
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}
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/*
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* Access PHYs integrated into the switch chip through the switch's MDIO
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* control register.
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*/
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int
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arswitch_readphy(device_t dev, int phy, int reg)
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arswitch_readphy_internal(device_t dev, int phy, int reg)
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{
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struct arswitch_softc *sc;
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uint32_t data = 0, ctrl;
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@ -105,8 +140,10 @@ arswitch_readphy(device_t dev, int phy, int reg)
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if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
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break;
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}
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if (timeout < 0)
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if (timeout < 0) {
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DPRINTF(dev, "arswitch_readphy(): phy=%d.%02x; timeout=%d\n", phy, reg, timeout);
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goto fail;
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}
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data = arswitch_readreg_lsb(dev, a) &
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AR8X16_MDIO_CTRL_DATA_MASK;
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ARSWITCH_UNLOCK(sc);
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@ -118,7 +155,7 @@ arswitch_readphy(device_t dev, int phy, int reg)
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}
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int
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arswitch_writephy(device_t dev, int phy, int reg, int data)
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arswitch_writephy_internal(device_t dev, int phy, int reg, int data)
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{
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struct arswitch_softc *sc;
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uint32_t ctrl;
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@ -28,7 +28,10 @@
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#ifndef __ARSWITCH_PHY_H__
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#define __ARSWITCH_PHY_H__
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extern int arswitch_readphy(device_t dev, int phy, int reg);
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extern int arswitch_writephy(device_t dev, int phy, int reg, int data);
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extern int arswitch_readphy_external(device_t dev, int phy, int reg);
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extern int arswitch_writephy_external(device_t dev, int phy, int reg, int data);
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extern int arswitch_readphy_internal(device_t dev, int phy, int reg);
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extern int arswitch_writephy_internal(device_t dev, int phy, int reg, int data);
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#endif /* __ARSWITCH_PHY_H__ */
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@ -68,12 +68,13 @@ arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy,
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struct arswitch_softc *sc = device_get_softc(dev);
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uint16_t page;
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page = ((addr) >> 9) & 0xffff;
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*phy = (((addr) >> 6) & 0x07) | 0x10;
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*reg = ((addr) >> 1) & 0x1f;
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page = (addr >> 9) & 0x1ff;
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*phy = (addr >> 6) & 0x7;
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*reg = (addr >> 1) & 0x1f;
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if (sc->page != page) {
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MDIO_WRITEREG(device_get_parent(dev), 0x18, 0, page);
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DELAY(2000);
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sc->page = page;
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}
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}
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@ -87,9 +88,21 @@ static inline int
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arswitch_readreg16(device_t dev, int addr)
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{
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uint16_t phy, reg;
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arswitch_split_setpage(dev, addr, &phy, ®);
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return (MDIO_READREG(device_get_parent(dev), phy, reg));
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return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg));
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}
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/*
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* Write half a register. See above!
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*/
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static inline int
|
||||
arswitch_writereg16(device_t dev, int addr, int data)
|
||||
{
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data));
|
||||
}
|
||||
|
||||
/*
|
||||
@ -121,18 +134,70 @@ arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr,
|
||||
MII_ATH_MMD_DATA, dbg_data);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write half a register
|
||||
*/
|
||||
static inline int
|
||||
arswitch_writereg16(device_t dev, int addr, int data)
|
||||
static uint32_t
|
||||
arswitch_reg_read32(device_t dev, int phy, int reg)
|
||||
{
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
return (MDIO_WRITEREG(device_get_parent(dev), phy, reg, data));
|
||||
uint16_t lo, hi;
|
||||
lo = MDIO_READREG(device_get_parent(dev), phy, reg);
|
||||
hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1);
|
||||
|
||||
return (hi << 16) | lo;
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value)
|
||||
{
|
||||
struct arswitch_softc *sc;
|
||||
int r;
|
||||
uint16_t lo, hi;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
lo = value & 0xffff;
|
||||
hi = (uint16_t) (value >> 16);
|
||||
|
||||
if (sc->mii_lo_first) {
|
||||
r = MDIO_WRITEREG(device_get_parent(dev),
|
||||
phy, reg, lo);
|
||||
r |= MDIO_WRITEREG(device_get_parent(dev),
|
||||
phy, reg + 1, hi);
|
||||
} else {
|
||||
r = MDIO_WRITEREG(device_get_parent(dev),
|
||||
phy, reg + 1, hi);
|
||||
r |= MDIO_WRITEREG(device_get_parent(dev),
|
||||
phy, reg, lo);
|
||||
}
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_readreg(device_t dev, int addr)
|
||||
{
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
return arswitch_reg_read32(dev, 0x10 | phy, reg);
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_writereg(device_t dev, int addr, int value)
|
||||
{
|
||||
struct arswitch_softc *sc;
|
||||
uint16_t phy, reg;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));
|
||||
}
|
||||
|
||||
/*
|
||||
* Read/write 16 bit values in the switch register space.
|
||||
*
|
||||
* Some of the registers are control registers (eg the MDIO
|
||||
* data versus control space) and so need to be treated
|
||||
* differently.
|
||||
*/
|
||||
int
|
||||
arswitch_readreg_lsb(device_t dev, int addr)
|
||||
{
|
||||
@ -161,53 +226,31 @@ arswitch_writereg_msb(device_t dev, int addr, int data)
|
||||
return (arswitch_writereg16(dev, addr + 2, (data >> 16) & 0xffff));
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_readreg(device_t dev, int addr)
|
||||
{
|
||||
|
||||
return (arswitch_readreg_lsb(dev, addr) |
|
||||
arswitch_readreg_msb(dev, addr));
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_writereg(device_t dev, int addr, int value)
|
||||
{
|
||||
struct arswitch_softc *sc;
|
||||
int r;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
/* XXX Check the first write too? */
|
||||
if (sc->mii_lo_first) {
|
||||
r = arswitch_writereg_lsb(dev, addr, value);
|
||||
r |= arswitch_writereg_msb(dev, addr, value);
|
||||
} else {
|
||||
r = arswitch_writereg_msb(dev, addr, value);
|
||||
r |= arswitch_writereg_lsb(dev, addr, value);
|
||||
}
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_modifyreg(device_t dev, int addr, int mask, int set)
|
||||
{
|
||||
int value;
|
||||
|
||||
value = arswitch_readreg(dev, addr);
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
|
||||
value = arswitch_reg_read32(dev, 0x10 | phy, reg);
|
||||
value &= ~mask;
|
||||
value |= set;
|
||||
return (arswitch_writereg(dev, addr, value));
|
||||
return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_waitreg(device_t dev, int addr, int mask, int val, int timeout)
|
||||
{
|
||||
int err, v;
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
|
||||
err = -1;
|
||||
while (1) {
|
||||
v = arswitch_readreg(dev, addr);
|
||||
v = arswitch_reg_read32(dev, 0x10 | phy, reg);
|
||||
v &= mask;
|
||||
if (v == val) {
|
||||
err = 0;
|
||||
|
||||
@ -60,7 +60,7 @@ struct arswitch_softc {
|
||||
int is_internal_switch;
|
||||
int chip_ver;
|
||||
int chip_rev;
|
||||
int mii_lo_first;
|
||||
int mii_lo_first; /* Send low data DWORD before high */
|
||||
ar8x16_switch_type sc_switchtype;
|
||||
/* should be the max of both pre-AR8327 and AR8327 ports */
|
||||
char *ifname[ARSWITCH_NUM_PHYS];
|
||||
@ -98,6 +98,10 @@ struct arswitch_softc {
|
||||
int *);
|
||||
int (* arswitch_vlan_set_pvid) (struct arswitch_softc *, int,
|
||||
int);
|
||||
|
||||
/* PHY functions */
|
||||
int (* arswitch_phy_read) (device_t, int, int);
|
||||
int (* arswitch_phy_write) (device_t, int, int, int);
|
||||
} hal;
|
||||
|
||||
struct {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user