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Spell "Hz" correctly wherever it is user-visible.

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PR:		bin/142566
Submitted by:	N.J. Mann   njm njm.me.uk
Approved by:	ed (mentor)
MFC after:	2 weeks
This commit is contained in:
Gavin Atkinson 2010-01-12 17:59:58 +00:00
parent 329fe20011
commit 7964930201
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=202161
12 changed files with 21 additions and 21 deletions
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10
sbin/ifconfig/ifieee80211.c
View File

@ -3429,9 +3429,9 @@ get_chaninfo(const struct ieee80211_channel *c, int precise,
else if (IEEE80211_IS_CHAN_B(c))
strlcat(buf, " 11b", bsize);
if (IEEE80211_IS_CHAN_HALF(c))
strlcat(buf, "/10Mhz", bsize);
strlcat(buf, "/10MHz", bsize);
if (IEEE80211_IS_CHAN_QUARTER(c))
strlcat(buf, "/5Mhz", bsize);
strlcat(buf, "/5MHz", bsize);
if (IEEE80211_IS_CHAN_TURBO(c))
strlcat(buf, " Turbo", bsize);
if (precise) {
@ -3453,7 +3453,7 @@ print_chaninfo(const struct ieee80211_channel *c, int verb)
{
char buf[14];
printf("Channel %3u : %u%c Mhz%-14.14s",
printf("Channel %3u : %u%c MHz%-14.14s",
ieee80211_mhz2ieee(c->ic_freq, c->ic_flags), c->ic_freq,
IEEE80211_IS_CHAN_PASSIVE(c) ? '*' : ' ',
get_chaninfo(c, verb, buf, sizeof(buf)));
@ -3562,7 +3562,7 @@ list_channels(int s, int allchans)
static void
print_txpow(const struct ieee80211_channel *c)
{
printf("Channel %3u : %u Mhz %3.1f reg %2d ",
printf("Channel %3u : %u MHz %3.1f reg %2d ",
c->ic_ieee, c->ic_freq,
c->ic_maxpower/2., c->ic_maxregpower);
}
@ -4244,7 +4244,7 @@ ieee80211_status(int s)
c = getcurchan(s);
if (c->ic_freq != IEEE80211_CHAN_ANY) {
char buf[14];
printf(" channel %d (%u Mhz%s)", c->ic_ieee, c->ic_freq,
printf(" channel %d (%u MHz%s)", c->ic_ieee, c->ic_freq,
get_chaninfo(c, 1, buf, sizeof(buf)));
} else if (verbose)
printf(" channel UNDEF");

2
share/man/man4/ath.4
View File

@ -249,7 +249,7 @@ This should not happen.
An invalid transmit rate was specified for an outgoing frame.
The frame is discarded.
This should not happen.
.It "ath%d: ath_chan_set: unable to reset channel %u (%u Mhz)"
.It "ath%d: ath_chan_set: unable to reset channel %u (%u MHz)"
The Atheros Hardware Access Layer was unable to reset the hardware
when switching channels during scanning.
This should not happen.

2
share/man/man4/cpufreq.4
View File

@ -234,7 +234,7 @@ The driver should set unknown or irrelevant values to
All the following elements for each setting should be returned:
.Bd -literal
struct cf_setting {
int freq; /* CPU clock in Mhz or 100ths of a percent. */
int freq; /* CPU clock in MHz or 100ths of a percent. */
int volts; /* Voltage in mV. */
int power; /* Power consumed in mW. */
int lat; /* Transition latency in us. */

2
share/man/man4/vge.4
View File

@ -58,7 +58,7 @@ driver provides support for various NICs and embedded Ethernet interfaces
based on the VIA Technologies VT6120, VT6122, VT6130 and VT6132 Velocity
Family Gigabit Ethernet controller chips.
.Pp
The VT6120/VT6122 is a 33/66Mhz 64-bit PCI device which combines a tri-speed
The VT6120/VT6122 is a 33/66MHz 64-bit PCI device which combines a tri-speed
MAC with an integrated 10/100/1000 copper PHY.
(Some older cards use an external PHY.)
The VT6130/VT6132 is the PCI express version of Velocity family.

2
sys/amd64/amd64/local_apic.c
View File

@ -448,7 +448,7 @@ lapic_setup_clock(void)
panic("lapic: Divisor too big");
value /= 2;
if (bootverbose)
printf("lapic: Divisor %lu, Frequency %lu hz\n",
printf("lapic: Divisor %lu, Frequency %lu Hz\n",
lapic_timer_divisor, value);
/*

8
sys/dev/aic7xxx/aic79xx_pci.c
View File

@ -248,10 +248,10 @@ static const char *pci_bus_modes[] =
"PCI bus mode unknown",
"PCI bus mode unknown",
"PCI bus mode unknown",
"PCI-X 101-133Mhz",
"PCI-X 67-100Mhz",
"PCI-X 50-66Mhz",
"PCI 33 or 66Mhz"
"PCI-X 101-133MHz",
"PCI-X 67-100MHz",
"PCI-X 50-66MHz",
"PCI 33 or 66MHz"
};
#define TESTMODE 0x00000800ul

2
sys/dev/ath/ath_hal/ar5210/ar5210_reset.c
View File

@ -87,7 +87,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
if (!IEEE80211_IS_CHAN_5GHZ(chan)) {
/* Only 11a mode */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5Ghz\n", __func__);
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5GHz\n", __func__);
FAIL(HAL_EINVAL);
}
/*

2
sys/dev/ath/if_ath.c
View File

@ -5351,7 +5351,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
ath_stoprecv(sc); /* turn off frame recv */
if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
if_printf(ifp, "%s: unable to reset "
"channel %u (%u Mhz, flags 0x%x), hal status %u\n",
"channel %u (%u MHz, flags 0x%x), hal status %u\n",
__func__, ieee80211_chan2ieee(ic, chan),
chan->ic_freq, chan->ic_flags, status);
return EIO;

2
sys/dev/ct/ct_isa.c
View File

@ -316,7 +316,7 @@ ct_isa_attach(device_t dev)
break;
}
#if 0
printf("%s: chiprev %s chipclk %d Mhz\n",
printf("%s: chiprev %s chipclk %d MHz\n",
slp->sl_dev.dv_xname, s, ct->sc_chipclk);
#endif

2
sys/dev/mly/mly.c
View File

@ -2528,7 +2528,7 @@ mly_describe_controller(struct mly_softc *sc)
mly_describe_code(mly_table_memorytype, mi->memory_type),
mi->memory_parity ? "+parity": "",mi->memory_ecc ? "+ECC": "",
mi->cache_size);
mly_printf(sc, "CPU: %s @ %dMHZ\n",
mly_printf(sc, "CPU: %s @ %dMHz\n",
mly_describe_code(mly_table_cputype, mi->cpu[0].type), mi->cpu[0].speed);
if (mi->l2cache_size != 0)
mly_printf(sc, "%dKB L2 cache\n", mi->l2cache_size);

2
sys/i386/i386/local_apic.c
View File

@ -450,7 +450,7 @@ lapic_setup_clock(void)
panic("lapic: Divisor too big");
value /= 2;
if (bootverbose)
printf("lapic: Divisor %lu, Frequency %lu hz\n",
printf("lapic: Divisor %lu, Frequency %lu Hz\n",
lapic_timer_divisor, value);
/*

6
tools/tools/ath/athdecode/main.c
View File

@ -125,13 +125,13 @@ opmark(FILE *fd, int i, const struct athregrec *r)
fprintf(fd, "ar%uReset (done), OK", state.chipnum);
break;
case AH_MARK_CHIPRESET:
fprintf(fd, "ar%uChipReset, channel %u Mhz", state.chipnum, r->val);
fprintf(fd, "ar%uChipReset, channel %u MHz", state.chipnum, r->val);
break;
case AH_MARK_PERCAL:
fprintf(fd, "ar%uPerCalibration, channel %u Mhz", state.chipnum, r->val);
fprintf(fd, "ar%uPerCalibration, channel %u MHz", state.chipnum, r->val);
break;
case AH_MARK_SETCHANNEL:
fprintf(fd, "ar%uSetChannel, channel %u Mhz", state.chipnum, r->val);
fprintf(fd, "ar%uSetChannel, channel %u MHz", state.chipnum, r->val);
break;
case AH_MARK_ANI_RESET:
switch (r->val) {