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Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this

Browse Source 
shifts into the sign bit.  Instead use (1U << 31) which gets the
expected result.

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

Discussed with:	-arch, rdivacky
Reviewed by:	cperciva
This commit is contained in:
Eitan Adler 2013-11-30 22:17:27 +00:00
parent c8aef31d30
commit 7a22215c53
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=258780
112 changed files with 327 additions and 327 deletions
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6
lib/libc/sparc64/fpu/fpu.c
View File

@ -202,7 +202,7 @@ static const int opmask[] = {0, 0, 1, 3, 1};
* Implement a move operation for all supported operand types. The additional
* nand and xor parameters will be applied to the upper 32 bit word of the
* source operand. This allows to implement fabs and fneg (for fp operands
* only!) using this functions, too, by passing (1 << 31) for one of the
* only!) using this functions, too, by passing (1U << 31) for one of the
* parameters, and 0 for the other.
*/
static void
@ -358,10 +358,10 @@ __fpu_execute(struct utrapframe *uf, struct fpemu *fe, u_int32_t insn,
__fpu_mov(fe, type, rd, rs2, 0, 0);
return (0);
case FOP(INS2_FPop1, INSFP1_FNEG):
__fpu_mov(fe, type, rd, rs2, 0, (1 << 31));
__fpu_mov(fe, type, rd, rs2, 0, (1U << 31));
return (0);
case FOP(INS2_FPop1, INSFP1_FABS):
__fpu_mov(fe, type, rd, rs2, (1 << 31), 0);
__fpu_mov(fe, type, rd, rs2, (1U << 31), 0);
return (0);
case FOP(INS2_FPop1, INSFP1_FSQRT):
__fpu_explode(fe, &fe->fe_f1, type, rs2);

2
lib/libc/sparc64/fpu/fpu_sqrt.c
View File

@ -257,7 +257,7 @@ __fpu_sqrt(fe)
* double x correctly while doing the `known q=1.0'.
*
* We do this one mantissa-word at a time, as noted above, to
* save work. To avoid `(1 << 31) << 1', we also do the top bit
* save work. To avoid `(1U << 31) << 1', we also do the top bit
* outside of each per-word loop.
*
* The calculation `t = y + bit' breaks down into `t0 = y0, ...,

2
lib/libc/xdr/xdr_rec.c
View File

@ -106,7 +106,7 @@ static const struct xdr_ops xdrrec_ops = {
* meet the needs of xdr and rpc based on tcp.
*/
#define LAST_FRAG ((u_int32_t)(1 << 31))
#define LAST_FRAG ((u_int32_t)(1U << 31))
typedef struct rec_strm {
char *tcp_handle;

2
sys/amd64/pci/pci_cfgreg.c
View File

@ -184,7 +184,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
(unsigned)reg <= PCI_REGMAX && bytes != 3 &&
(unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) {
outl(CONF1_ADDR_PORT, (1 << 31) | (bus << 16) | (slot << 11)
outl(CONF1_ADDR_PORT, (1U << 31) | (bus << 16) | (slot << 11)
| (func << 8) | (reg & ~0x03));
dataport = CONF1_DATA_PORT + (reg & 0x03);
}

2
sys/amd64/vmm/intel/vmcs.h
View File

@ -318,7 +318,7 @@ uint64_t vmcs_read(uint32_t encoding);
/*
* VMCS IDT-Vectoring information fields
*/
#define VMCS_IDT_VEC_VALID (1 << 31)
#define VMCS_IDT_VEC_VALID (1U << 31)
#define VMCS_IDT_VEC_ERRCODE_VALID (1 << 11)
/*

2
sys/amd64/vmm/intel/vmx_controls.h
View File

@ -56,7 +56,7 @@
#define PROCBASED_MSR_BITMAPS (1 << 28)
#define PROCBASED_MONITOR_EXITING (1 << 29)
#define PROCBASED_PAUSE_EXITING (1 << 30)
#define PROCBASED_SECONDARY_CONTROLS (1 << 31)
#define PROCBASED_SECONDARY_CONTROLS (1U << 31)
/* Secondary Processor-Based VM-Execution Controls */
#define PROCBASED2_VIRTUALIZE_APIC (1 << 0)

4
sys/amd64/vmm/intel/vtd.c
View File

@ -73,11 +73,11 @@ struct vtdmap {
#define VTD_GCR_WBF (1 << 27)
#define VTD_GCR_SRTP (1 << 30)
#define VTD_GCR_TE (1 << 31)
#define VTD_GCR_TE (1U << 31)
#define VTD_GSR_WBFS (1 << 27)
#define VTD_GSR_RTPS (1 << 30)
#define VTD_GSR_TES (1 << 31)
#define VTD_GSR_TES (1U << 31)
#define VTD_CCR_ICC (1UL << 63) /* invalidate context cache */
#define VTD_CCR_CIRG_GLOBAL (1UL << 61) /* global invalidation */

2
sys/arm/arm/cpufunc_asm_pj4b.S
View File

@ -105,7 +105,7 @@ ENTRY(pj4b_config)
orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */
orr r0, r0, #(1 << 29) /* Disable MO device read / write */
orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/
orr r0, r0, #(1 << 31) /* Enable write evict */
orr r0, r0, #(1U << 31) /* Enable write evict */
mcr p15, 1, r0, c15, c1, 2
#if defined(SMP)
/* Set SMP mode in Auxiliary Control Register */

2
sys/arm/arm/db_trace.c
View File

@ -376,7 +376,7 @@ db_stack_trace_cmd(struct unwind_state *state)
index = db_find_index(state->start_pc);
if (index->insn != EXIDX_CANTUNWIND) {
if (index->insn & (1 << 31)) {
if (index->insn & (1U << 31)) {
/* The data is within the instruction */
state->insn = &index->insn;
} else {

2
sys/arm/arm/pl190.c
View File

@ -113,7 +113,7 @@ pl190_intc_attach(device_t dev)
/* Disable all interrupts */
intc_vic_write_4(VICINTENCLEAR, 0xffffffff);
/* Enable INT31, SIC IRQ */
intc_vic_write_4(VICINTENABLE, (1 << 31));
intc_vic_write_4(VICINTENABLE, (1U << 31));
id = 0;
for (i = 3; i >= 0; i--) {

4
sys/arm/at91/if_macbvar.h
View File

@ -18,7 +18,7 @@
struct eth_tx_desc {
uint32_t addr;
uint32_t flags;
#define TD_OWN (1 << 31)
#define TD_OWN (1U << 31)
#define TD_LAST (1 << 15)
#define TD_WRAP_MASK (1 << 30)
};
@ -30,7 +30,7 @@ struct eth_rx_desc {
#define RD_OWN 0x00000001
uint32_t flags;
#define RD_BROADCAST (1 << 31)
#define RD_BROADCAST (1U << 31)
#define RD_MULTICAST (1 << 30)
#define RD_UNICAST (1 << 29)
#define RD_EXTERNAL (1 << 28)

2
sys/arm/broadcom/bcm2835/bcm2835_dma.c
View File

@ -74,7 +74,7 @@ __FBSDID("$FreeBSD$");
#define CS_WAITWRT (1 << 28)
#define CS_DISDBG (1 << 29)
#define CS_ABORT (1 << 30)
#define CS_RESET (1 << 31)
#define CS_RESET (1U << 31)
#define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04)
#define BCM_DMA_INFO(n) (0x100*(n) + 0x08)
#define INFO_INT_EN (1 << 0)

2
sys/arm/econa/if_ece.c
View File

@ -1243,7 +1243,7 @@ configure_cpu_port(struct ece_softc *sc)
/* SA learning Disable */
cpu_port_config |= (SA_LEARNING_DISABLE);
/* set data offset + 2 */
cpu_port_config &= ~(1 << 31);
cpu_port_config &= ~(1U << 31);
write_4(sc, CPU_PORT_CONFIG, cpu_port_config);

2
sys/arm/freescale/imx/imx6_anatopreg.h
View File

@ -37,7 +37,7 @@
#define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014
#define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018
#define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C
#define IMX6_ANALOG_CCM_PLL_USB_LOCK (1 << 31)
#define IMX6_ANALOG_CCM_PLL_USB_LOCK (1U << 31)
#define IMX6_ANALOG_CCM_PLL_USB_BYPASS (1 << 16)
#define IMX6_ANALOG_CCM_PLL_USB_ENABLE (1 << 13)
#define IMX6_ANALOG_CCM_PLL_USB_POWER (1 << 12)

2
sys/arm/freescale/imx/imx6_usbphy.c
View File

@ -57,7 +57,7 @@ __FBSDID("$FreeBSD$");
#define CTRL_SET_REG 0x0034
#define CTRL_CLR_REG 0x0038
#define CTRL_TOGGLE_REG 0x003c
#define CTRL_SFTRST (1 << 31)
#define CTRL_SFTRST (1U << 31)
#define CTRL_CLKGATE (1 << 30)
#define CTRL_ENUTMILEVEL3 (1 << 15)
#define CTRL_ENUTMILEVEL2 (1 << 14)

2
sys/arm/freescale/imx/imx_gptreg.h
View File

@ -32,7 +32,7 @@
/* Registers definition for Freescale i.MX515 Generic Periodic Timer */
#define IMX_GPT_CR 0x0000 /* Control Register R/W */
#define GPT_CR_FO3 (1 << 31)
#define GPT_CR_FO3 (1U << 31)
#define GPT_CR_FO2 (1 << 30)
#define GPT_CR_FO1 (1 << 29)
#define GPT_CR_OM3_SHIFT 26

2
sys/arm/freescale/vybrid/vf_anadig.c
View File

@ -90,7 +90,7 @@ __FBSDID("$FreeBSD$");
#define USB_LOOPBACK(n) (0x1E0 + 0x60 * n)
#define USB_MISC(n) (0x1F0 + 0x60 * n)
#define ANADIG_PLL_LOCKED (1 << 31)
#define ANADIG_PLL_LOCKED (1U << 31)
#define ENABLE_LINREG (1 << 0)
#define EN_CLK_TO_UTMI (1 << 30)

2
sys/arm/freescale/vybrid/vf_ccm.c
View File

@ -79,7 +79,7 @@ __FBSDID("$FreeBSD$");
#define CCM_CPPDSR 0x88 /* PLL PFD Disable Status Register */
#define CCM_CCOWR 0x8C /* CORE Wakeup Register */
#define PLL3_PFD4_EN (1 << 31)
#define PLL3_PFD4_EN (1U << 31)
#define PLL3_PFD3_EN (1 << 30)
#define PLL3_PFD2_EN (1 << 29)
#define PLL3_PFD1_EN (1 << 28)

2
sys/arm/freescale/vybrid/vf_ehci.c
View File

@ -105,7 +105,7 @@ __FBSDID("$FreeBSD$");
#define USBPHY_IP_CLR 0x98 /* PHY IP Block Register */
#define USBPHY_IP_TOG 0x9C /* PHY IP Block Register */
#define USBPHY_CTRL_SFTRST (1 << 31)
#define USBPHY_CTRL_SFTRST (1U << 31)
#define USBPHY_CTRL_CLKGATE (1 << 30)
#define USBPHY_DEBUG_CLKGATE (1 << 30)

2
sys/arm/include/armreg.h
View File

@ -360,7 +360,7 @@
#define CPU_CT_ARMV7 0x4
/* ARM v7 Cache type definitions */
#define CPUV7_CT_CTYPE_WT (1 << 31)
#define CPUV7_CT_CTYPE_WT (1U << 31)
#define CPUV7_CT_CTYPE_WB (1 << 30)
#define CPUV7_CT_CTYPE_RA (1 << 29)
#define CPUV7_CT_CTYPE_WA (1 << 28)

6
sys/arm/lpc/if_lpereg.h
View File

@ -169,7 +169,7 @@ struct lpe_hwstatus {
/* These are valid for both Rx and Tx descriptors */
#define LPE_HWDESC_SIZE_MASK (1 << 10)
#define LPE_HWDESC_INTERRUPT (1 << 31)
#define LPE_HWDESC_INTERRUPT (1U << 31)
/* These are valid for Tx descriptors */
#define LPE_HWDESC_LAST (1 << 30)
@ -186,7 +186,7 @@ struct lpe_hwstatus {
#define LPE_HWDESC_LATECOLL (1 << 28)
#define LPE_HWDESC_UNDERRUN (1 << 29)
#define LPE_HWDESC_TXNODESCR (1 << 30)
#define LPE_HWDESC_ERROR (1 << 31)
#define LPE_HWDESC_ERROR (1U << 31)
/* These are valid for Rx status descriptors */
#define LPE_HWDESC_CONTROL (1 << 18)
@ -202,7 +202,7 @@ struct lpe_hwstatus {
#define LPE_HWDESC_OVERRUN (1 << 28)
#define LPE_HWDESC_RXNODESCR (1 << 29)
#define LPE_HWDESC_LASTFLAG (1 << 30)
#define LPE_HWDESC_ERROR (1 << 31)
#define LPE_HWDESC_ERROR (1U << 31)
#endif /* _ARM_LPC_IF_LPEREG_H */

2
sys/arm/lpc/lpcreg.h
View File

@ -604,7 +604,7 @@
#define LPC_DMAC_CH_LLI 0x08
#define LPC_DMAC_CH_LLI_AHB1 (1 << 0)
#define LPC_DMAC_CH_CONTROL 0x0c
#define LPC_DMAC_CH_CONTROL_I (1 << 31)
#define LPC_DMAC_CH_CONTROL_I (1U << 31)
#define LPC_DMAC_CH_CONTROL_DI (1 << 27)
#define LPC_DMAC_CH_CONTROL_SI (1 << 26)
#define LPC_DMAC_CH_CONTROL_D (1 << 25)

2
sys/arm/mv/mv_pci.c
View File

@ -81,7 +81,7 @@ __FBSDID("$FreeBSD$");
#define debugf(fmt, args...)
#endif
#define PCI_CFG_ENA (1 << 31)
#define PCI_CFG_ENA (1U << 31)
#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
#define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)

2
sys/arm/samsung/exynos/ehci_exynos5.c
View File

@ -82,7 +82,7 @@ __FBSDID("$FreeBSD$");
#define HOST_CTRL_SUSPEND (1 << 4)
#define HOST_CTRL_RESET_LINK (1 << 1)
#define HOST_CTRL_RESET_PHY (1 << 0)
#define HOST_CTRL_RESET_PHY_ALL (1 << 31)
#define HOST_CTRL_RESET_PHY_ALL (1U << 31)
/* Forward declarations */
static int exynos_ehci_attach(device_t dev);

10
sys/arm/xscale/i8134x/i81342reg.h
View File

@ -83,7 +83,7 @@
#define IOP34X_ADMA_PQTE (1 << 18) /* P+Q Transfer Enable */
#define IOP34X_ADMA_PTD (1 << 19) /* P Transfer Disable */
#define IOP34X_ADMA_ROE (1 << 30) /* Relaxed Ordering Enable */
#define IOP34X_ADMA_NSE (1 << 31) /* No Snoop Enable */
#define IOP34X_ADMA_NSE (1U << 31) /* No Snoop Enable */
#define IOP34X_PBBAR0 0x81588 /* PBI Base Address Register 0 */
#define IOP34X_PBBAR0_ADDRMASK 0xfffff000
@ -113,7 +113,7 @@
#define SMC_SDBR 0x8180c /* Base Register */
#define SMC_SDBR_BASEADDR (1 << 27)
#define SMC_SDBR_BASEADDR_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \
| (1 << 31))
| (1U << 31))
#define SMC_SDUBR 0x81810 /* Upper Base Register */
#define SMC_SBSR 0x81814 /* SDRAM Bank Size Register */
#define SMC_SBSR_BANK_NB (1 << 2) /* Number of DDR Banks
@ -128,7 +128,7 @@
0x01000 1GB
*/
#define SMC_SBSR_BANK_SZ_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \
| (1 << 31))
| (1U << 31))
/* Two possible addresses for ATUe depending on configuration. */
@ -190,7 +190,7 @@
#define ATU_CR_OUT_EN (1 << 1)
#define ATU_PCSR 0x0074 /* PCI Configuration and Status Register */
#define PCIE_BUSNO(x) ((x & 0xff000000) >> 24)
#define ATUX_CORE_RST ((1 << 30) | (1 << 31)) /* Core Processor Reset */
#define ATUX_CORE_RST ((1 << 30) | (1U << 31)) /* Core Processor Reset */
#define ATUX_P_RSTOUT (1 << 21) /* Central Resource PCI Bus Reset */
#define ATUE_CORE_RST ((1 << 9) | (1 << 8)) /* Core Processor Reset */
#define ATU_ISR 0x0078 /* ATU Interrupt Status Register */
@ -250,7 +250,7 @@
#define ATU_OIOWTVR 0x0304 /* Outbound I/O Window Translate Value Reg */
#define ATU_OUMBAR0 0x0308 /* Outbound Upper Memory Window base addr reg 0*/
#define ATU_OUMBAR_FUNC (28)
#define ATU_OUMBAR_EN (1 << 31)
#define ATU_OUMBAR_EN (1U << 31)
#define ATU_OUMWTVR0 0x030c /* Outbound Upper 32bit Memory Window Translate Value Register 0 */
#define ATU_OUMBAR1 0x0310 /* Outbound Upper Memory Window base addr reg1*/
#define ATU_OUMWTVR1 0x0314 /* Outbound Upper 32bit Memory Window Translate Value Register 1 */

2
sys/arm/xscale/ixp425/ixp425reg.h
View File

@ -400,7 +400,7 @@
#define EXP_CNFG0_PCI_HOST (1 << 1)
#define EXP_CNFG0_PCI_ARB (1 << 2)
#define EXP_CNFG0_PCI_66MHZ (1 << 4)
#define EXP_CNFG0_MEM_MAP (1 << 31)
#define EXP_CNFG0_MEM_MAP (1U << 31)
/* EXP_CNFG1 bits */
#define EXP_CNFG1_SW_INT0 (1 << 0)

2
sys/boot/arm/at91/libat91/mci_device.h
View File

@ -306,7 +306,7 @@ typedef struct _AT91S_MciDevice
#define AT91C_VDD_33_34 (1 << 21)
#define AT91C_VDD_34_35 (1 << 22)
#define AT91C_VDD_35_36 (1 << 23)
#define AT91C_CARD_POWER_UP_BUSY (1 << 31)
#define AT91C_CARD_POWER_UP_BUSY (1U << 31)
#define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 | AT91C_VDD_28_29 | \
AT91C_VDD_29_30 | AT91C_VDD_30_31 | AT91C_VDD_31_32 | AT91C_VDD_32_33)

4
sys/boot/i386/libfirewire/fwohci.h
View File

@ -76,7 +76,7 @@ void fwohci_poll(struct fwohci_softc *);
#define OHCI_CROMHDR 0x18
#define OHCI_BUS_ID 0x1c
#define OHCI_BUS_OPT 0x20
#define OHCI_BUSIRMC (1 << 31)
#define OHCI_BUSIRMC (1U << 31)
#define OHCI_BUSCMC (1 << 30)
#define OHCI_BUSISC (1 << 29)
#define OHCI_BUSBMC (1 << 28)
@ -102,7 +102,7 @@ void fwohci_poll(struct fwohci_softc *);
#define OHCI_SID_BUF 0x64
#define OHCI_SID_CNT 0x68
#define OHCI_SID_ERR (1 << 31)
#define OHCI_SID_ERR (1U << 31)
#define OHCI_SID_CNT_MASK 0xffc
#define OHCI_IT_STAT 0x90

4
sys/boot/i386/libfirewire/fwohcireg.h
View File

@ -239,7 +239,7 @@ struct ohci_registers {
fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */
#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */
#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */
#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */
#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */
@ -278,7 +278,7 @@ struct ohci_registers {
fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/
#define FWOHCI_NODEID 0xe8
fwohcireg_t node; /* Node ID 0xe8 */
#define OHCI_NODE_VALID (1 << 31)
#define OHCI_NODE_VALID (1U << 31)
#define OHCI_NODE_ROOT (1 << 30)
#define OHCI_ASYSRCBUS 1

2
sys/dev/aac/aacvar.h
View File

@ -412,7 +412,7 @@ struct aac_softc
#define AAC_FLAGS_RAW_IO (1 << 12) /* Raw I/O interface */
#define AAC_FLAGS_ARRAY_64BIT (1 << 13) /* 64-bit array size */
#define AAC_FLAGS_LBA_64BIT (1 << 14) /* 64-bit LBA support */
#define AAC_FLAGS_NOMSI (1 << 31) /* Broken MSI */
#define AAC_FLAGS_NOMSI (1U << 31) /* Broken MSI */
u_int32_t supported_options;
u_int32_t scsi_method_id;

4
sys/dev/acpica/acpi_video.c
View File

@ -132,7 +132,7 @@ static void vo_set_device_state(ACPI_HANDLE, UINT32);
#define DOD_HEAD_ID_BITS 3
#define DOD_HEAD_ID_MASK \
(((1 << DOD_HEAD_ID_BITS) - 1) << DOD_HEAD_ID_SHIFT)
#define DOD_DEVID_SCHEME_STD (1 << 31)
#define DOD_DEVID_SCHEME_STD (1U << 31)
/* _BCL related constants */
#define BCL_FULLPOWER 0
@ -149,7 +149,7 @@ static void vo_set_device_state(ACPI_HANDLE, UINT32);
#define DSS_INACTIVE 0
#define DSS_ACTIVE (1 << 0)
#define DSS_SETNEXT (1 << 30)
#define DSS_COMMIT (1 << 31)
#define DSS_COMMIT (1U << 31)
static device_method_t acpi_video_methods[] = {
DEVMETHOD(device_identify, acpi_video_identify),

4
sys/dev/agp/agp_i810.c
View File

@ -2226,10 +2226,10 @@ agp_i830_chipset_flush(device_t dev)
sc = device_get_softc(dev);
pmap_invalidate_cache();
hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);
bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1 << 31));
bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1U << 31));
for (i = 0; i < 20000 /* 1 sec */; i++) {
hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);
if ((hic & (1 << 31)) == 0)
if ((hic & (1U << 31)) == 0)
break;
DELAY(50);
}

2
sys/dev/ahci/ahci.h
View File

@ -321,7 +321,7 @@ struct ahci_dma_prd {
u_int32_t dbc; /* 0 based */
#define AHCI_PRD_MASK 0x003fffff /* max 4MB */
#define AHCI_PRD_MAX (AHCI_PRD_MASK + 1)
#define AHCI_PRD_IPC (1 << 31)
#define AHCI_PRD_IPC (1U << 31)
} __packed;
struct ahci_cmd_tab {

2
sys/dev/bktr/bktr_core.c
View File

@ -2599,7 +2599,7 @@ dump_bt848( bktr_ptr_t bktr )
#define BKTR_TEST_RISC_STATUS_BIT0 (1 << 28)
#define BKTR_TEST_RISC_STATUS_BIT1 (1 << 29)
#define BKTR_TEST_RISC_STATUS_BIT2 (1 << 30)
#define BKTR_TEST_RISC_STATUS_BIT3 (1 << 31)
#define BKTR_TEST_RISC_STATUS_BIT3 (1U << 31)
static bool_t notclipped (bktr_reg_t * bktr, int x, int width) {
int i;

30
sys/dev/drm/i915_reg.h
View File

@ -349,7 +349,7 @@ __FBSDID("$FreeBSD$");
#define VGA1_PD_P1_MASK (0x1f << 8)
#define DPLL_A 0x06014
#define DPLL_B 0x06018
#define DPLL_VCO_ENABLE (1 << 31)
#define DPLL_VCO_ENABLE (1U << 31)
#define DPLL_DVO_HIGH_SPEED (1 << 30)
#define DPLL_SYNCLOCK_ENABLE (1 << 29)
#define DPLL_VGA_MODE_DIS (1 << 28)
@ -653,7 +653,7 @@ __FBSDID("$FreeBSD$");
/* SDVO port control */
#define SDVOB 0x61140
#define SDVOC 0x61160
#define SDVO_ENABLE (1 << 31)
#define SDVO_ENABLE (1U << 31)
#define SDVO_PIPE_B_SELECT (1 << 30)
#define SDVO_STALL_SELECT (1 << 29)
#define SDVO_INTERRUPT_ENABLE (1 << 26)
@ -690,7 +690,7 @@ __FBSDID("$FreeBSD$");
#define DVOA 0x61120
#define DVOB 0x61140
#define DVOC 0x61160
#define DVO_ENABLE (1 << 31)
#define DVO_ENABLE (1U << 31)
#define DVO_PIPE_B_SELECT (1 << 30)
#define DVO_PIPE_STALL_UNUSED (0 << 28)
#define DVO_PIPE_STALL (1 << 28)
@ -726,7 +726,7 @@ __FBSDID("$FreeBSD$");
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
* the DPLL semantics change when the LVDS is assigned to that pipe.
*/
#define LVDS_PORT_EN (1 << 31)
#define LVDS_PORT_EN (1U << 31)
/* Selects pipe B for LVDS data. Must be set on pre-965. */
#define LVDS_PIPEB_SELECT (1 << 30)
/*
@ -762,7 +762,7 @@ __FBSDID("$FreeBSD$");
/* Panel power sequencing */
#define PP_STATUS 0x61200
#define PP_ON (1 << 31)
#define PP_ON (1U << 31)
/*
* Indicates that all dependencies of the panel are on:
*
@ -783,7 +783,7 @@ __FBSDID("$FreeBSD$");
/* Panel fitting */
#define PFIT_CONTROL 0x61230
#define PFIT_ENABLE (1 << 31)
#define PFIT_ENABLE (1U << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
#define VERT_INTERP_DISABLE (0 << 10)
@ -826,7 +826,7 @@ __FBSDID("$FreeBSD$");
/* TV port control */
#define TV_CTL 0x68000
/** Enables the TV encoder */
# define TV_ENC_ENABLE (1 << 31)
# define TV_ENC_ENABLE (1U << 31)
/** Sources the TV encoder input from pipe B instead of A. */
# define TV_ENC_PIPEB_SELECT (1 << 30)
/** Outputs composite video (DAC A only) */
@ -897,7 +897,7 @@ __FBSDID("$FreeBSD$");
*
* This gets cleared when TV_DAC_STATE_EN is cleared
*/
# define TVDAC_STATE_CHG (1 << 31)
# define TVDAC_STATE_CHG (1U << 31)
# define TVDAC_SENSE_MASK (7 << 28)
/** Reports that DAC A voltage is above the detect threshold */
# define TVDAC_A_SENSE (1 << 30)
@ -1024,7 +1024,7 @@ __FBSDID("$FreeBSD$");
#define TV_H_CTL_2 0x68034
/** Enables the colorburst (needed for non-component color) */
# define TV_BURST_ENA (1 << 31)
# define TV_BURST_ENA (1U << 31)
/** Offset of the colorburst from the start of hsync, in pixels minus one. */
# define TV_HBURST_START_SHIFT 16
# define TV_HBURST_START_MASK 0x1fff0000
@ -1069,7 +1069,7 @@ __FBSDID("$FreeBSD$");
#define TV_V_CTL_3 0x68044
/** Enables generation of the equalization signal */
# define TV_EQUAL_ENA (1 << 31)
# define TV_EQUAL_ENA (1U << 31)
/** Length of vsync, in half lines */
# define TV_VEQ_LEN_MASK 0x007f0000
# define TV_VEQ_LEN_SHIFT 16
@ -1143,7 +1143,7 @@ __FBSDID("$FreeBSD$");
#define TV_SC_CTL_1 0x68060
/** Turns on the first subcarrier phase generation DDA */
# define TV_SC_DDA1_EN (1 << 31)
# define TV_SC_DDA1_EN (1U << 31)
/** Turns on the first subcarrier phase generation DDA */
# define TV_SC_DDA2_EN (1 << 30)
/** Turns on the first subcarrier phase generation DDA */
@ -1206,7 +1206,7 @@ __FBSDID("$FreeBSD$");
* If set, the rest of the registers are ignored, and the calculated values can
* be read back from the register.
*/
# define TV_AUTO_SCALE (1 << 31)
# define TV_AUTO_SCALE (1U << 31)
/**
* Disables the vertical filter.
*
@ -1269,7 +1269,7 @@ __FBSDID("$FreeBSD$");
# define TV_VSCALE_IP_FRAC_SHIFT 0
#define TV_CC_CONTROL 0x68090
# define TV_CC_ENABLE (1 << 31)
# define TV_CC_ENABLE (1U << 31)
/**
* Specifies which field to send the CC data in.
*
@ -1285,7 +1285,7 @@ __FBSDID("$FreeBSD$");
# define TV_CC_LINE_SHIFT 0
#define TV_CC_DATA 0x68094
# define TV_CC_RDY (1 << 31)
# define TV_CC_RDY (1U << 31)
/** Second word of CC data to be transmitted. */
# define TV_CC_DATA_2_MASK 0x007f0000
# define TV_CC_DATA_2_SHIFT 16
@ -1469,7 +1469,7 @@ __FBSDID("$FreeBSD$");
/* VBIOS regs */
#define VGACNTRL 0x71400
# define VGA_DISP_DISABLE (1 << 31)
# define VGA_DISP_DISABLE (1U << 31)
# define VGA_2X_MODE (1 << 30)
# define VGA_PIPE_B_SELECT (1 << 29)

6
sys/dev/drm/mach64_drv.h
View File

@ -202,7 +202,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device *dev);
# define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0)
# define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0)
# define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0)
# define MACH64_LAST_DESCRIPTOR (1 << 31)
# define MACH64_LAST_DESCRIPTOR (1U << 31)
#define MACH64_BM_HOSTDATA 0x0644
#define MACH64_BM_STATUS 0x018c
#define MACH64_BM_SYSTEM_MEM_ADDR 0x0184
@ -316,7 +316,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device *dev);
#define MACH64_FIFO_STAT 0x0710
# define MACH64_FIFO_SLOT_MASK 0x0000ffff
# define MACH64_FIFO_ERR (1 << 31)
# define MACH64_FIFO_ERR (1U << 31)
#define MACH64_GEN_TEST_CNTL 0x04d0
# define MACH64_GUI_ENGINE_ENABLE (1 << 8)
@ -442,7 +442,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device *dev);
# define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */
# define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */
# define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */
# define MACH64_CRTC_VBLANK2_INT (1 << 31)
# define MACH64_CRTC_VBLANK2_INT (1U << 31)
# define MACH64_CRTC_INT_ENS \
( \
MACH64_CRTC_VBLANK_INT_EN | \

4
sys/dev/drm/mga_drv.h
View File

@ -458,7 +458,7 @@ do { \
# define MGA_BLTMOD_BU24RGB (15 << 25)
# define MGA_PATTERN (1 << 29)
# define MGA_TRANSC (1 << 30)
# define MGA_CLIPDIS (1 << 31)
# define MGA_CLIPDIS (1U << 31)
#define MGA_DWGSYNC 0x2c4c
#define MGA_FCOL 0x1c24
@ -526,7 +526,7 @@ do { \
#define MGA_TEXCTL2 0x2c3c
# define MGA_DUALTEX (1 << 7)
# define MGA_G400_TC2_MAGIC (1 << 15)
# define MGA_MAP1_ENABLE (1 << 31)
# define MGA_MAP1_ENABLE (1U << 31)
#define MGA_TEXFILTER 0x2c58
#define MGA_TEXHEIGHT 0x2c2c
#define MGA_TEXORG 0x2c24

10
sys/dev/drm/r128_drv.h
View File

@ -227,7 +227,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
# define R128_ROP3_P 0x00f00000
#define R128_DP_WRITE_MASK 0x16cc
#define R128_DST_PITCH_OFFSET_C 0x1c80
# define R128_DST_TILE (1 << 31)
# define R128_DST_TILE (1U << 31)
#define R128_GEN_INT_CNTL 0x0040
# define R128_CRTC_VBLANK_INT_EN (1 << 0)
@ -246,7 +246,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
#define R128_GUI_STAT 0x1740
# define R128_GUI_FIFOCNT_MASK 0x0fff
# define R128_GUI_ACTIVE (1 << 31)
# define R128_GUI_ACTIVE (1U << 31)
#define R128_MCLK_CNTL 0x000f
# define R128_FORCE_GCP (1 << 16)
@ -258,7 +258,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
# define R128_PC_FLUSH_GUI (3 << 0)
# define R128_PC_RI_GUI (1 << 2)
# define R128_PC_FLUSH_ALL 0x00ff
# define R128_PC_BUSY (1 << 31)
# define R128_PC_BUSY (1U << 31)
#define R128_PCI_GART_PAGE 0x017c
#define R128_PRIM_TEX_CNTL_C 0x1cb0
@ -302,7 +302,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
#define R128_PM4_BUFFER_DL_RPTR 0x0710
#define R128_PM4_BUFFER_DL_WPTR 0x0714
# define R128_PM4_BUFFER_DL_DONE (1 << 31)
# define R128_PM4_BUFFER_DL_DONE (1U << 31)
#define R128_PM4_VC_FPU_SETUP 0x071c
@ -312,7 +312,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
#define R128_PM4_STAT 0x07b8
# define R128_PM4_FIFOCNT_MASK 0x0fff
# define R128_PM4_BUSY (1 << 16)
# define R128_PM4_GUI_ACTIVE (1 << 31)
# define R128_PM4_GUI_ACTIVE (1U << 31)
#define R128_PM4_MICROCODE_ADDR 0x07d4
#define R128_PM4_MICROCODE_RADDR 0x07d8

6
sys/dev/drm/r300_reg.h
View File

@ -1205,7 +1205,7 @@ __FBSDID("$FreeBSD$");
# define R300_FPI0_OUTC_FRC (9 << 23)
# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
# define R300_FPI0_OUTC_SAT (1 << 30)
# define R300_FPI0_INSERT_NOP (1 << 31)
# define R300_FPI0_INSERT_NOP (1U << 31)
#define R300_PFS_INSTR2_0 0x49C0
# define R300_FPI2_ARGA_SRC0C_X 0
@ -1252,7 +1252,7 @@ __FBSDID("$FreeBSD$");
# define R300_FPI2_OUTA_RCP (10 << 23)
# define R300_FPI2_OUTA_RSQ (11 << 23)
# define R300_FPI2_OUTA_SAT (1 << 30)
# define R300_FPI2_UNKNOWN_31 (1 << 31)
# define R300_FPI2_UNKNOWN_31 (1U << 31)
/* END: Fragment program instruction set */
/* Fog state and color */
@ -1452,7 +1452,7 @@ __FBSDID("$FreeBSD$");
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1U << 31)
#define R300_ZB_BW_CNTL 0x4f1c
# define R300_HIZ_DISABLE (0 << 0)

4
sys/dev/drm/r600_blit.c
View File

@ -1428,12 +1428,12 @@ set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
OUT_RING((x2 << 0) | (y2 << 16));
OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
OUT_RING((x2 << 0) | (y2 << 16));
ADVANCE_RING();
}

2
sys/dev/drm/radeon_cp.c
View File

@ -542,7 +542,7 @@ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
#if 0
u32 tmp;
tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1U << 31);
RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
#endif
}

30
sys/dev/drm/radeon_drv.h
View File

@ -659,7 +659,7 @@ extern int r600_cs_init(struct drm_device *dev);
# define RS480_GTW_LAC_EN (1 << 25)
# define RS480_2LEVEL_GART (0 << 30)
# define RS480_1LEVEL_GART (1 << 30)
# define RS480_PDC_EN (1 << 31)
# define RS480_PDC_EN (1U << 31)
#define RS480_GART_BASE 0x2c
#define RS480_GART_CACHE_CNTRL 0x2e
# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
@ -775,7 +775,7 @@ extern int r600_cs_init(struct drm_device *dev);
# define R300_SUBPIXEL_1_12 (0 << 16)
# define R300_SUBPIXEL_1_16 (1 << 16)
#define R300_DST_PIPE_CONFIG 0x170c
# define R300_PIPE_AUTO_CONFIG (1 << 31)
# define R300_PIPE_AUTO_CONFIG (1U << 31)
#define R300_RB2D_DSTCACHE_MODE 0x3428
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
@ -902,7 +902,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R300_RB2D_DC_FLUSH (3 << 0)
# define R300_RB2D_DC_FREE (3 << 2)
# define R300_RB2D_DC_FLUSH_ALL 0xf
# define R300_RB2D_DC_BUSY (1 << 31)
# define R300_RB2D_DC_BUSY (1U << 31)
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
@ -924,16 +924,16 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_RB3D_ZC_FLUSH (1 << 0)
# define RADEON_RB3D_ZC_FREE (1 << 2)
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
# define RADEON_RB3D_ZC_BUSY (1 << 31)
# define RADEON_RB3D_ZC_BUSY (1U << 31)
#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
# define R300_ZC_BUSY (1 << 31)
# define R300_ZC_BUSY (1U << 31)
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
# define RADEON_RB3D_DC_BUSY (1 << 31)
# define RADEON_RB3D_DC_BUSY (1U << 31)
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FLUSH (2 << 0)
# define R300_RB3D_DC_FREE (2 << 2)
@ -949,7 +949,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
@ -1003,7 +1003,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
# define RADEON_GA_BUSY (1 << 26)
# define RADEON_CBA2D_BUSY (1 << 27)
# define RADEON_RBBM_ACTIVE (1 << 31)
# define RADEON_RBBM_ACTIVE (1U << 31)
#define RADEON_RE_LINE_PATTERN 0x1cd0
#define RADEON_RE_MISC 0x26c4
#define RADEON_RE_TOP_LEFT 0x26c0
@ -1117,7 +1117,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define RADEON_CP_RB_CNTL 0x0704
# define RADEON_BUF_SWAP_32BIT (2 << 16)
# define RADEON_RB_NO_UPDATE (1 << 27)
# define RADEON_RB_RPTR_WR_ENA (1 << 31)
# define RADEON_RB_RPTR_WR_ENA (1U << 31)
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
@ -1193,7 +1193,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
#define RADEON_VTX_Z_PRESENT (1 << 31)
#define RADEON_VTX_Z_PRESENT (1U << 31)
#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
#define RADEON_PRIM_TYPE_NONE (0 << 0)
@ -1524,7 +1524,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define R600_GRBM_STATUS 0x8010
# define R600_CMDFIFO_AVAIL_MASK 0x1f
# define R700_CMDFIFO_AVAIL_MASK 0xf
# define R600_GUI_ACTIVE (1 << 31)
# define R600_GUI_ACTIVE (1U << 31)
#define R600_GRBM_STATUS2 0x8014
#define R600_GRBM_SOFT_RESET 0x8020
# define R600_SOFT_RESET_CP (1 << 0)
@ -1546,7 +1546,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_RB_BUFSZ(x) ((x) << 0)
# define R600_RB_BLKSZ(x) ((x) << 8)
# define R600_RB_NO_UPDATE (1 << 27)
# define R600_RB_RPTR_WR_ENA (1 << 31)
# define R600_RB_RPTR_WR_ENA (1U << 31)
#define R600_CP_RB_RPTR_WR 0xc108
#define R600_CP_RB_RPTR_ADDR 0xc10c
#define R600_CP_RB_RPTR_ADDR_HI 0xc110
@ -1619,7 +1619,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define R600_SX_MISC 0x28350
#define R600_DB_DEBUG 0x9830
# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31)
#define R600_DB_WATERMARKS 0x9838
# define R600_DEPTH_FREE(x) ((x) << 0)
# define R600_DEPTH_FLUSH(x) ((x) << 5)
@ -1679,7 +1679,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_SYNC_WALKER (1 << 25)
# define R600_SYNC_ALIGNER (1 << 26)
# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
# define R600_BILINEAR_PRECISION_8_BIT (1U << 31)
#define R700_TCP_CNTL 0x9610
@ -1753,7 +1753,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_PERSP_GRADIENT_ENA (1 << 28)
# define R600_LINEAR_GRADIENT_ENA (1 << 29)
# define R600_POSITION_SAMPLE (1 << 30)
# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
# define R600_BARYC_AT_SAMPLE_ENA (1U << 31)
#define R600_SPI_PS_IN_CONTROL_1 0x286d0
# define R600_GEN_INDEX_PIX (1 << 0)
# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)

2
sys/dev/drm/via_irq.c
View File

@ -46,7 +46,7 @@ __FBSDID("$FreeBSD$");
#define VIA_REG_INTERRUPT 0x200
/* VIA_REG_INTERRUPT */
#define VIA_IRQ_GLOBAL (1 << 31)
#define VIA_IRQ_GLOBAL (1U << 31)
#define VIA_IRQ_VBLANK_ENABLE (1 << 19)
#define VIA_IRQ_VBLANK_PENDING (1 << 3)
#define VIA_IRQ_HQV0_ENABLE (1 << 11)

44
sys/dev/drm2/i915/i915_reg.h
View File

@ -798,7 +798,7 @@ __FBSDID("$FreeBSD$");
#define _DPLL_A 0x06014
#define _DPLL_B 0x06018
#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
#define DPLL_VCO_ENABLE (1 << 31)
#define DPLL_VCO_ENABLE (1U << 31)
#define DPLL_DVO_HIGH_SPEED (1 << 30)
#define DPLL_SYNCLOCK_ENABLE (1 << 29)
#define DPLL_VGA_MODE_DIS (1 << 28)
@ -1483,7 +1483,7 @@ __FBSDID("$FreeBSD$");
/* SDVO port control */
#define SDVOB 0x61140
#define SDVOC 0x61160
#define SDVO_ENABLE (1 << 31)
#define SDVO_ENABLE (1U << 31)
#define SDVO_PIPE_B_SELECT (1 << 30)
#define SDVO_STALL_SELECT (1 << 29)
#define SDVO_INTERRUPT_ENABLE (1 << 26)
@ -1521,7 +1521,7 @@ __FBSDID("$FreeBSD$");
#define DVOA 0x61120
#define DVOB 0x61140
#define DVOC 0x61160
#define DVO_ENABLE (1 << 31)
#define DVO_ENABLE (1U << 31)
#define DVO_PIPE_B_SELECT (1 << 30)
#define DVO_PIPE_STALL_UNUSED (0 << 28)
#define DVO_PIPE_STALL (1 << 28)
@ -1557,7 +1557,7 @@ __FBSDID("$FreeBSD$");
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
* the DPLL semantics change when the LVDS is assigned to that pipe.
*/
#define LVDS_PORT_EN (1 << 31)
#define LVDS_PORT_EN (1U << 31)
/* Selects pipe B for LVDS data. Must be set on pre-965. */
#define LVDS_PIPEB_SELECT (1 << 30)
#define LVDS_PIPE_MASK (1 << 30)
@ -1604,7 +1604,7 @@ __FBSDID("$FreeBSD$");
/* Video Data Island Packet control */
#define VIDEO_DIP_DATA 0x61178
#define VIDEO_DIP_CTL 0x61170
#define VIDEO_DIP_ENABLE (1 << 31)
#define VIDEO_DIP_ENABLE (1U << 31)
#define VIDEO_DIP_PORT_B (1 << 29)
#define VIDEO_DIP_PORT_C (2 << 29)
#define VIDEO_DIP_ENABLE_AVI (1 << 21)
@ -1620,7 +1620,7 @@ __FBSDID("$FreeBSD$");
/* Panel power sequencing */
#define PP_STATUS 0x61200
#define PP_ON (1 << 31)
#define PP_ON (1U << 31)
/*
* Indicates that all dependencies of the panel are on:
*
@ -1653,7 +1653,7 @@ __FBSDID("$FreeBSD$");
/* Panel fitting */
#define PFIT_CONTROL 0x61230
#define PFIT_ENABLE (1 << 31)
#define PFIT_ENABLE (1U << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
#define VERT_INTERP_DISABLE (0 << 10)
@ -1714,7 +1714,7 @@ __FBSDID("$FreeBSD$");
/* TV port control */
#define TV_CTL 0x68000
/** Enables the TV encoder */
# define TV_ENC_ENABLE (1 << 31)
# define TV_ENC_ENABLE (1U << 31)
/** Sources the TV encoder input from pipe B instead of A. */
# define TV_ENC_PIPEB_SELECT (1 << 30)
/** Outputs composite video (DAC A only) */
@ -1786,7 +1786,7 @@ __FBSDID("$FreeBSD$");
*
* This gets cleared when TV_DAC_STATE_EN is cleared
*/
# define TVDAC_STATE_CHG (1 << 31)
# define TVDAC_STATE_CHG (1U << 31)
# define TVDAC_SENSE_MASK (7 << 28)
/** Reports that DAC A voltage is above the detect threshold */
# define TVDAC_A_SENSE (1 << 30)
@ -1913,7 +1913,7 @@ __FBSDID("$FreeBSD$");
#define TV_H_CTL_2 0x68034
/** Enables the colorburst (needed for non-component color) */
# define TV_BURST_ENA (1 << 31)
# define TV_BURST_ENA (1U << 31)
/** Offset of the colorburst from the start of hsync, in pixels minus one. */
# define TV_HBURST_START_SHIFT 16
# define TV_HBURST_START_MASK 0x1fff0000
@ -1958,7 +1958,7 @@ __FBSDID("$FreeBSD$");
#define TV_V_CTL_3 0x68044
/** Enables generation of the equalization signal */
# define TV_EQUAL_ENA (1 << 31)
# define TV_EQUAL_ENA (1U << 31)
/** Length of vsync, in half lines */
# define TV_VEQ_LEN_MASK 0x007f0000
# define TV_VEQ_LEN_SHIFT 16
@ -2032,7 +2032,7 @@ __FBSDID("$FreeBSD$");
#define TV_SC_CTL_1 0x68060
/** Turns on the first subcarrier phase generation DDA */
# define TV_SC_DDA1_EN (1 << 31)
# define TV_SC_DDA1_EN (1U << 31)
/** Turns on the first subcarrier phase generation DDA */
# define TV_SC_DDA2_EN (1 << 30)
/** Turns on the first subcarrier phase generation DDA */
@ -2095,7 +2095,7 @@ __FBSDID("$FreeBSD$");
* If set, the rest of the registers are ignored, and the calculated values can
* be read back from the register.
*/
# define TV_AUTO_SCALE (1 << 31)
# define TV_AUTO_SCALE (1U << 31)
/**
* Disables the vertical filter.
*
@ -2158,7 +2158,7 @@ __FBSDID("$FreeBSD$");
# define TV_VSCALE_IP_FRAC_SHIFT 0
#define TV_CC_CONTROL 0x68090
# define TV_CC_ENABLE (1 << 31)
# define TV_CC_ENABLE (1U << 31)
/**
* Specifies which field to send the CC data in.
*
@ -2174,7 +2174,7 @@ __FBSDID("$FreeBSD$");
# define TV_CC_LINE_SHIFT 0
#define TV_CC_DATA 0x68094
# define TV_CC_RDY (1 << 31)
# define TV_CC_RDY (1U << 31)
/** Second word of CC data to be transmitted. */
# define TV_CC_DATA_2_MASK 0x007f0000
# define TV_CC_DATA_2_SHIFT 16
@ -2197,7 +2197,7 @@ __FBSDID("$FreeBSD$");
#define DP_C 0x64200
#define DP_D 0x64300
#define DP_PORT_EN (1 << 31)
#define DP_PORT_EN (1U << 31)
#define DP_PIPEB_SELECT (1 << 30)
#define DP_PIPE_MASK (1 << 30)
@ -2307,7 +2307,7 @@ __FBSDID("$FreeBSD$");
#define DPD_AUX_CH_DATA4 0x64320
#define DPD_AUX_CH_DATA5 0x64324
#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
#define DP_AUX_CH_CTL_SEND_BUSY (1U << 31)
#define DP_AUX_CH_CTL_DONE (1 << 30)
#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
@ -2903,7 +2903,7 @@ __FBSDID("$FreeBSD$");
/* VBIOS regs */
#define VGACNTRL 0x71400
# define VGA_DISP_DISABLE (1 << 31)
# define VGA_DISP_DISABLE (1U << 31)
# define VGA_2X_MODE (1 << 30)
# define VGA_PIPE_B_SELECT (1 << 29)
@ -3029,7 +3029,7 @@ __FBSDID("$FreeBSD$");
#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_MASTER_IRQ_CONTROL (1U << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29)
#define DE_SPRITEA_FLIP_DONE (1 << 28)
#define DE_PLANEB_FLIP_DONE (1 << 27)
@ -3553,7 +3553,7 @@ __FBSDID("$FreeBSD$");
/* or SDVOB */
#define HDMIB 0xe1140
#define PORT_ENABLE (1 << 31)
#define PORT_ENABLE (1U << 31)
#define TRANSCODER(pipe) ((pipe) << 30)
#define TRANSCODER_CPT(pipe) ((pipe) << 29)
#define TRANSCODER_MASK (1 << 30)
@ -3583,13 +3583,13 @@ __FBSDID("$FreeBSD$");
#define LVDS_DETECTED (1 << 1)
#define BLC_PWM_CPU_CTL2 0x48250
#define PWM_ENABLE (1 << 31)
#define PWM_ENABLE (1U << 31)
#define PWM_PIPE_A (0 << 29)
#define PWM_PIPE_B (1 << 29)
#define BLC_PWM_CPU_CTL 0x48254
#define BLC_PWM_PCH_CTL1 0xc8250
#define PWM_PCH_ENABLE (1 << 31)
#define PWM_PCH_ENABLE (1U << 31)
#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)

4
sys/dev/drm2/radeon/evergreen_blit_kms.c
View File

@ -241,12 +241,12 @@ set_scissors(struct radeon_device *rdev, int x1, int y1,
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
}

12
sys/dev/drm2/radeon/evergreen_cs.c
View File

@ -2949,7 +2949,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
switch (misc) {
case 0:
/* L2T, frame to fields */
if (idx_value & (1 << 31)) {
if (idx_value & (1U << 31)) {
DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
return -EINVAL;
}
@ -2992,7 +2992,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
return -EINVAL;
}
/* detile bit */
if (idx_value & (1 << 31)) {
if (idx_value & (1U << 31)) {
/* tiled src, linear dst */
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
@ -3009,7 +3009,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
break;
case 3:
/* L2T, broadcast */
if (idx_value & (1 << 31)) {
if (idx_value & (1U << 31)) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
@ -3048,7 +3048,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
case 4:
/* L2T, T2L */
/* detile bit */
if (idx_value & (1 << 31)) {
if (idx_value & (1U << 31)) {
/* tiled src, linear dst */
src_offset = radeon_get_ib_value(p, idx+1);
src_offset <<= 8;
@ -3093,7 +3093,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
break;
case 7:
/* L2T, broadcast */
if (idx_value & (1 << 31)) {
if (idx_value & (1U << 31)) {
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
@ -3137,7 +3137,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
switch (misc) {
case 0:
/* detile bit */
if (idx_value & (1 << 31)) {
if (idx_value & (1U << 31)) {
/* tiled src, linear dst */
src_offset = radeon_get_ib_value(p, idx+1);
src_offset <<= 8;

22
sys/dev/drm2/radeon/evergreend.h
View File

@ -61,7 +61,7 @@ __FBSDID("$FreeBSD$");
#define INSTANCE_INDEX(x) ((x) << 0)
#define SE_INDEX(x) ((x) << 16)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
#define SE_BROADCAST_WRITES (1 << 31)
#define SE_BROADCAST_WRITES (1U << 31)
#define RLC_GFX_INDEX 0x3fC4
#define CC_GC_SHADER_PIPE_CONFIG 0x8950
#define WRITE_DIS (1 << 0)
@ -125,7 +125,7 @@ __FBSDID("$FreeBSD$");
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
#define RB_RPTR_WR_ENA (1 << 31)
#define RB_RPTR_WR_ENA (1U << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB_RPTR 0x8700
#define CP_RB_RPTR_ADDR 0xC10C
@ -187,7 +187,7 @@ __FBSDID("$FreeBSD$");
# define HDMI_ACR_X1 1
# define HDMI_ACR_X2 2
# define HDMI_ACR_X4 4
# define HDMI_ACR_AUDIO_PRIORITY (1 << 31)
# define HDMI_ACR_AUDIO_PRIORITY (1U << 31)
#define HDMI_VBI_PACKET_CONTROL 0x7040
# define HDMI_NULL_SEND (1 << 0)
# define HDMI_GC_SEND (1 << 4)
@ -322,7 +322,7 @@ __FBSDID("$FreeBSD$");
# define AFMT_AUDIO_CRC_EN (1 << 0)
#define AFMT_RAMP_CONTROL0 0x7110
# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
# define AFMT_RAMP_DATA_SIGN (1 << 31)
# define AFMT_RAMP_DATA_SIGN (1U << 31)
#define AFMT_RAMP_CONTROL1 0x7114
# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
@ -406,7 +406,7 @@ __FBSDID("$FreeBSD$");
# define PIN1_AUDIO_ENABLED (1 << 25)
# define PIN2_AUDIO_ENABLED (1 << 26)
# define PIN3_AUDIO_ENABLED (1 << 27)
# define AUDIO_ENABLED (1 << 31)
# define AUDIO_ENABLED (1U << 31)
#define GC_USER_SHADER_PIPE_CONFIG 0x8954
@ -452,7 +452,7 @@ __FBSDID("$FreeBSD$");
#define CP_COHERENCY_BUSY (1 << 28)
#define CP_BUSY (1 << 29)
#define CB_BUSY (1 << 30)
#define GUI_ACTIVE (1 << 31)
#define GUI_ACTIVE (1U << 31)
#define GRBM_STATUS_SE0 0x8014
#define GRBM_STATUS_SE1 0x8018
#define SE_SX_CLEAN (1 << 0)
@ -464,7 +464,7 @@ __FBSDID("$FreeBSD$");
#define SE_SH_BUSY (1 << 28)
#define SE_SC_BUSY (1 << 29)
#define SE_DB_BUSY (1 << 30)
#define SE_CB_BUSY (1 << 31)
#define SE_CB_BUSY (1U << 31)
/* evergreen */
#define CG_THERMAL_CTRL 0x72c
#define TOFFSET_MASK 0x00003FE0
@ -771,7 +771,7 @@ __FBSDID("$FreeBSD$");
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
# define IH_WPTR_OVERFLOW_CLEAR (1U << 31)
#define IH_RB_BASE 0x3e04
#define IH_RB_RPTR 0x3e08
#define IH_RB_WPTR 0x3e0c
@ -797,13 +797,13 @@ __FBSDID("$FreeBSD$");
# define TIME_STAMP_INT_ENABLE (1 << 26)
# define IB2_INT_ENABLE (1 << 29)
# define IB1_INT_ENABLE (1 << 30)
# define RB_INT_ENABLE (1 << 31)
# define RB_INT_ENABLE (1U << 31)
#define CP_INT_STATUS 0xc128
# define SCRATCH_INT_STAT (1 << 25)
# define TIME_STAMP_INT_STAT (1 << 26)
# define IB2_INT_STAT (1 << 29)
# define IB1_INT_STAT (1 << 30)
# define RB_INT_STAT (1 << 31)
# define RB_INT_STAT (1U << 31)
#define GRBM_INT_CNTL 0x8060
# define RDERR_INT_ENABLE (1 << 0)
@ -1062,7 +1062,7 @@ __FBSDID("$FreeBSD$");
* 1 - GDS
* 2 - DATA
*/
# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
# define PACKET3_CP_DMA_CP_SYNC (1U << 31)
/* COMMAND */
# define PACKET3_CP_DMA_DIS_WC (1 << 21)
# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)

10
sys/dev/drm2/radeon/nid.h
View File

@ -219,7 +219,7 @@ __FBSDID("$FreeBSD$");
#define CP_COHERENCY_BUSY (1 << 28)
#define CP_BUSY (1 << 29)
#define CB_BUSY (1 << 30)
#define GUI_ACTIVE (1 << 31)
#define GUI_ACTIVE (1U << 31)
#define GRBM_STATUS_SE0 0x8014
#define GRBM_STATUS_SE1 0x8018
#define SE_SX_CLEAN (1 << 0)
@ -233,7 +233,7 @@ __FBSDID("$FreeBSD$");
#define SE_SH_BUSY (1 << 28)
#define SE_SC_BUSY (1 << 29)
#define SE_DB_BUSY (1 << 30)
#define SE_CB_BUSY (1 << 31)
#define SE_CB_BUSY (1U << 31)
#define GRBM_SOFT_RESET 0x8020
#define SOFT_RESET_CP (1 << 0)
#define SOFT_RESET_CB (1 << 1)
@ -253,7 +253,7 @@ __FBSDID("$FreeBSD$");
#define INSTANCE_INDEX(x) ((x) << 0)
#define SE_INDEX(x) ((x) << 16)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
#define SE_BROADCAST_WRITES (1 << 31)
#define SE_BROADCAST_WRITES (1U << 31)
#define SCRATCH_REG0 0x8500
#define SCRATCH_REG1 0x8504
@ -442,7 +442,7 @@ __FBSDID("$FreeBSD$");
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
#define RB_RPTR_WR_ENA (1 << 31)
#define RB_RPTR_WR_ENA (1U << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB0_RPTR_ADDR 0xC10C
#define CP_RB0_RPTR_ADDR_HI 0xC110
@ -641,7 +641,7 @@ __FBSDID("$FreeBSD$");
#define DMA_IB_CNTL 0xd024
# define DMA_IB_ENABLE (1 << 0)
# define DMA_IB_SWAP_ENABLE (1 << 4)
# define CMD_VMID_FORCE (1 << 31)
# define CMD_VMID_FORCE (1U << 31)
#define DMA_IB_RPTR 0xd028
#define DMA_CNTL 0xd02c
# define TRAP_ENABLE (1 << 0)

2
sys/dev/drm2/radeon/r200.c
View File

@ -116,7 +116,7 @@ int r200_copy_dma(struct radeon_device *rdev,
radeon_ring_write(ring, PACKET0(0x720, 2));
radeon_ring_write(ring, src_offset);
radeon_ring_write(ring, dst_offset);
radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30));
radeon_ring_write(ring, cur_size | (1U << 31) | (1 << 30));
src_offset += cur_size;
dst_offset += cur_size;
}

2
sys/dev/drm2/radeon/r300.c
View File

@ -1041,7 +1041,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->textures[i].height = tmp + 1;
tmp = (idx_value >> 26) & 0xF;
track->textures[i].num_levels = tmp;
tmp = idx_value & (1 << 31);
tmp = idx_value & (1U << 31);
track->textures[i].use_pitch = !!tmp;
tmp = (idx_value >> 22) & 0xF;
track->textures[i].txdepth = tmp;

6
sys/dev/drm2/radeon/r300_reg.h
View File

@ -1210,7 +1210,7 @@ __FBSDID("$FreeBSD$");
# define R300_FPI0_OUTC_FRC (9 << 23)
# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
# define R300_FPI0_OUTC_SAT (1 << 30)
# define R300_FPI0_INSERT_NOP (1 << 31)
# define R300_FPI0_INSERT_NOP (1U << 31)
#define R300_PFS_INSTR2_0 0x49C0
# define R300_FPI2_ARGA_SRC0C_X 0
@ -1257,7 +1257,7 @@ __FBSDID("$FreeBSD$");
# define R300_FPI2_OUTA_RCP (10 << 23)
# define R300_FPI2_OUTA_RSQ (11 << 23)
# define R300_FPI2_OUTA_SAT (1 << 30)
# define R300_FPI2_UNKNOWN_31 (1 << 31)
# define R300_FPI2_UNKNOWN_31 (1U << 31)
/* END: Fragment program instruction set */
/* Fog state and color */
@ -1460,7 +1460,7 @@ __FBSDID("$FreeBSD$");
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1U << 31)
#define R300_ZB_BW_CNTL 0x4f1c
# define R300_HIZ_DISABLE (0 << 0)

8
sys/dev/drm2/radeon/r500_reg.h
View File

@ -88,7 +88,7 @@ __FBSDID("$FreeBSD$");
# define R300_SUBPIXEL_1_12 (0 << 16)
# define R300_SUBPIXEL_1_16 (1 << 16)
#define R300_DST_PIPE_CONFIG 0x170c
# define R300_PIPE_AUTO_CONFIG (1 << 31)
# define R300_PIPE_AUTO_CONFIG (1U << 31)
#define R300_RB2D_DSTCACHE_MODE 0x3428
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
@ -148,7 +148,7 @@ __FBSDID("$FreeBSD$");
# define RS480_GTW_LAC_EN (1 << 25)
# define RS480_2LEVEL_GART (0 << 30)
# define RS480_1LEVEL_GART (1 << 30)
# define RS480_PDC_EN (1 << 31)
# define RS480_PDC_EN (1U << 31)
#define RS480_GART_BASE 0x2c
#define RS480_GART_CACHE_CNTRL 0x2e
# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
@ -639,7 +639,7 @@ __FBSDID("$FreeBSD$");
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31)
#define AVIVO_LVTMA_CNTL 0x7a80
# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
@ -705,7 +705,7 @@ __FBSDID("$FreeBSD$");
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31)
#define R500_LVTMA_PWRSEQ_CNTL 0x7af0
#define R600_LVTMA_PWRSEQ_CNTL 0x7af4

4
sys/dev/drm2/radeon/r600_blit.c
View File

@ -275,12 +275,12 @@ set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
OUT_RING((x2 << 0) | (y2 << 16));
OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
OUT_RING((x2 << 0) | (y2 << 16));
ADVANCE_RING();
}

4
sys/dev/drm2/radeon/r600_blit_kms.c
View File

@ -244,12 +244,12 @@ set_scissors(struct radeon_device *rdev, int x1, int y1,
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
}

2
sys/dev/drm2/radeon/r600_cs.c
View File

@ -2664,7 +2664,7 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
if (tiled) {
idx_value = radeon_get_ib_value(p, idx + 2);
/* detile bit */
if (idx_value & (1 << 31)) {
if (idx_value & (1U << 31)) {
/* tiled src, linear dst */
src_offset = radeon_get_ib_value(p, idx+1);
src_offset <<= 8;

16
sys/dev/drm2/radeon/r600d.h
View File

@ -204,7 +204,7 @@ __FBSDID("$FreeBSD$");
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
#define RB_RPTR_WR_ENA (1 << 31)
#define RB_RPTR_WR_ENA (1U << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB_RPTR 0x8700
#define CP_RB_RPTR_ADDR 0xC10C
@ -220,7 +220,7 @@ __FBSDID("$FreeBSD$");
#define CP_SEM_WAIT_TIMER 0x85BC
#define DB_DEBUG 0x9830
#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31)
#define DB_DEPTH_BASE 0x2800C
#define DB_HTILE_DATA_BASE 0x28014
#define DB_HTILE_SURFACE 0x28D24
@ -507,7 +507,7 @@ __FBSDID("$FreeBSD$");
#define SYNC_WALKER (1 << 25)
#define SYNC_ALIGNER (1 << 26)
#define BILINEAR_PRECISION_6_BIT (0 << 31)
#define BILINEAR_PRECISION_8_BIT (1 << 31)
#define BILINEAR_PRECISION_8_BIT (1U << 31)
#define TC_CNTL 0x9608
#define TC_L2_SIZE(x) ((x)<<5)
@ -650,7 +650,7 @@ __FBSDID("$FreeBSD$");
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
# define IH_WPTR_OVERFLOW_CLEAR (1U << 31)
#define IH_RB_BASE 0x3e04
#define IH_RB_RPTR 0x3e08
#define IH_RB_WPTR 0x3e0c
@ -701,13 +701,13 @@ __FBSDID("$FreeBSD$");
# define TIME_STAMP_INT_ENABLE (1 << 26)
# define IB2_INT_ENABLE (1 << 29)
# define IB1_INT_ENABLE (1 << 30)
# define RB_INT_ENABLE (1 << 31)
# define RB_INT_ENABLE (1U << 31)
#define CP_INT_STATUS 0xc128
# define SCRATCH_INT_STAT (1 << 25)
# define TIME_STAMP_INT_STAT (1 << 26)
# define IB2_INT_STAT (1 << 29)
# define IB1_INT_STAT (1 << 30)
# define RB_INT_STAT (1 << 31)
# define RB_INT_STAT (1U << 31)
#define GRBM_INT_CNTL 0x8060
# define RDERR_INT_ENABLE (1 << 0)
@ -914,7 +914,7 @@ __FBSDID("$FreeBSD$");
#define DCCG_AUDIO_DTO0_PHASE 0x0514
#define DCCG_AUDIO_DTO0_MODULE 0x0518
#define DCCG_AUDIO_DTO0_LOAD 0x051c
# define DTO_LOAD (1 << 31)
# define DTO_LOAD (1U << 31)
#define DCCG_AUDIO_DTO0_CNTL 0x0520
#define DCCG_AUDIO_DTO1_PHASE 0x0524
@ -1197,7 +1197,7 @@ __FBSDID("$FreeBSD$");
* 5. DST_ADDR_HI [7:0]
* 6. COMMAND [29:22] | BYTE_COUNT [20:0]
*/
# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
# define PACKET3_CP_DMA_CP_SYNC (1U << 31)
/* COMMAND */
# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
/* 0 - none

2
sys/dev/drm2/radeon/radeon_cp.c
View File

@ -564,7 +564,7 @@ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
#if 0
u32 tmp;
tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1U << 31);
RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
#endif
}

30
sys/dev/drm2/radeon/radeon_drv.h
View File

@ -572,7 +572,7 @@ void radeon_unregister_atpx_handler(void);
# define RS480_GTW_LAC_EN (1 << 25)
# define RS480_2LEVEL_GART (0 << 30)
# define RS480_1LEVEL_GART (1 << 30)
# define RS480_PDC_EN (1 << 31)
# define RS480_PDC_EN (1U << 31)
#define RS480_GART_BASE 0x2c
#define RS480_GART_CACHE_CNTRL 0x2e
# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
@ -688,7 +688,7 @@ void radeon_unregister_atpx_handler(void);
# define R300_SUBPIXEL_1_12 (0 << 16)
# define R300_SUBPIXEL_1_16 (1 << 16)
#define R300_DST_PIPE_CONFIG 0x170c
# define R300_PIPE_AUTO_CONFIG (1 << 31)
# define R300_PIPE_AUTO_CONFIG (1U << 31)
#define R300_RB2D_DSTCACHE_MODE 0x3428
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
@ -815,7 +815,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R300_RB2D_DC_FLUSH (3 << 0)
# define R300_RB2D_DC_FREE (3 << 2)
# define R300_RB2D_DC_FLUSH_ALL 0xf
# define R300_RB2D_DC_BUSY (1 << 31)
# define R300_RB2D_DC_BUSY (1U << 31)
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
@ -837,16 +837,16 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_RB3D_ZC_FLUSH (1 << 0)
# define RADEON_RB3D_ZC_FREE (1 << 2)
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
# define RADEON_RB3D_ZC_BUSY (1 << 31)
# define RADEON_RB3D_ZC_BUSY (1U << 31)
#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
# define R300_ZC_BUSY (1 << 31)
# define R300_ZC_BUSY (1U << 31)
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
# define RADEON_RB3D_DC_BUSY (1 << 31)
# define RADEON_RB3D_DC_BUSY (1U << 31)
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FLUSH (2 << 0)
# define R300_RB3D_DC_FREE (2 << 2)
@ -862,7 +862,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
@ -916,7 +916,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
# define RADEON_GA_BUSY (1 << 26)
# define RADEON_CBA2D_BUSY (1 << 27)
# define RADEON_RBBM_ACTIVE (1 << 31)
# define RADEON_RBBM_ACTIVE (1U << 31)
#define RADEON_RE_LINE_PATTERN 0x1cd0
#define RADEON_RE_MISC 0x26c4
#define RADEON_RE_TOP_LEFT 0x26c0
@ -1030,7 +1030,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define RADEON_CP_RB_CNTL 0x0704
# define RADEON_BUF_SWAP_32BIT (2 << 16)
# define RADEON_RB_NO_UPDATE (1 << 27)
# define RADEON_RB_RPTR_WR_ENA (1 << 31)
# define RADEON_RB_RPTR_WR_ENA (1U << 31)
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
@ -1166,7 +1166,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
#define RADEON_VTX_Z_PRESENT (1 << 31)
#define RADEON_VTX_Z_PRESENT (1U << 31)
#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
#define RADEON_PRIM_TYPE_NONE (0 << 0)
@ -1497,7 +1497,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define R600_GRBM_STATUS 0x8010
# define R600_CMDFIFO_AVAIL_MASK 0x1f
# define R700_CMDFIFO_AVAIL_MASK 0xf
# define R600_GUI_ACTIVE (1 << 31)
# define R600_GUI_ACTIVE (1U << 31)
#define R600_GRBM_STATUS2 0x8014
#define R600_GRBM_SOFT_RESET 0x8020
# define R600_SOFT_RESET_CP (1 << 0)
@ -1520,7 +1520,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_RB_BLKSZ(x) ((x) << 8)
# define R600_BUF_SWAP_32BIT (2 << 16)
# define R600_RB_NO_UPDATE (1 << 27)
# define R600_RB_RPTR_WR_ENA (1 << 31)
# define R600_RB_RPTR_WR_ENA (1U << 31)
#define R600_CP_RB_RPTR_WR 0xc108
#define R600_CP_RB_RPTR_ADDR 0xc10c
#define R600_CP_RB_RPTR_ADDR_HI 0xc110
@ -1593,7 +1593,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define R600_SX_MISC 0x28350
#define R600_DB_DEBUG 0x9830
# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31)
#define R600_DB_WATERMARKS 0x9838
# define R600_DEPTH_FREE(x) ((x) << 0)
# define R600_DEPTH_FLUSH(x) ((x) << 5)
@ -1699,7 +1699,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_SYNC_WALKER (1 << 25)
# define R600_SYNC_ALIGNER (1 << 26)
# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
# define R600_BILINEAR_PRECISION_8_BIT (1U << 31)
#define R700_TCP_CNTL 0x9610
@ -1773,7 +1773,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_PERSP_GRADIENT_ENA (1 << 28)
# define R600_LINEAR_GRADIENT_ENA (1 << 29)
# define R600_POSITION_SAMPLE (1 << 30)
# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
# define R600_BARYC_AT_SAMPLE_ENA (1U << 31)
#define R600_SPI_PS_IN_CONTROL_1 0x286d0
# define R600_GEN_INDEX_PIX (1 << 0)
# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)

36
sys/dev/drm2/radeon/radeon_reg.h
View File

@ -361,7 +361,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
# define RADEON_DYN_STOP_MODE_MASK (7 << 21)
# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
# define RADEON_TVCLK_TURNOFF (1 << 31)
# define RADEON_TVCLK_TURNOFF (1U << 31)
#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */
# define RADEON_PM_MODE_SEL (1 << 13)
# define RADEON_TCL_BYPASS_DISABLE (1 << 20)
@ -585,13 +585,13 @@ __FBSDID("$FreeBSD$");
#define RADEON_CUR_HORZ_VERT_OFF 0x0268
#define RADEON_CUR_HORZ_VERT_POSN 0x0264
#define RADEON_CUR_OFFSET 0x0260
# define RADEON_CUR_LOCK (1 << 31)
# define RADEON_CUR_LOCK (1U << 31)
#define RADEON_CUR2_CLR0 0x036c
#define RADEON_CUR2_CLR1 0x0370
#define RADEON_CUR2_HORZ_VERT_OFF 0x0368
#define RADEON_CUR2_HORZ_VERT_POSN 0x0364
#define RADEON_CUR2_OFFSET 0x0360
# define RADEON_CUR2_LOCK (1 << 31)
# define RADEON_CUR2_LOCK (1U << 31)
#define RADEON_DAC_CNTL 0x0058
# define RADEON_DAC_RANGE_CNTL (3 << 0)
@ -670,7 +670,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TV_DAC_BDACPD (1 << 26)
# define RADEON_TV_DAC_RDACDET (1 << 29)
# define RADEON_TV_DAC_GDACDET (1 << 30)
# define RADEON_TV_DAC_BDACDET (1 << 31)
# define RADEON_TV_DAC_BDACDET (1U << 31)
# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
# define R420_TV_DAC_RDACPD (1 << 25)
# define R420_TV_DAC_GDACPD (1 << 26)
@ -745,7 +745,7 @@ __FBSDID("$FreeBSD$");
#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
# define RADEON_DST_Y_MAJOR (1 << 2)
# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1U << 31)
#define RADEON_DP_DATATYPE 0x16c4
# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
#define RADEON_DP_GUI_MASTER_CNTL 0x146c
@ -1230,7 +1230,7 @@ __FBSDID("$FreeBSD$");
#define RADEON_MIN_GRANT 0x0f3e /* PCI */
#define RADEON_MM_DATA 0x0004
#define RADEON_MM_INDEX 0x0000
# define RADEON_MM_APER (1 << 31)
# define RADEON_MM_APER (1U << 31)
#define RADEON_MPLL_CNTL 0x000e /* PLL */
#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
@ -1600,12 +1600,12 @@ __FBSDID("$FreeBSD$");
# define RADEON_SOFT_RESET_HDP (1 << 7)
#define RADEON_RBBM_STATUS 0x0e40
# define RADEON_RBBM_FIFOCNT_MASK 0x007f
# define RADEON_RBBM_ACTIVE (1 << 31)
# define RADEON_RBBM_ACTIVE (1U << 31)
#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
# define RADEON_RB2D_DC_FLUSH (3 << 0)
# define RADEON_RB2D_DC_FREE (3 << 2)
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
# define RADEON_RB2D_DC_BUSY (1 << 31)
# define RADEON_RB2D_DC_BUSY (1U << 31)
#define RADEON_RB2D_DSTCACHE_MODE 0x3428
#define RADEON_DSTCACHE_CTLSTAT 0x1714
@ -1631,7 +1631,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
# define RADEON_RB3D_DC_BUSY (1 << 31)
# define RADEON_RB3D_DC_BUSY (1U << 31)
#define RADEON_REG_BASE 0x0f18 /* PCI */
#define RADEON_REGPROG_INF 0x0f09 /* PCI */
@ -1854,7 +1854,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_WAIT_VAP_IDLE (1 << 28)
# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)
# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)
# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)
# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1U << 31)
#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
#define RADEON_XCLK_CNTL 0x000d /* PLL */
@ -1896,7 +1896,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_BUMPED_MAP_T2 (2 << 27)
# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
# define RADEON_MC_ENABLE (1 << 31)
# define RADEON_MC_ENABLE (1U << 31)
#define RADEON_PP_FOG_COLOR 0x1c18
# define RADEON_FOG_COLOR_MASK 0x00ffffff
# define RADEON_FOG_VERTEX (0 << 24)
@ -2091,7 +2091,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TEX_VSIZE_SHIFT 16
# define RADEON_SIGNED_RGB_MASK (1 << 30)
# define RADEON_SIGNED_RGB_SHIFT 30
# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
# define RADEON_SIGNED_ALPHA_MASK (1U << 31)
# define RADEON_SIGNED_ALPHA_SHIFT 31
#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
@ -2558,7 +2558,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TCL_VTX_Z1 (1 << 28)
# define RADEON_TCL_VTX_W1 (1 << 29)
# define RADEON_TCL_VTX_NORM1 (1 << 30)
# define RADEON_TCL_VTX_Z0 (1 << 31)
# define RADEON_TCL_VTX_Z0 (1U << 31)
#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
# define RADEON_TCL_COMPUTE_XYZW (1 << 0)
@ -2667,7 +2667,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_CULL_FRONT_IS_CCW (1 << 28)
# define RADEON_CULL_FRONT (1 << 29)
# define RADEON_CULL_BACK (1 << 30)
# define RADEON_FORCE_W_TO_ONE (1 << 31)
# define RADEON_FORCE_W_TO_ONE (1U << 31)
#define RADEON_SE_VPORT_XSCALE 0x1d98
#define RADEON_SE_VPORT_XOFFSET 0x1d9c
@ -3306,7 +3306,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_MAX_FETCH_SHIFT 18
# define RADEON_MAX_FETCH_MASK (0x3 << 18)
# define RADEON_RB_NO_UPDATE (1 << 27)
# define RADEON_RB_RPTR_WR_ENA (1 << 31)
# define RADEON_RB_RPTR_WR_ENA (1U << 31)
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
@ -3320,7 +3320,7 @@ __FBSDID("$FreeBSD$");
# define R600_RB_BUFSZ(x) ((x) << 0)
# define R600_RB_BLKSZ(x) ((x) << 8)
# define R600_RB_NO_UPDATE (1 << 27)
# define R600_RB_RPTR_WR_ENA (1 << 31)
# define R600_RB_RPTR_WR_ENA (1U << 31)
#define R600_CP_RB_RPTR_WR 0xc108
#define R600_CP_RB_RPTR_ADDR 0xc10c
#define R600_CP_RB_RPTR_ADDR_HI 0xc110
@ -3519,7 +3519,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TV_FIFO_CE_EN (1 << 10)
# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)
# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
# define RADEON_TV_ON (1 << 31)
# define RADEON_TV_ON (1U << 31)
#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
# define RADEON_Y_RED_EN (1 << 0)
# define RADEON_C_GRN_EN (1 << 1)
@ -3651,7 +3651,7 @@ __FBSDID("$FreeBSD$");
# define RADEON_TVPVG_MASK (7 << 11)
# define RADEON_TVPDC_SHIFT 14
# define RADEON_TVPDC_MASK (3 << 14)
# define RADEON_TVPLL_TEST_DIS (1 << 31)
# define RADEON_TVPLL_TEST_DIS (1U << 31)
# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
#define RS400_DISP2_REQ_CNTL1 0xe30

8
sys/dev/drm2/radeon/rv770d.h
View File

@ -82,7 +82,7 @@ __FBSDID("$FreeBSD$");
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
#define RB_RPTR_WR_ENA (1 << 31)
#define RB_RPTR_WR_ENA (1U << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB_RPTR 0x8700
#define CP_RB_RPTR_ADDR 0xC10C
@ -312,7 +312,7 @@ __FBSDID("$FreeBSD$");
#define SYNC_WALKER (1 << 25)
#define SYNC_ALIGNER (1 << 26)
#define BILINEAR_PRECISION_6_BIT (0 << 31)
#define BILINEAR_PRECISION_8_BIT (1 << 31)
#define BILINEAR_PRECISION_8_BIT (1U << 31)
#define TCP_CNTL 0x9610
#define TCP_CHAN_STEER 0x9614
@ -537,7 +537,7 @@ __FBSDID("$FreeBSD$");
# define AFMT_AUDIO_CRC_EN (1 << 0)
#define AFMT_RAMP_CONTROL0 0x74e0
# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
# define AFMT_RAMP_DATA_SIGN (1 << 31)
# define AFMT_RAMP_DATA_SIGN (1U << 31)
#define AFMT_RAMP_CONTROL1 0x74e4
# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
@ -622,7 +622,7 @@ __FBSDID("$FreeBSD$");
# define PIN1_AUDIO_ENABLED (1 << 25)
# define PIN2_AUDIO_ENABLED (1 << 26)
# define PIN3_AUDIO_ENABLED (1 << 27)
# define AUDIO_ENABLED (1 << 31)
# define AUDIO_ENABLED (1U << 31)
#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110

18
sys/dev/drm2/radeon/sid.h
View File

@ -199,7 +199,7 @@ __FBSDID("$FreeBSD$");
#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
#define TRAIN_DONE_D0 (1 << 30)
#define TRAIN_DONE_D1 (1 << 31)
#define TRAIN_DONE_D1 (1U << 31)
#define MC_SEQ_SUP_CNTL 0x28c8
#define RUN_MASK (1 << 0)
@ -227,7 +227,7 @@ __FBSDID("$FreeBSD$");
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
# define IH_WPTR_OVERFLOW_CLEAR (1U << 31)
#define IH_RB_BASE 0x3e04
#define IH_RB_RPTR 0x3e08
#define IH_RB_WPTR 0x3e0c
@ -414,7 +414,7 @@ __FBSDID("$FreeBSD$");
#define CP_COHERENCY_BUSY (1 << 28)
#define CP_BUSY (1 << 29)
#define CB_BUSY (1 << 30)
#define GUI_ACTIVE (1 << 31)
#define GUI_ACTIVE (1U << 31)
#define GRBM_STATUS_SE0 0x8014
#define GRBM_STATUS_SE1 0x8018
#define SE_DB_CLEAN (1 << 1)
@ -427,7 +427,7 @@ __FBSDID("$FreeBSD$");
#define SE_SPI_BUSY (1 << 27)
#define SE_SC_BUSY (1 << 29)
#define SE_DB_BUSY (1 << 30)
#define SE_CB_BUSY (1 << 31)
#define SE_CB_BUSY (1U << 31)
#define GRBM_SOFT_RESET 0x8020
#define SOFT_RESET_CP (1 << 0)
@ -451,7 +451,7 @@ __FBSDID("$FreeBSD$");
#define SE_INDEX(x) ((x) << 16)
#define SH_BROADCAST_WRITES (1 << 29)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
#define SE_BROADCAST_WRITES (1 << 31)
#define SE_BROADCAST_WRITES (1U << 31)
#define GRBM_INT_CNTL 0x8060
# define RDERR_INT_ENABLE (1 << 0)
@ -672,7 +672,7 @@ __FBSDID("$FreeBSD$");
#define RB_BLKSZ(x) ((x) << 8)
#define BUF_SWAP_32BIT (2 << 16)
#define RB_NO_UPDATE (1 << 27)
#define RB_RPTR_WR_ENA (1 << 31)
#define RB_RPTR_WR_ENA (1U << 31)
#define CP_RB0_RPTR_ADDR 0xC10C
#define CP_RB0_RPTR_ADDR_HI 0xC110
@ -706,7 +706,7 @@ __FBSDID("$FreeBSD$");
# define TIME_STAMP_INT_ENABLE (1 << 26)
# define CP_RINGID2_INT_ENABLE (1 << 29)
# define CP_RINGID1_INT_ENABLE (1 << 30)
# define CP_RINGID0_INT_ENABLE (1 << 31)
# define CP_RINGID0_INT_ENABLE (1U << 31)
#define CP_INT_STATUS_RING0 0xC1B4
#define CP_INT_STATUS_RING1 0xC1B8
#define CP_INT_STATUS_RING2 0xC1BC
@ -714,7 +714,7 @@ __FBSDID("$FreeBSD$");
# define TIME_STAMP_INT_STAT (1 << 26)
# define CP_RINGID2_INT_STAT (1 << 29)
# define CP_RINGID1_INT_STAT (1 << 30)
# define CP_RINGID0_INT_STAT (1 << 31)
# define CP_RINGID0_INT_STAT (1U << 31)
#define CP_DEBUG 0xC1FC
@ -890,7 +890,7 @@ __FBSDID("$FreeBSD$");
* 1 - GDS
* 2 - DATA
*/
# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
# define PACKET3_CP_DMA_CP_SYNC (1U << 31)
/* COMMAND */
# define PACKET3_CP_DMA_DIS_WC (1 << 21)
# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)

6
sys/dev/drm2/ttm/ttm_bo.c
View File

@ -216,7 +216,7 @@ int ttm_bo_reserve_nolru(struct ttm_buffer_object *bo,
* Already reserved by a thread that will not back
* off for us. We need to back off.
*/
if (unlikely(sequence - bo->val_seq < (1 << 31)))
if (unlikely(sequence - bo->val_seq < (1U << 31)))
return -EAGAIN;
}
@ -235,7 +235,7 @@ int ttm_bo_reserve_nolru(struct ttm_buffer_object *bo,
* Wake up waiters that may need to recheck for deadlock,
* if we decreased the sequence number.
*/
if (unlikely((bo->val_seq - sequence < (1 << 31))
if (unlikely((bo->val_seq - sequence < (1U << 31))
|| !bo->seq_valid))
wake_up = true;
@ -313,7 +313,7 @@ int ttm_bo_reserve_slowpath_nolru(struct ttm_buffer_object *bo,
return ret;
}
if ((bo->val_seq - sequence < (1 << 31)) || !bo->seq_valid)
if ((bo->val_seq - sequence < (1U << 31)) || !bo->seq_valid)
wake_up = true;
/**

4
sys/dev/e1000/e1000_82575.h
View File

@ -384,7 +384,7 @@ struct e1000_adv_tx_context_desc {
#define E1000_ETQF_FILTER_ENABLE (1 << 26)
#define E1000_ETQF_IMM_INT (1 << 29)
#define E1000_ETQF_1588 (1 << 30)
#define E1000_ETQF_QUEUE_ENABLE (1 << 31)
#define E1000_ETQF_QUEUE_ENABLE (1U << 31)
/*
* ETQF filter list: one static filter per filter consumer. This is
* to avoid filter collisions later. Add new filters
@ -411,7 +411,7 @@ struct e1000_adv_tx_context_desc {
#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
#define E1000_DTXSWC_LLE_SHIFT 16
#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1U << 31) /* global VF LB enable */
/* Easy defines for setting default pool, would normally be left a zero */
#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7

2
sys/dev/e1000/e1000_ich8lan.c
View File

@ -4149,7 +4149,7 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
/* Device Status */
if (hw->mac.type == e1000_ich8lan) {
reg = E1000_READ_REG(hw, E1000_STATUS);
reg &= ~(1 << 31);
reg &= ~(1U << 31);
E1000_WRITE_REG(hw, E1000_STATUS, reg);
}

2
sys/dev/e1000/e1000_regs.h
View File

@ -207,7 +207,7 @@
/* QAV Tx mode control register bitfields masks */
#define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */
#define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */
#define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */
#define E1000_TQAVCC_QUEUE_MODE (1U << 31) /* SP vs. SR Tx mode */
/* Good transmitted packets counter registers */
#define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n)))

12
sys/dev/etherswitch/arswitch/arswitchreg.h
View File

@ -46,7 +46,7 @@
#define AR8X16_MASK_CTRL_REV_MASK 0x000000ff
#define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00
#define AR8X16_MASK_CTRL_VER_SHIFT 8
#define AR8X16_MASK_CTRL_SOFT_RESET (1 << 31)
#define AR8X16_MASK_CTRL_SOFT_RESET (1U << 31)
#define AR8X16_REG_MODE 0x0008
/* DIR-615 E4 U-Boot */
@ -111,7 +111,7 @@
#define AR8X16_VLAN_VID_SHIFT 16
#define AR8X16_VLAN_PRIO 0x70000000
#define AR8X16_VLAN_PRIO_SHIFT 28
#define AR8X16_VLAN_PRIO_EN (1 << 31)
#define AR8X16_VLAN_PRIO_EN (1U << 31)
#define AR8X16_REG_VLAN_DATA 0x0044
#define AR8X16_VLAN_MEMBER 0x0000003f
@ -162,7 +162,7 @@
#define AR8X16_MDIO_CTRL_CMD_WRITE 0
#define AR8X16_MDIO_CTRL_CMD_READ (1 << 27)
#define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30)
#define AR8X16_MDIO_CTRL_BUSY (1 << 31)
#define AR8X16_MDIO_CTRL_BUSY (1U << 31)
#define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100)
@ -376,7 +376,7 @@
#define AR8327_PAD_RGMII_EN (1 << 26)
#define AR8327_REG_POWER_ON_STRIP 0x010
#define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1 << 31)
#define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1U << 31)
#define AR8327_POWER_ON_STRIP_LED_OPEN_EN (1 << 24)
#define AR8327_POWER_ON_STRIP_SERDES_AEN (1 << 7)
@ -444,7 +444,7 @@
#define AR8327_ATU_FUNC_OP_GET_NEXT 0x6
#define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7
#define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8
#define AR8327_ATU_FUNC_BUSY (1 << 31)
#define AR8327_ATU_FUNC_BUSY (1U << 31)
#define AR8327_REG_VTU_FUNC0 0x0610
#define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14)
@ -470,7 +470,7 @@
#define AR8327_VTU_FUNC1_PORT_S 8
#define AR8327_VTU_FUNC1_VID (1 << 16, 12)
#define AR8327_VTU_FUNC1_VID_S 16
#define AR8327_VTU_FUNC1_BUSY (1 << 31)
#define AR8327_VTU_FUNC1_BUSY (1U << 31)
#define AR8327_REG_FWD_CTRL0 0x620
#define AR8327_FWD_CTRL0_CPU_PORT_EN (1 << 10)

10
sys/dev/ffec/if_ffecreg.h
View File

@ -40,7 +40,7 @@ __FBSDID("$FreeBSD$");
*/
#define FEC_IER_REG 0x0004
#define FEC_IEM_REG 0x0008
#define FEC_IER_HBERR (1 << 31)
#define FEC_IER_HBERR (1U << 31)
#define FEC_IER_BABR (1 << 30)
#define FEC_IER_BABT (1 << 29)
#define FEC_IER_GRA (1 << 28)
@ -98,12 +98,12 @@ __FBSDID("$FreeBSD$");
#define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT)
#define FEC_MIBC_REG 0x0064
#define FEC_MIBC_DIS (1 << 31)
#define FEC_MIBC_DIS (1U << 31)
#define FEC_MIBC_IDLE (1 << 30)
#define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */
#define FEC_RCR_REG 0x0084
#define FEC_RCR_GRS (1 << 31)
#define FEC_RCR_GRS (1U << 31)
#define FEC_RCR_NLC (1 << 30)
#define FEC_RCR_MAX_FL_SHIFT 16
#define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT)
@ -265,7 +265,7 @@ struct ffec_hwdesc
uint32_t buf_paddr;
};
#define FEC_TXDESC_READY (1 << 31)
#define FEC_TXDESC_READY (1U << 31)
#define FEC_TXDESC_T01 (1 << 30)
#define FEC_TXDESC_WRAP (1 << 29)
#define FEC_TXDESC_T02 (1 << 28)
@ -274,7 +274,7 @@ struct ffec_hwdesc
#define FEC_TXDESC_ABC (1 << 25)
#define FEC_TXDESC_LEN_MASK (0xffff)
#define FEC_RXDESC_EMPTY (1 << 31)
#define FEC_RXDESC_EMPTY (1U << 31)
#define FEC_RXDESC_R01 (1 << 30)
#define FEC_RXDESC_WRAP (1 << 29)
#define FEC_RXDESC_R02 (1 << 28)

2
sys/dev/firewire/firewire.c
View File

@ -649,7 +649,7 @@ fw_reset_csr(struct firewire_comm *fc)
CSRARC(fc, BANDWIDTH_AV) = 4915;
CSRARC(fc, CHANNELS_AV_HI) = 0xffffffff;
CSRARC(fc, CHANNELS_AV_LO) = 0xffffffff;
CSRARC(fc, IP_CHANNELS) = (1 << 31);
CSRARC(fc, IP_CHANNELS) = (1U << 31);
CSRARC(fc, CONF_ROM) = 0x04 << 24;
CSRARC(fc, CONF_ROM + 4) = 0x31333934; /* means strings 1394 */

4
sys/dev/firewire/fwohci.c
View File

@ -179,7 +179,7 @@ static void fwohci_task_dma(void *, int);
#define OHCI_ATRETRY 0x08
#define OHCI_CROMHDR 0x18
#define OHCI_BUS_OPT 0x20
#define OHCI_BUSIRMC (1 << 31)
#define OHCI_BUSIRMC (1U << 31)
#define OHCI_BUSCMC (1 << 30)
#define OHCI_BUSISC (1 << 29)
#define OHCI_BUSBMC (1 << 28)
@ -205,7 +205,7 @@ static void fwohci_task_dma(void *, int);
#define OHCI_SID_BUF 0x64
#define OHCI_SID_CNT 0x68
#define OHCI_SID_ERR (1 << 31)
#define OHCI_SID_ERR (1U << 31)
#define OHCI_SID_CNT_MASK 0xffc
#define OHCI_IT_STAT 0x90

4
sys/dev/firewire/fwohcireg.h
View File

@ -241,7 +241,7 @@ struct ohci_registers {
fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */
#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */
#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */
#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */
#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */
@ -280,7 +280,7 @@ struct ohci_registers {
fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/
#define FWOHCI_NODEID 0xe8
fwohcireg_t node; /* Node ID 0xe8 */
#define OHCI_NODE_VALID (1 << 31)
#define OHCI_NODE_VALID (1U << 31)
#define OHCI_NODE_ROOT (1 << 30)
#define OHCI_ASYSRCBUS 1

2
sys/dev/firewire/sbp.c
View File

@ -2472,7 +2472,7 @@ END_DEBUG
ocb->sdev = sdev;
ocb->ccb = ccb;
ccb->ccb_h.ccb_sdev_ptr = sdev;
ocb->orb[0] = htonl(1 << 31);
ocb->orb[0] = htonl(1U << 31);
ocb->orb[1] = 0;
ocb->orb[2] = htonl(((sbp->fd.fc->nodeid | FWLOCALBUS )<< 16) );
ocb->orb[3] = htonl(ocb->bus_addr + IND_PTR_OFFSET);

2
sys/dev/firewire/sbp.h
View File

@ -35,7 +35,7 @@
*
*/
#define ORB_NOTIFY (1 << 31)
#define ORB_NOTIFY (1U << 31)
#define ORB_FMT_STD (0 << 29)
#define ORB_FMT_VED (2 << 29)
#define ORB_FMT_NOP (3 << 29)

2
sys/dev/firewire/sbp_targ.c
View File

@ -1716,7 +1716,7 @@ sbp_targ_pointer_handler(struct fw_xfer *xfer)
orb0 = ntohl(orbi->orb[0]);
orb1 = ntohl(orbi->orb[1]);
if ((orb0 & (1 << 31)) != 0) {
if ((orb0 & (1U << 31)) != 0) {
printf("%s: invalid pointer\n", __func__);
goto done;
}

4
sys/dev/hatm/if_hatmreg.h
View File

@ -444,7 +444,7 @@
#define HE_REGM_TSR3_CRM (0xff << 0)
#define HE_REGS_TSR3_CRM 0
#define HE_REGM_TSR4_FLUSH (1 << 31)
#define HE_REGM_TSR4_FLUSH (1U << 31)
#define HE_REGM_TSR4_SESS_END (1 << 30)
#define HE_REGM_TSR4_OAM_CRC10 (1 << 28)
#define HE_REGM_TSR4_NULL_CRC10 (1 << 27)
@ -475,7 +475,7 @@
#define HE_REGM_TSR13_CRM 0xffff
#define HE_REGS_TSR13_CRM 0
#define HE_REGM_TSR14_CBR_DELETE (1 << 31)
#define HE_REGM_TSR14_CBR_DELETE (1U << 31)
#define HE_REGM_TSR14_ABR_CLOSE (1 << 16)
/*

2
sys/dev/hwpmc/hwpmc_piv.h
View File

@ -39,7 +39,7 @@
#define P4_MAX_ESCR_PER_EVENT 2
#define P4_MAX_PMC_PER_ESCR 3
#define P4_CCCR_OVF (1 << 31)
#define P4_CCCR_OVF (1U << 31)
#define P4_CCCR_CASCADE (1 << 30)
#define P4_CCCR_OVF_PMI_T1 (1 << 27)
#define P4_CCCR_OVF_PMI_T0 (1 << 26)

16
sys/dev/iwn/if_iwnreg.h
View File

@ -200,7 +200,7 @@
#define IWN_RESET_SW (1 << 7)
#define IWN_RESET_MASTER_DISABLED (1 << 8)
#define IWN_RESET_STOP_MASTER (1 << 9)
#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31)
#define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31)
/* Possible flags for register IWN_GP_CNTRL. */
#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0)
@ -265,7 +265,7 @@ static const struct {
/* Possible flags for register IWN_DRAM_INT_TBL. */
#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27)
#define IWN_DRAM_INT_TBL_ENABLE (1 << 31)
#define IWN_DRAM_INT_TBL_ENABLE (1U << 31)
/* Possible values for register IWN_ANA_PLL. */
#define IWN_ANA_PLL_INIT 0x00880300
@ -275,7 +275,7 @@ static const struct {
/* Possible flags for register IWN_BSM_WR_CTRL. */
#define IWN_BSM_WR_CTRL_START_EN (1 << 30)
#define IWN_BSM_WR_CTRL_START (1 << 31)
#define IWN_BSM_WR_CTRL_START (1U << 31)
/* Possible flags for register IWN_INT. */
#define IWN_INT_ALIVE (1 << 0)
@ -288,7 +288,7 @@ static const struct {
#define IWN_INT_FH_TX (1 << 27)
#define IWN_INT_RX_PERIODIC (1 << 28)
#define IWN_INT_HW_ERR (1 << 29)
#define IWN_INT_FH_RX (1 << 31)
#define IWN_INT_FH_RX (1U << 31)
/* Shortcut. */
#define IWN_INT_MASK_DEF \
@ -308,7 +308,7 @@ static const struct {
/* Possible flags/values for register IWN_FH_TX_CONFIG. */
#define IWN_FH_TX_CONFIG_DMA_PAUSE 0
#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31)
#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20)
/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
@ -323,7 +323,7 @@ static const struct {
#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16))
/* Possible flags for register IWN_FH_RX_CONFIG. */
#define IWN_FH_RX_CONFIG_ENA (1 << 31)
#define IWN_FH_RX_CONFIG_ENA (1U << 31)
#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20)
#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16)
#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15)
@ -332,7 +332,7 @@ static const struct {
#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2)
/* Possible flags for register IWN_FH_TX_CONFIG. */
#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31)
#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3)
/* Possible flags for register IWN_EEPROM. */
@ -380,7 +380,7 @@ static const struct {
#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11)
/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
#define IWN_FW_UPDATED (1 << 31)
#define IWN_FW_UPDATED (1U << 31)
#define IWN_SCHED_WINSZ 64
#define IWN_SCHED_LIMIT 64

6
sys/dev/mge/if_mgevar.h
View File

@ -262,7 +262,7 @@ struct mge_softc {
#define MGE_PORT_INT_RXQ0 (1 << 2)
#define MGE_PORT_INT_RXERR (1 << 10)
#define MGE_PORT_INT_RXERRQ0 (1 << 11)
#define MGE_PORT_INT_SUM (1 << 31)
#define MGE_PORT_INT_SUM (1U << 31)
#define MGE_PORT_INT_CAUSE_EXT 0x464
#define MGE_PORT_INT_MASK_EXT 0x46C
@ -273,7 +273,7 @@ struct mge_softc {
#define MGE_PORT_INT_EXT_TXUR (1 << 19)
#define MGE_PORT_INT_EXT_LC (1 << 20)
#define MGE_PORT_INT_EXT_IAR (1 << 23)
#define MGE_PORT_INT_EXT_SUM (1 << 31)
#define MGE_PORT_INT_EXT_SUM (1U << 31)
#define MGE_RX_FIFO_URGENT_TRSH 0x470
#define MGE_TX_FIFO_URGENT_TRSH 0x474
@ -330,7 +330,7 @@ struct mge_softc {
#define MGE_RX_DESC_FIRST (1 << 27)
#define MGE_RX_ENABLE_INT (1 << 29)
#define MGE_RX_L4_CSUM_OK (1 << 30)
#define MGE_DMA_OWNED (1 << 31)
#define MGE_DMA_OWNED (1U << 31)
#define MGE_RX_IP_FRAGMENT (1 << 2)

4
sys/dev/mpt/mpt_cam.c
View File

@ -1431,7 +1431,7 @@ mpt_execute_req_a64(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
/* SAS1078 36GB limitation WAR */
if (mpt->is_1078 && (((uint64_t)dm_segs->ds_addr +
MPI_SGE_LENGTH(se->FlagsLength)) >> 32) == 9) {
addr |= (1 << 31);
addr |= (1U << 31);
tf |= MPI_SGE_FLAGS_LOCAL_ADDRESS;
}
se->Address.High = htole32(addr);
@ -1554,7 +1554,7 @@ mpt_execute_req_a64(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
(((uint64_t)dm_segs->ds_addr +
MPI_SGE_LENGTH(se->FlagsLength)) >>
32) == 9) {
addr |= (1 << 31);
addr |= (1U << 31);
tf |= MPI_SGE_FLAGS_LOCAL_ADDRESS;
}
se->Address.High = htole32(addr);

2
sys/dev/msk/if_mskreg.h
View File

@ -156,7 +156,7 @@
#define DEVICEID_DLINK_DGE560SX 0x4002
#define DEVICEID_DLINK_DGE560T 0x4b00
#define BIT_31 (1 << 31)
#define BIT_31 (1U << 31)
#define BIT_30 (1 << 30)
#define BIT_29 (1 << 29)
#define BIT_28 (1 << 28)

2
sys/dev/mvs/mvs.h
View File

@ -141,7 +141,7 @@
#define EDMA_IE_LINKDATARXERR(x) ((x) << 17) /* Link Data Recv Err */
#define EDMA_IE_LINKCTLTXERR(x) ((x) << 21) /* Link Ctrl Tx Error */
#define EDMA_IE_LINKDATATXERR(x) ((x) << 26) /* Link Data Tx Error */
#define EDMA_IE_TRANSPROTERR (1 << 31) /* Transport Proto E */
#define EDMA_IE_TRANSPROTERR (1U << 31) /* Transport Proto E */
#define EDMA_IE_TRANSIENT (EDMA_IE_LINKCTLRXERR(0x0b) | \
EDMA_IE_LINKCTLTXERR(0x1f))
/* Non-fatal Errors */

2
sys/dev/mxge/mxge_mcp.h
View File

@ -226,7 +226,7 @@ enum myri10ge_mcp_cmd_type {
a power of 2 number of entries. */
MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */
#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31)
#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1U << 31)
/* command to bring ethernet interface up. Above parameters
(plus mtu & mac address) must have been exchanged prior

2
sys/dev/qlxge/qls_dump.c
View File

@ -111,7 +111,7 @@ enum
Q81_PAUSE_FRM_DEST_LO = 0x00000128,
Q81_PAUSE_FRM_DEST_HI = 0x0000012c,
Q81_MAC_TX_PARAMS = 0x00000134,
Q81_MAC_TX_PARAMS_JUMBO = (1 << 31), /*Control*/
Q81_MAC_TX_PARAMS_JUMBO = (1U << 31), /*Control*/
Q81_MAC_TX_PARAMS_SIZE_SHIFT = 16, /*Control*/
Q81_MAC_RX_PARAMS = 0x00000138,
Q81_MAC_SYS_INT = 0x00000144,

2
sys/dev/ral/rt2560reg.h
View File

@ -268,7 +268,7 @@ struct rt2560_rx_desc {
#define RT2560_BBP_BUSY (1 << 15)
#define RT2560_BBP_WRITE (1 << 16)
#define RT2560_RF_20BIT (20 << 24)
#define RT2560_RF_BUSY (1 << 31)
#define RT2560_RF_BUSY (1U << 31)
#define RT2560_RF_2522 0x00
#define RT2560_RF_2523 0x01

2
sys/dev/ral/rt2661reg.h
View File

@ -182,7 +182,7 @@
/* possible flags for register PHY_CSR4 */
#define RT2661_RF_21BIT (21 << 24)
#define RT2661_RF_BUSY (1 << 31)
#define RT2661_RF_BUSY (1U << 31)
/* possible values for register STA_CSR4 */
#define RT2661_TX_STAT_VALID (1 << 0)

14
sys/dev/ral/rt2860reg.h
View File

@ -258,7 +258,7 @@
#define RT2860_TX_DMA_EN (1 << 0)
/* possible flags for register DELAY_INT_CFG */
#define RT2860_TXDLY_INT_EN (1 << 31)
#define RT2860_TXDLY_INT_EN (1U << 31)
#define RT2860_TXMAX_PINT_SHIFT 24
#define RT2860_TXMAX_PTIME_SHIFT 16
#define RT2860_RXDLY_INT_EN (1 << 15)
@ -270,7 +270,7 @@
#define RT2860_GPIO_O_SHIFT 0
/* possible flags for register USB_DMA_CFG */
#define RT2860_USB_TX_BUSY (1 << 31)
#define RT2860_USB_TX_BUSY (1U << 31)
#define RT2860_USB_RX_BUSY (1 << 30)
#define RT2860_USB_EPOUT_VLD_SHIFT 24
#define RT2860_USB_TX_EN (1 << 23)
@ -370,7 +370,7 @@
#define RT2860_TX0Q_PCNT_MASK 0x000000ff
/* possible flags for register CAP_CTRL */
#define RT2860_CAP_ADC_FEQ (1 << 31)
#define RT2860_CAP_ADC_FEQ (1U << 31)
#define RT2860_CAP_START (1 << 30)
#define RT2860_MAN_TRIG (1 << 29)
#define RT2860_TRIG_OFFSET_SHIFT 16
@ -381,7 +381,7 @@
#define RT3070_RF_WRITE (1 << 16)
/* possible flags for register EFUSE_CTRL */
#define RT3070_SEL_EFUSE (1 << 31)
#define RT3070_SEL_EFUSE (1U << 31)
#define RT3070_EFSROM_KICK (1 << 30)
#define RT3070_EFSROM_AIN_MASK 0x03ff0000
#define RT3070_EFSROM_AIN_SHIFT 16
@ -420,7 +420,7 @@
#define RT2860_BBP_DATA_SHIFT 0
/* possible flags for register RF_CSR_CFG0 */
#define RT2860_RF_REG_CTRL (1 << 31)
#define RT2860_RF_REG_CTRL (1U << 31)
#define RT2860_RF_LE_SEL1 (1 << 30)
#define RT2860_RF_LE_STBY (1 << 29)
#define RT2860_RF_REG_WIDTH_SHIFT 24
@ -455,7 +455,7 @@
#define RT2860_SLOT_TIME 0
/* possible flags for register NAV_TIME_CFG */
#define RT2860_NAV_UPD (1 << 31)
#define RT2860_NAV_UPD (1U << 31)
#define RT2860_NAV_UPD_VAL_SHIFT 16
#define RT2860_NAV_CLR_EN (1 << 15)
#define RT2860_NAV_TIMER_SHIFT 0
@ -509,7 +509,7 @@
#define RT2860_WAKEUP_LEAD_TIME_SHIFT 0
/* possible flags for register TX_PIN_CFG */
#define RT3593_LNA_PE_G2_POL (1 << 31)
#define RT3593_LNA_PE_G2_POL (1U << 31)
#define RT3593_LNA_PE_A2_POL (1 << 30)
#define RT3593_LNA_PE_G2_EN (1 << 29)
#define RT3593_LNA_PE_A2_EN (1 << 28)

2
sys/dev/sound/pci/hda/hdaa.h
View File

@ -56,7 +56,7 @@
#define HDAA_QUIRK_IVREF100 (1 << 28)
#define HDAA_QUIRK_OVREF50 (1 << 29)
#define HDAA_QUIRK_OVREF80 (1 << 30)
#define HDAA_QUIRK_OVREF100 (1 << 31)
#define HDAA_QUIRK_OVREF100 (1U << 31)
#define HDAA_QUIRK_IVREF (HDAA_QUIRK_IVREF50 | HDAA_QUIRK_IVREF80 | \
HDAA_QUIRK_IVREF100)

4
sys/dev/usb/controller/ehci.h
View File

@ -90,7 +90,7 @@ struct ehci_itd {
#define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0x7)
#define EHCI_ITD_SET_OFFS(x) (x)
#define EHCI_ITD_GET_OFFS(x) (((x) >> 0) & 0xFFF)
#define EHCI_ITD_ACTIVE (1 << 31)
#define EHCI_ITD_ACTIVE (1U << 31)
#define EHCI_ITD_DATABUFERR (1 << 30)
#define EHCI_ITD_BABBLE (1 << 29)
#define EHCI_ITD_XACTERR (1 << 28)
@ -126,7 +126,7 @@ struct ehci_sitd {
volatile uint32_t sitd_next;
volatile uint32_t sitd_portaddr;
#define EHCI_SITD_SET_DIR_OUT (0 << 31)
#define EHCI_SITD_SET_DIR_IN (1 << 31)
#define EHCI_SITD_SET_DIR_IN (1U << 31)
#define EHCI_SITD_SET_ADDR(x) (x)
#define EHCI_SITD_GET_ADDR(x) ((x) & 0x7F)
#define EHCI_SITD_SET_ENDPT(x) ((x) << 8)

2
sys/dev/usb/wlan/if_rumreg.h
View File

@ -139,7 +139,7 @@
#define RT2573_BBP_BUSY (1 << 16)
/* possible flags for register PHY_CSR4 */
#define RT2573_RF_20BIT (20 << 24)
#define RT2573_RF_BUSY (1 << 31)
#define RT2573_RF_BUSY (1U << 31)
/* LED values */
#define RT2573_LED_RADIO (1 << 8)

12
sys/dev/usb/wlan/if_runreg.h
View File

@ -257,7 +257,7 @@
#define RT2860_TX_DMA_EN (1 << 0)
/* possible flags for register DELAY_INT_CFG */
#define RT2860_TXDLY_INT_EN (1 << 31)
#define RT2860_TXDLY_INT_EN (1U << 31)
#define RT2860_TXMAX_PINT_SHIFT 24
#define RT2860_TXMAX_PTIME_SHIFT 16
#define RT2860_RXDLY_INT_EN (1 << 15)
@ -269,7 +269,7 @@
#define RT2860_GPIO_O_SHIFT 0
/* possible flags for register USB_DMA_CFG */
#define RT2860_USB_TX_BUSY (1 << 31)
#define RT2860_USB_TX_BUSY (1U << 31)
#define RT2860_USB_RX_BUSY (1 << 30)
#define RT2860_USB_EPOUT_VLD_SHIFT 24
#define RT2860_USB_TX_EN (1 << 23)
@ -369,7 +369,7 @@
#define RT2860_TX0Q_PCNT_MASK 0x000000ff
/* possible flags for register CAP_CTRL */
#define RT2860_CAP_ADC_FEQ (1 << 31)
#define RT2860_CAP_ADC_FEQ (1U << 31)
#define RT2860_CAP_START (1 << 30)
#define RT2860_MAN_TRIG (1 << 29)
#define RT2860_TRIG_OFFSET_SHIFT 16
@ -380,7 +380,7 @@
#define RT3070_RF_WRITE (1 << 16)
/* possible flags for register EFUSE_CTRL */
#define RT3070_SEL_EFUSE (1 << 31)
#define RT3070_SEL_EFUSE (1U << 31)
#define RT3070_EFSROM_KICK (1 << 30)
#define RT3070_EFSROM_AIN_MASK 0x03ff0000
#define RT3070_EFSROM_AIN_SHIFT 16
@ -419,7 +419,7 @@
#define RT2860_BBP_DATA_SHIFT 0
/* possible flags for register RF_CSR_CFG0 */
#define RT2860_RF_REG_CTRL (1 << 31)
#define RT2860_RF_REG_CTRL (1U << 31)
#define RT2860_RF_LE_SEL1 (1 << 30)
#define RT2860_RF_LE_STBY (1 << 29)
#define RT2860_RF_REG_WIDTH_SHIFT 24
@ -454,7 +454,7 @@
#define RT2860_SLOT_TIME 0
/* possible flags for register NAV_TIME_CFG */
#define RT2860_NAV_UPD (1 << 31)
#define RT2860_NAV_UPD (1U << 31)
#define RT2860_NAV_UPD_VAL_SHIFT 16
#define RT2860_NAV_CLR_EN (1 << 15)
#define RT2860_NAV_TIMER_SHIFT 0

2
sys/dev/usb/wlan/if_uralreg.h
View File

@ -197,7 +197,7 @@ struct ural_rx_desc {
} __packed;
#define RAL_RF_LOBUSY (1 << 15)
#define RAL_RF_BUSY (1 << 31)
#define RAL_RF_BUSY (1U << 31)
#define RAL_RF_20BIT (20 << 24)
#define RAL_RF1 0

8
sys/dev/usb/wlan/if_urtwreg.h
View File

@ -72,7 +72,7 @@
#define URTW_TX_HWMASK (7 << 25)
#define URTW_TX_DISREQQSIZE (1 << 28)
#define URTW_TX_HW_SEQNUM (1 << 30)
#define URTW_TX_CWMIN (1 << 31)
#define URTW_TX_CWMIN (1U << 31)
#define URTW_TX_NOICV (0x80000)
#define URTW_RX 0x0044 /* 4 byte */
#define URTW_RX_9356SEL (1 << 6)
@ -106,7 +106,7 @@
#define URTW_MAX_RX_DMA_2048 (7 << URTW_MAX_RX_DMA_SHIFT)
#define URTW_MAX_RX_DMA_1024 (6)
#define URTW_MAX_RX_DMA_SHIFT (10)
#define URTW_RCR_ONLYERLPKT (1 << 31)
#define URTW_RCR_ONLYERLPKT (1U << 31)
#define URTW_INT_TIMEOUT 0x0048 /* 4 byte */
#define URTW_INT_TBDA 0x004c /* 4 byte */
#define URTW_EPROM_CMD 0x0050 /* 1 byte */
@ -330,7 +330,7 @@ struct urtw_8187b_rxhdr {
#define URTW_RX_FLAG_LAST (1 << 28)
#define URTW_RX_FLAG_FIRST (1 << 29)
#define URTW_RX_FLAG_EOR (1 << 30)
#define URTW_RX_FLAG_OWN (1 << 31)
#define URTW_RX_FLAG_OWN (1U << 31)
uint64_t mactime;
uint8_t noise;
uint8_t rssi;
@ -367,7 +367,7 @@ struct urtw_8187b_txhdr {
#define URTW_TX_FLAG_LAST (1 << 28)
#define URTW_TX_FLAG_FIRST (1 << 29)
#define URTW_TX_FLAG_DMA (1 << 30)
#define URTW_TX_FLAG_OWN (1 << 31)
#define URTW_TX_FLAG_OWN (1U << 31)
uint16_t rtsdur;
uint16_t len;
#define URTW_TX_LEN /* 0 ~ 14 bits */

2
sys/dev/usb/wlan/if_zydreg.h
View File

@ -1007,7 +1007,7 @@
#define ZYD_FILTER_CTS (1 << 28)
#define ZYD_FILTER_ACK (1 << 29)
#define ZYD_FILTER_CFE (1 << 30)
#define ZYD_FILTER_CFE_A (1 << 31)
#define ZYD_FILTER_CFE_A (1U << 31)
/* helpers for register ZYD_MAC_RXFILTER */
#define ZYD_FILTER_MONITOR 0xffffffff

4
sys/dev/wpi/if_wpireg.h
View File

@ -143,7 +143,7 @@
/* possible flags for register WPI_UC_CTL */
#define WPI_UC_ENABLE (1 << 30)
#define WPI_UC_RUN (1 << 31)
#define WPI_UC_RUN (1U << 31)
/* possible flags for register WPI_INTR_CSR */
#define WPI_ALIVE_INTR (1 << 0)
@ -151,7 +151,7 @@
#define WPI_SW_ERROR (1 << 25)
#define WPI_TX_INTR (1 << 27)
#define WPI_HW_ERROR (1 << 29)
#define WPI_RX_INTR (1 << 31)
#define WPI_RX_INTR (1U << 31)
#define WPI_INTR_MASK \
(WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \

6
sys/geom/raid/tr_raid1e.c
View File

@ -1051,7 +1051,7 @@ g_raid_tr_iodone_raid1e(struct g_raid_tr_object *tr,
nsd->sd_pos);
if (do_write)
mask |= 1 << 31;
if ((mask & (1 << 31)) != 0)
if ((mask & (1U << 31)) != 0)
sd->sd_recovery++;
cbp->bio_caller2 = (void *)mask;
if (do_write) {
@ -1074,7 +1074,7 @@ g_raid_tr_iodone_raid1e(struct g_raid_tr_object *tr,
}
if (bp->bio_cmd == BIO_READ &&
bp->bio_error == 0 &&
(mask & (1 << 31)) != 0) {
(mask & (1U << 31)) != 0) {
G_RAID_LOGREQ(3, bp, "Recovered data from other drive");
/* Restore what we were doing. */
@ -1101,7 +1101,7 @@ g_raid_tr_iodone_raid1e(struct g_raid_tr_object *tr,
return;
}
}
if ((mask & (1 << 31)) != 0) {
if ((mask & (1U << 31)) != 0) {
/*
* We're done with a recovery, mark the range as unlocked.
* For any write errors, we agressively fail the disk since

2
sys/i386/pci/pci_cfgreg.c
View File

@ -306,7 +306,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
switch (cfgmech) {
case CFGMECH_PCIE:
case CFGMECH_1:
outl(CONF1_ADDR_PORT, (1 << 31)
outl(CONF1_ADDR_PORT, (1U << 31)
| (bus << 16) | (slot << 11)
| (func << 8) | (reg & ~0x03));
dataport = CONF1_DATA_PORT + (reg & 0x03);

8
sys/mips/atheros/ar71xxreg.h
View File

@ -162,7 +162,7 @@
#define AR71XX_BASE_FREQ 40000000
#define AR71XX_PLL_CPU_BASE 0x18050000
#define AR71XX_PLL_CPU_CONFIG 0x18050000
#define PLL_SW_UPDATE (1 << 31)
#define PLL_SW_UPDATE (1U << 31)
#define PLL_LOCKED (1 << 30)
#define PLL_AHB_DIV_SHIFT 20
#define PLL_AHB_DIV_MASK 7
@ -200,7 +200,7 @@
#define AR71XX_RST_BLOCK_BASE 0x18060000
#define AR71XX_RST_WDOG_CONTROL 0x18060008
#define RST_WDOG_LAST (1 << 31)
#define RST_WDOG_LAST (1U << 31)
#define RST_WDOG_ACTION_MASK 3
#define RST_WDOG_ACTION_RESET 3
#define RST_WDOG_ACTION_NMI 2
@ -303,7 +303,7 @@ typedef enum {
#define AR71XX_MAC1_BASE 0x1A000000
#define AR71XX_MAC_CFG1 0x00
#define MAC_CFG1_SOFT_RESET (1 << 31)
#define MAC_CFG1_SOFT_RESET (1U << 31)
#define MAC_CFG1_SIMUL_RESET (1 << 30)
#define MAC_CFG1_MAC_RX_BLOCK_RESET (1 << 19)
#define MAC_CFG1_MAC_TX_BLOCK_RESET (1 << 18)
@ -332,7 +332,7 @@ typedef enum {
#define AR71XX_MAC_HDUPLEX 0x0C
#define AR71XX_MAC_MAX_FRAME_LEN 0x10
#define AR71XX_MAC_MII_CFG 0x20
#define MAC_MII_CFG_RESET (1 << 31)
#define MAC_MII_CFG_RESET (1U << 31)
#define MAC_MII_CFG_SCAN_AUTO_INC (1 << 5)
#define MAC_MII_CFG_PREAMBLE_SUP (1 << 4)
#define MAC_MII_CFG_CLOCK_SELECT_MASK 0x7

2
sys/mips/atheros/ar934xreg.h
View File

@ -103,7 +103,7 @@
#define AR934X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xb0)
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS (AR71XX_RST_BLOCK_BASE + 0xac)
#define AR934X_RESET_HOST (1 << 31)
#define AR934X_RESET_HOST (1U << 31)
#define AR934X_RESET_SLIC (1 << 30)
#define AR934X_RESET_HDMA (1 << 29)
#define AR934X_RESET_EXTERNAL (1 << 28)

2
sys/mips/atheros/if_argevar.h
View File

@ -82,7 +82,7 @@
#define ARGE_MDIO_BARRIER_WRITE(_sc) ARGE_BARRIER_WRITE(_sc)
#define ARGE_MDIO_BARRIER_RW(_sc) ARGE_BARRIER_READ_RW(_sc)
#define ARGE_DESC_EMPTY (1 << 31)
#define ARGE_DESC_EMPTY (1U << 31)
#define ARGE_DESC_MORE (1 << 24)
#define ARGE_DESC_SIZE_MASK ((1 << 12) - 1)
#define ARGE_DMASIZE(len) ((len) & ARGE_DESC_SIZE_MASK)

4
sys/mips/malta/gt_pci.c
View File

@ -448,7 +448,7 @@ gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
/* Clear cause register bits. */
GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1 << 31) | addr);
GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
/*
* Galileo system controller is special
*/
@ -555,7 +555,7 @@ gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
/* Clear cause register bits. */
GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1 << 31) | addr);
GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
/*
* Galileo system controller is special

4
sys/mips/nlm/dev/net/nae.c
View File

@ -1401,7 +1401,7 @@ nlm_nae_open_if(uint64_t nae_base, int nblock, int port_type,
mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
nlm_write_nae_reg(nae_base, conf1_reg,
mac_cfg1 |
(1 << 31) | /* soft reset */
(1U << 31) | /* soft reset */
(1 << 2) | /* rx enable */
(1)); /* tx enable */
@ -1415,7 +1415,7 @@ nlm_nae_open_if(uint64_t nae_base, int nblock, int port_type,
/* clear gmac reset */
mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(1 << 31));
nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(1U << 31));
/* clear speed debug bit */
iface_ctrl3_reg = SGMII_NET_IFACE_CTRL3(nblock, iface);

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