Add a check to validate that memory BARs of passthru devices are 4KB aligned.
Also, the MSI-x table offset is not required to be 4KB aligned so take this into account when computing the pages occupied by the MSI-x tables.
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53905cf487
commit
7a902ec0ec
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=262184
@ -792,7 +792,6 @@ pci_msix_table_init(struct pci_devinst *pi, int table_entries)
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int
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pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
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{
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uint16_t pba_index;
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uint32_t tab_size;
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struct msixcap msixcap;
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@ -809,10 +808,7 @@ pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
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pi->pi_msix.table_offset = 0;
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pi->pi_msix.table_count = msgnum;
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pi->pi_msix.pba_offset = tab_size;
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/* calculate the MMIO size required for MSI-X PBA */
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pba_index = (msgnum - 1) / (PBA_TABLE_ENTRY_SIZE * 8);
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pi->pi_msix.pba_size = (pba_index + 1) * PBA_TABLE_ENTRY_SIZE;
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pi->pi_msix.pba_size = PBA_SIZE(msgnum);
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pci_msix_table_init(pi, msgnum);
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@ -100,7 +100,7 @@ struct msix_table_entry {
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*/
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#define MSIX_TABLE_ENTRY_SIZE 16
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#define MAX_MSIX_TABLE_ENTRIES 2048
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#define PBA_TABLE_ENTRY_SIZE 8
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#define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8)
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enum lintr_stat {
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IDLE,
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@ -135,10 +135,10 @@ struct pci_devinst {
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int enabled;
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int table_bar;
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int pba_bar;
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size_t table_offset;
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uint32_t table_offset;
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int table_count;
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size_t pba_offset;
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size_t pba_size;
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uint32_t pba_offset;
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int pba_size;
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int function_mask;
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struct msix_table_entry *table; /* allocated at runtime */
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} pi_msix;
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@ -228,6 +228,7 @@ cfginitmsi(struct passthru_softc *sc)
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pi->pi_msix.table_offset =
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msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
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pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
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pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
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/* Allocate the emulated MSI-X table array */
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table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
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@ -279,8 +280,10 @@ msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
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int index;
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pi = sc->psc_pi;
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offset -= pi->pi_msix.table_offset;
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if (offset < pi->pi_msix.table_offset)
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return (-1);
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offset -= pi->pi_msix.table_offset;
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index = offset / MSIX_TABLE_ENTRY_SIZE;
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if (index >= pi->pi_msix.table_count)
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return (-1);
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@ -324,8 +327,10 @@ msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc,
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int error, index;
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pi = sc->psc_pi;
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offset -= pi->pi_msix.table_offset;
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if (offset < pi->pi_msix.table_offset)
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return;
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offset -= pi->pi_msix.table_offset;
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index = offset / MSIX_TABLE_ENTRY_SIZE;
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if (index >= pi->pi_msix.table_count)
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return;
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@ -358,7 +363,9 @@ init_msix_table(struct vmctx *ctx, struct passthru_softc *sc, uint64_t base)
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{
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int b, s, f;
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int error, idx;
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size_t len, remaining, table_size;
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size_t len, remaining;
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uint32_t table_size, table_offset;
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uint32_t pba_size, pba_offset;
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vm_paddr_t start;
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struct pci_devinst *pi = sc->psc_pi;
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@ -374,24 +381,37 @@ init_msix_table(struct vmctx *ctx, struct passthru_softc *sc, uint64_t base)
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* either resides in its own page within the region,
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* or it resides in a page shared with only the PBA.
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*/
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if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar &&
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((pi->pi_msix.pba_offset - pi->pi_msix.table_offset) < 4096)) {
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/* Need to also emulate the PBA, not supported yet */
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printf("Unsupported MSI-X configuration: %d/%d/%d\n", b, s, f);
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return (-1);
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}
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table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
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/* Compute the MSI-X table size */
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table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
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table_size = pi->pi_msix.table_offset - table_offset;
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table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
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table_size = roundup2(table_size, 4096);
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if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar) {
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pba_offset = pi->pi_msix.pba_offset;
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pba_size = pi->pi_msix.pba_size;
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if (pba_offset >= table_offset + table_size ||
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table_offset >= pba_offset + pba_size) {
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/*
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* The PBA can reside in the same BAR as the MSI-x
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* tables as long as it does not overlap with any
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* naturally aligned page occupied by the tables.
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*/
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} else {
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/* Need to also emulate the PBA, not supported yet */
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printf("Unsupported MSI-X configuration: %d/%d/%d\n",
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b, s, f);
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return (-1);
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}
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}
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idx = pi->pi_msix.table_bar;
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start = pi->pi_bar[idx].addr;
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remaining = pi->pi_bar[idx].size;
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/* Map everything before the MSI-X table */
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if (pi->pi_msix.table_offset > 0) {
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len = pi->pi_msix.table_offset;
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if (table_offset > 0) {
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len = table_offset;
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error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
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if (error)
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return (error);
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@ -424,7 +444,7 @@ cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
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struct pci_devinst *pi;
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struct pci_bar_io bar;
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enum pcibar_type bartype;
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uint64_t base;
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uint64_t base, size;
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pi = sc->psc_pi;
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@ -453,15 +473,25 @@ cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
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}
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base = bar.pbi_base & PCIM_BAR_MEM_BASE;
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}
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size = bar.pbi_length;
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if (bartype != PCIBAR_IO) {
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if (((base | size) & PAGE_MASK) != 0) {
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printf("passthru device %d/%d/%d BAR %d: "
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"base %#lx or size %#lx not page aligned\n",
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sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
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sc->psc_sel.pc_func, i, base, size);
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return (-1);
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}
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}
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/* Cache information about the "real" BAR */
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sc->psc_bar[i].type = bartype;
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sc->psc_bar[i].size = bar.pbi_length;
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sc->psc_bar[i].size = size;
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sc->psc_bar[i].addr = base;
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/* Allocate the BAR in the guest I/O or MMIO space */
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error = pci_emul_alloc_pbar(pi, i, base, bartype,
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bar.pbi_length);
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error = pci_emul_alloc_pbar(pi, i, base, bartype, size);
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if (error)
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return (-1);
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@ -471,7 +501,7 @@ cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
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if (error)
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return (-1);
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} else if (bartype != PCIBAR_IO) {
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/* Map the physical MMIO space in the guest MMIO space */
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/* Map the physical BAR in the guest MMIO space */
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error = vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
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sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
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pi->pi_bar[i].addr, pi->pi_bar[i].size, base);
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