Remove mips MD atomic_load_64 and atomic_store_64.
The only users of the functions were db_read_bytes() and db_write_bytes() ddb(4) interfaces. Replace the calls with direct reads and writes, which are automatically atomic on 64bits and n32. Note that removed assembler implementation for mips32 is not atomic anyway. Reviewed by: jhb Discussed with: imp Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D13586
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=327097
@ -341,24 +341,6 @@ atomic_store_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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ATOMIC_STORE_LOAD(32)
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ATOMIC_STORE_LOAD(64)
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#if !defined(__mips_n64) && !defined(__mips_n32)
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void atomic_store_64(__volatile uint64_t *, uint64_t);
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uint64_t atomic_load_64(__volatile uint64_t *);
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#elif defined (__mips_n32)
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static __inline void
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atomic_store_64(__volatile uint64_t *p, uint64_t v)
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{
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*p = v;
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}
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static __inline uint64_t
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atomic_load_64(__volatile uint64_t *p)
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{
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return (*p);
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}
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/* #else atomic_common.h definitions of atomic_load/store_64 are used */
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#endif
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#undef ATOMIC_STORE_LOAD
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/*
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@ -152,6 +152,7 @@ db_read_bytes(vm_offset_t addr, size_t size, char *data)
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/*
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* 'addr' could be a memory-mapped I/O address. Try to
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* do atomic load/store in unit of size requested.
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* size == 8 is only atomic on 64bit or n32 kernel.
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*/
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if ((size == 2 || size == 4 || size == 8) &&
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((addr & (size -1)) == 0) &&
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@ -164,8 +165,7 @@ db_read_bytes(vm_offset_t addr, size_t size, char *data)
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*(uint32_t *)data = *(uint32_t *)addr;
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break;
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case 8:
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*(uint64_t *)data = atomic_load_64(
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(void *)addr);
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*(uint64_t *)data = *(uint64_t *)addr;
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break;
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}
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} else {
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@ -195,6 +195,7 @@ db_write_bytes(vm_offset_t addr, size_t size, char *data)
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/*
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* 'addr' could be a memory-mapped I/O address. Try to
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* do atomic load/store in unit of size requested.
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* size == 8 is only atomic on 64bit or n32 kernel.
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*/
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if ((size == 2 || size == 4 || size == 8) &&
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((addr & (size -1)) == 0) &&
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@ -207,8 +208,7 @@ db_write_bytes(vm_offset_t addr, size_t size, char *data)
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*(uint32_t *)addr = *(uint32_t *)data;
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break;
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case 8:
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atomic_store_64((uint64_t *)addr,
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*(uint64_t *)data);
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*(uint64_t *)addr = *(uint64_t *)data;
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break;
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}
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} else {
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@ -839,75 +839,8 @@ LEAF(atomic_subtract_8)
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nop
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END(atomic_subtract_8)
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/*
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* atomic 64-bit register read/write assembly language support routines.
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*/
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.set noreorder # Noreorder is default style!
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#if !defined(__mips_n64) && !defined(__mips_n32)
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/*
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* I don't know if these routines have the right number of
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* NOPs in it for all processors. XXX
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*
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* Maybe it would be better to just leave this undefined in that case.
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*
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* XXX These routines are not safe in the case of a TLB miss on a1 or
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* a0 unless the trapframe is 64-bit, which it just isn't with O32.
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* If we take any exception, not just an interrupt, the upper
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* 32-bits will be clobbered. Use only N32 and N64 kernels if you
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* want to use 64-bit registers while interrupts are enabled or
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* with memory operations. Since this isn't even using load-linked
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* and store-conditional, perhaps it should just use two registers
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* instead, as is right and good with the O32 ABI.
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*/
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LEAF(atomic_store_64)
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mfc0 t1, MIPS_COP_0_STATUS
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and t2, t1, ~MIPS_SR_INT_IE
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mtc0 t2, MIPS_COP_0_STATUS
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nop
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nop
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nop
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nop
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ld t0, (a1)
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nop
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nop
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sd t0, (a0)
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nop
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nop
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mtc0 t1,MIPS_COP_0_STATUS
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nop
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nop
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nop
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nop
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j ra
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nop
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END(atomic_store_64)
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LEAF(atomic_load_64)
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mfc0 t1, MIPS_COP_0_STATUS
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and t2, t1, ~MIPS_SR_INT_IE
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mtc0 t2, MIPS_COP_0_STATUS
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nop
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nop
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nop
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nop
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ld t0, (a0)
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nop
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nop
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sd t0, (a1)
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nop
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nop
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mtc0 t1,MIPS_COP_0_STATUS
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nop
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nop
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nop
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nop
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j ra
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nop
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END(atomic_load_64)
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#endif
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#if defined(DDB) || defined(DEBUG)
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LEAF(kdbpeek)
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