Add the generic timer registers to sysreg.h and cpu-v6.h, and use the
access functions in the generic timer driver. Differential Revision: https://reviews.freebsd.org/D2198 Sponsored by: The FreeBSD Foundation
This commit is contained in:
Andrew Turner
parent
42e70ae82a
commit
7b309274e3
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=280985
@ -105,12 +105,7 @@ static struct timecounter arm_tmr_timecount = {
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static int
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get_freq(void)
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{
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uint32_t val;
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/* cntfrq */
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__asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
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return (val);
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return (cp15_cntfrq_get());
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}
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static long
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@ -120,11 +115,9 @@ get_cntxct(bool physical)
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isb();
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if (physical)
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/* cntpct */
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__asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val));
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val = cp15_cntpct_get();
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else
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/* cntvct */
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__asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (val));
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val = cp15_cntvct_get();
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return (val);
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}
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@ -134,13 +127,9 @@ set_ctrl(uint32_t val, bool physical)
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{
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if (physical)
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/* cntp_ctl */
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__asm volatile("mcr p15, 0, %[val], c14, c2, 1" : :
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[val] "r" (val));
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cp15_cntp_ctl_set(val);
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else
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/* cntv_ctl */
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__asm volatile("mcr p15, 0, %[val], c14, c3, 1" : :
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[val] "r" (val));
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cp15_cntv_ctl_set(val);
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isb();
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return (0);
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@ -151,13 +140,9 @@ set_tval(uint32_t val, bool physical)
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{
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if (physical)
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/* cntp_tval */
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__asm volatile("mcr p15, 0, %[val], c14, c2, 0" : :
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[val] "r" (val));
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cp15_cntp_tval_set(val);
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else
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/* cntv_tval */
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__asm volatile("mcr p15, 0, %[val], c14, c3, 0" : :
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[val] "r" (val));
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cp15_cntv_tval_set(val);
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isb();
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return (0);
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@ -169,11 +154,9 @@ get_ctrl(bool physical)
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uint32_t val;
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if (physical)
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/* cntp_ctl */
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__asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
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val = cp15_cntp_ctl_get();
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else
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/* cntv_ctl */
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__asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
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val = cp15_cntv_ctl_get();
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return (val);
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}
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@ -183,10 +166,10 @@ disable_user_access(void)
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{
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uint32_t cntkctl;
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__asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
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cntkctl = cp15_cntkctl_get();
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cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
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GT_CNTKCTL_EVNTEN | GT_CNTKCTL_PL0VCTEN | GT_CNTKCTL_PL0PCTEN);
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__asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
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cp15_cntkctl_set(cntkctl);
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isb();
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}
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@ -54,6 +54,15 @@ fname(void) \
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return(reg); \
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}
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#define _R64F0(fname, aname) \
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static __inline uint64_t \
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fname(void) \
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{ \
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uint64_t reg; \
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__asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \
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return(reg); \
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}
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#define _WF0(fname, aname...) \
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static __inline void \
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fname(void) \
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@ -68,6 +77,13 @@ fname(register_t reg) \
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__asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \
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}
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#define _W64F1(fname, aname...) \
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static __inline void \
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fname(uint64_t reg) \
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{ \
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__asm __volatile("mcrr\t" _FX(aname):: "r" (reg)); \
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}
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/*
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* Raw CP15 maintenance operations
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* !!! not for external use !!!
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@ -189,6 +205,37 @@ _WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
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_RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
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_WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
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/* Generic Timer registers - only use when you know the hardware is available */
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_RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
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_WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
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_RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
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_WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
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_RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
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_WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
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_RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
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_WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
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_RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
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_WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
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_RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
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_WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
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_RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
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_WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
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_RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
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_WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
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_RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
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_WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
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_R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
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_R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
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_R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
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_W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
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_R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
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_W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
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_R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
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_W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
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_R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
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_W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
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#undef _FX
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#undef _RF0
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#undef _WF0
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@ -256,6 +256,28 @@
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#define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */
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#define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */
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/*
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* CP15 C14 registers
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* These are the Generic Timer registers and may be unallocated on some SoCs.
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* Only use these when you know the Generic Timer is available.
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*/
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#define CP15_CNTFRQ(rr) p15, 0, rr, c14, c0, 0 /* Counter Frequency Register */
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#define CP15_CNTKCTL(rr) p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */
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#define CP15_CNTP_TVAL(rr) p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */
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#define CP15_CNTP_CTL(rr) p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */
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#define CP15_CNTV_TVAL(rr) p15, 0, rr, c14, c3, 0 /* Virtual Timer Value Register */
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#define CP15_CNTV_CTL(rr) p15, 0, rr, c14, c3, 1 /* Virtual Timer Control Register */
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#define CP15_CNTHCTL(rr) p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */
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#define CP15_CNTHP_TVAL(rr) p15, 4, rr, c14, c2, 0 /* PL2 Physical Timer Value Register */
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#define CP15_CNTHP_CTL(rr) p15, 4, rr, c14, c2, 1 /* PL2 Physical Timer Control Register */
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/* 64-bit registers for use with mcrr/mrrc */
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#define CP15_CNTPCT(rq, rr) p15, 0, rq, rr, c14 /* Physical Count Register */
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#define CP15_CNTVCT(rq, rr) p15, 1, rq, rr, c14 /* Virtual Count Register */
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#define CP15_CNTP_CVAL(rq, rr) p15, 2, rq, rr, c14 /* PL1 Physical Timer Compare Value Register */
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#define CP15_CNTV_CVAL(rq, rr) p15, 3, rq, rr, c14 /* Virtual Timer Compare Value Register */
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#define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */
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#define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */
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/*
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* CP15 C15 registers
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*/
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