Fix i386 LINT after r349594.
MFC after: 1 month
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6683132d54
commit
7b96ad44dd
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=349595
@ -93,6 +93,26 @@ SYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN,
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device_printf(ntb->device, __VA_ARGS__); \
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} while (0)
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#ifdef __i386__
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static __inline uint64_t
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bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
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bus_size_t offset)
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{
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return (bus_space_read_4(tag, handle, offset) |
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((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32);
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}
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static __inline void
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bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle,
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bus_size_t offset, uint64_t val)
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{
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bus_space_write_4(tag, handle, offset, val);
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bus_space_write_4(tag, handle, offset + 4, val >> 32);
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}
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#endif
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/*
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* AMD NTB INTERFACE ROUTINES
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*/
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@ -316,11 +336,6 @@ amd_ntb_mw_get_range(device_t dev, unsigned mw_idx, vm_paddr_t *base,
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*plimit = BUS_SPACE_MAXADDR_32BIT;
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}
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amd_ntb_printf(1, "%s: mw %d padd %p vadd %p psize 0x%lx "
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"align 0x%lx asize 0x%lx alimit %p\n", __func__, mw_idx,
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(void *)*base, (void *)*vbase, (uint64_t)*size, (uint64_t)*align,
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(uint64_t)*align_size, (void *)*plimit);
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return (0);
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}
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@ -353,14 +368,14 @@ amd_ntb_mw_set_trans(device_t dev, unsigned mw_idx, bus_addr_t addr, size_t size
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* set and verify setting the translation address
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*/
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amd_ntb_peer_reg_write(8, bar_info->xlat_off, (uint64_t)addr);
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amd_ntb_printf(0, "%s: mw %d xlat_off 0x%x cur_val 0x%lx addr %p\n",
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amd_ntb_printf(0, "%s: mw %d xlat_off 0x%x cur_val 0x%jx addr %p\n",
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__func__, mw_idx, bar_info->xlat_off,
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amd_ntb_peer_reg_read(8, bar_info->xlat_off), (void *)addr);
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/* set and verify setting the limit */
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if (mw_idx != 0) {
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amd_ntb_reg_write(8, bar_info->limit_off, (uint64_t)size);
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amd_ntb_printf(1, "%s: limit_off 0x%x cur_val 0x%lx limit 0x%x\n",
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amd_ntb_printf(1, "%s: limit_off 0x%x cur_val 0x%jx limit 0x%x\n",
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__func__, bar_info->limit_off,
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amd_ntb_peer_reg_read(8, bar_info->limit_off), (uint32_t)size);
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} else {
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@ -470,7 +485,7 @@ amd_ntb_db_read(device_t dev)
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dbstat_off = (uint64_t)amd_ntb_reg_read(2, AMD_DBSTAT_OFFSET);
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amd_ntb_printf(1, "%s: dbstat_off 0x%lx\n", __func__, dbstat_off);
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amd_ntb_printf(1, "%s: dbstat_off 0x%jx\n", __func__, dbstat_off);
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return (dbstat_off);
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}
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@ -480,7 +495,7 @@ amd_ntb_db_clear(device_t dev, uint64_t db_bits)
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{
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struct amd_ntb_softc *ntb = device_get_softc(dev);
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amd_ntb_printf(1, "%s: db_bits 0x%lx\n", __func__, db_bits);
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amd_ntb_printf(1, "%s: db_bits 0x%jx\n", __func__, db_bits);
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amd_ntb_reg_write(2, AMD_DBSTAT_OFFSET, (uint16_t)db_bits);
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}
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@ -490,7 +505,7 @@ amd_ntb_db_set_mask(device_t dev, uint64_t db_bits)
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struct amd_ntb_softc *ntb = device_get_softc(dev);
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DB_MASK_LOCK(ntb);
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amd_ntb_printf(1, "%s: db_mask 0x%x db_bits 0x%lx\n",
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amd_ntb_printf(1, "%s: db_mask 0x%x db_bits 0x%jx\n",
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__func__, ntb->db_mask, db_bits);
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ntb->db_mask |= db_bits;
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@ -504,7 +519,7 @@ amd_ntb_db_clear_mask(device_t dev, uint64_t db_bits)
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struct amd_ntb_softc *ntb = device_get_softc(dev);
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DB_MASK_LOCK(ntb);
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amd_ntb_printf(1, "%s: db_mask 0x%x db_bits 0x%lx\n",
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amd_ntb_printf(1, "%s: db_mask 0x%x db_bits 0x%jx\n",
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__func__, ntb->db_mask, db_bits);
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ntb->db_mask &= ~db_bits;
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@ -517,7 +532,7 @@ amd_ntb_peer_db_set(device_t dev, uint64_t db_bits)
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{
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struct amd_ntb_softc *ntb = device_get_softc(dev);
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amd_ntb_printf(1, "%s: db_bits 0x%lx\n", __func__, db_bits);
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amd_ntb_printf(1, "%s: db_bits 0x%jx\n", __func__, db_bits);
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amd_ntb_reg_write(2, AMD_DBREQ_OFFSET, (uint16_t)db_bits);
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}
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@ -660,17 +675,17 @@ amd_ntb_hw_info_handler(SYSCTL_HANDLER_ARGS)
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sbuf_printf(sb, "AMD Doorbell: 0x%x\n",
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amd_ntb_reg_read(4, AMD_DBSTAT_OFFSET));
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sbuf_printf(sb, "AMD NTB Incoming XLAT: \n");
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sbuf_printf(sb, "AMD XLAT1: 0x%lx\n",
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sbuf_printf(sb, "AMD XLAT1: 0x%jx\n",
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amd_ntb_peer_reg_read(8, AMD_BAR1XLAT_OFFSET));
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sbuf_printf(sb, "AMD XLAT23: 0x%lx\n",
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sbuf_printf(sb, "AMD XLAT23: 0x%jx\n",
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amd_ntb_peer_reg_read(8, AMD_BAR23XLAT_OFFSET));
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sbuf_printf(sb, "AMD XLAT45: 0x%lx\n",
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sbuf_printf(sb, "AMD XLAT45: 0x%jx\n",
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amd_ntb_peer_reg_read(8, AMD_BAR45XLAT_OFFSET));
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sbuf_printf(sb, "AMD LMT1: 0x%x\n",
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amd_ntb_reg_read(4, AMD_BAR1LMT_OFFSET));
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sbuf_printf(sb, "AMD LMT23: 0x%lx\n",
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sbuf_printf(sb, "AMD LMT23: 0x%jx\n",
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amd_ntb_reg_read(8, AMD_BAR23LMT_OFFSET));
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sbuf_printf(sb, "AMD LMT45: 0x%lx\n",
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sbuf_printf(sb, "AMD LMT45: 0x%jx\n",
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amd_ntb_reg_read(8, AMD_BAR45LMT_OFFSET));
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rc = sbuf_finish(sb);
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