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Major snd_hda driver rewrite:

Browse Source 
- Huge old hdac driver was split into three independent pieces: HDA
controller driver (hdac), HDA CODEC driver (hdacc) and HDA sudio function
driver (hdaa).
 - Support for multichannel recording was added. Now, as specification
defines, driver checks input associations for pins with sequence numbers
14 and 15, and if found (usually) -- works as before, mixing signals
together. If it doesn't, it configures input association as multichannel.
 - Signal tracer was improved to look for cases where several DACs/ADCs in
CODEC can work with the same audio signal. If such case found, driver
registers additional playback/record stream (channel) for the pcm device.
 - New controller streams reservation mechanism was implemented. That
allows to have more pcm devices then streams supported by the controller
(usually 4 in each direction). Now it limits only number of simultaneously
transferred audio streams, that is rarely reachable and properly reported
if happens.
 - Codec pins and GPIO signals configuration was exported via set of
writable sysctls. Another sysctl dev.hdaa.X.reconfig allows to trigger
driver reconfiguration in run-time.
 - Driver now decodes pins location and connector type names. In some cases
it allows to hint user where on the system case connectors, related to the
pcm device, are located. Number of channels supported by pcm device,
reported now (if it is not 2), should also make search easier.
 - Added workaround for digital mic on some Asus laptops/netbooks.

MFC after:	2 months
Sponsored by:	iXsystems, Inc.
This commit is contained in:
Alexander Motin 2012-01-15 13:21:36 +00:00
parent f6e633a9e1
commit 7c6b05d280
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=230130
14 changed files with 8994 additions and 7542 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

343
share/man/man4/snd_hda.4
View File

@ -25,7 +25,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd January 22, 2010
.Dd January 11, 2012
.Dt SND_HDA 4
.Os
.Sh NAME
@ -53,8 +53,9 @@ support for several logical audio devices, and general purpose DMA channels.
.Pp
The
.Nm
driver is a HDA bus controller driver and HDA codecs audio functions bridge
driver that allows the generic audio driver,
driver includes HDA bus controller driver (hdac), HDA codec driver (hdacc)
and HDA codecs audio functions bridge driver (hdaa) that allows
the generic audio driver,
.Xr sound 4 ,
to be used with this hardware.
Only audio functions are supported by
@ -77,7 +78,9 @@ For example, one device for main rear 7.1 output and inputs, one device
for independent headset connectors at front and one device for SPDIF or
HDMI audio input/output.
The assignment of audio inputs and outputs may be tuned with
.Xr device.hints 5 .
.Xr device.hints 5
or
.Xr sysctl 8 .
The driver's verbose boot messages provide a lot of information about
the operation of the driver and present audio setup.
.Pp
@ -92,19 +95,26 @@ The following variables are available at boot-time through the
file:
.Bl -tag -width ".Va hint.hdac.%d.config"-offset indent
.It Va hint.hdac.%d.config
Configures a range of possible options.
Configures a range of possible controller options.
Possible values are:
.Dq Li 64bit ,
.Dq Li dmapos ,
.Dq Li msi .
An option prefixed with
.Dq Li no ,
such as
.Dq Li nomsi ,
will do the opposite and takes precedence.
Options can be separated by whitespace and commas.
.It Va hint.hdac.%d.msi
Controls MSI (Message Signaled Interrupts) support.
.It Va hint.hdac.%d.cad%d.nid%d.config
Same as
.Va hint.hdaa.%d.nid%d.config
.It Va hint.hdaa.%d.config
Configures a range of possible audio function options.
Possible values are:
.Dq Li eapdinv ,
.Dq Li gpio0 ,
.Dq Li gpio1 ,
.Dq Li gpio2 ,
.Dq Li gpio3 ,
.Dq Li gpio4 ,
.Dq Li gpio5 ,
.Dq Li gpio6 ,
.Dq Li gpio7 ,
.Dq Li gpioflush ,
.Dq Li ivref ,
.Dq Li ivref50 ,
.Dq Li ivref80 ,
@ -126,22 +136,47 @@ such as
will do the opposite and takes precedence.
Options can be separated by whitespace and commas.
.Pp
The
.Dq Li eapdinv
option inverts External Amplifier Power Down signal.
The
.Dq Li fixedrate
denies all sampling rates except 48KHz.
The
.Dq Li forcestereo
denies mono playback/recording.
The
.Dq Li senseinv
option inverts jack sensing logic.
The
.Dq Li ivref Ns Ar X
and
.Dq Li ovref Ns Ar X
options control the voltage used to power external microphones.
.It Va hint.hdaa.%d.gpio_config
Overrides audio function GPIO pins configuration set by BIOS.
May be specified as a set of space-separated
.Dq Ar num Ns = Ns Ar value
pairs, where
.Ar num
is GPIO line number, and
.Ar value
is one of:
.Dq Li keep ,
.Dq Li set ,
.Dq Li clear ,
.Dq Li disable
and
.Dq Li input .
.Pp
.Dq Li GPIO Ns s
are a codec's General Purpose I/O pins which system integrators sometimes
use to control external muters, amplifiers and so on.
If you have no sound, or sound volume is not adequate, you may have to
experiment a bit with the GPIO setup to find the optimal setup for your
system.
.Pp
The
.Dq Li ivref Ns Ar X
and
.Dq Li ovref Ns Ar X
options control the voltage used to power external microphones.
.It Va hint.hdac.%d.msi
Controls MSI (Message Signaled Interrupts) support.
.It Va hint.hdac.%d.cad%d.nid%d.config
Overrides codec pin configuration set by BIOS.
.It Va hint.hdaa.%d.nid%d.config
Overrides audio function pin configuration set by BIOS.
May be specified as a 32-bit hexadecimal value with a leading
.Dq 0x ,
or as a set of space-separated
@ -165,7 +200,7 @@ The following options are supported:
Association number.
Associations are used to group individual pins to form a complex multi-pin
device.
For example, to group 4 connectors for 7.1 output, or to treat several
For example, to group 4 connectors for 7.1 input/output, or to treat several
input connectors as sources for the same input device.
Association numbers can be specified as numeric values from 0 to 15.
A value of 0 means disabled pin.
@ -180,16 +215,22 @@ A unique, per-association number used to order pins inside the
particular association.
Sequence numbers can be specified as numeric values from 0 to 15.
.Pp
For output assotiations sequence numbers encode speaker pairs positions:
0 - Front, 1 - Center/LFE, 2 - Back, 3 - Front Wide Center, 4 - Side.
Standard combinations are: (0) - Stereo; (0, 2), (0, 4) - Quadro;
(0, 1, 2), (0, 1, 4) - 5.1; (0, 1, 2, 4) - 7.1.
.Pp
The sequence number 15 has a special meaning for output associations.
Output pins with this number and device type
.Dq Ar Headphones
will duplicate (with automatic mute if jack detection is supported) the
first pin in that association.
.Pp
The sequence numbers 14 and 15 has a special meaning for input associations.
Their presence in association defines it as multiplexed or mixed respectively.
If none of them present and there are more then one pin in association,
the association will provide multichannel input.
.Pp
For multichannel input/output assotiations sequence numbers encode
channel pairs positions:
0 - Front, 1 - Center/LFE, 2 - Back, 3 - Front Wide Center, 4 - Side.
Standard combinations are: (0) - Stereo; (0, 2), (0, 4) - Quadro;
(0, 1, 2), (0, 1, 4) - 5.1; (0, 1, 2, 4) - 7.1.
.It Va device
Device type.
Can be specified as a number from 0 to 15 or as a name:
@ -278,7 +319,11 @@ The following
variables are available in addition to those available to all
.Xr sound 4
devices:
.Bl -tag -width ".Va dev.hdac.%d.polling" -offset indent
.Bl -tag -width ".Va dev.hdaa.%d.nid%d_original" -offset indent
.It Va dev.hdac.%d.pindump
Setting this to a non-zero value dumps the current pin configuration, main
capabilities and jack sense status of all audio functions on the controller
to console and syslog.
.It Va dev.hdac.%d.polling
Enables polling mode.
In this mode the driver operates by querying the device state on timer
@ -288,11 +333,30 @@ instead of interrupts.
Polling is disabled by default.
Do not enable it unless you are facing weird interrupt problems or if the
device cannot generate interrupts at all.
.It Va dev.hdac.%d.polling_interval
Controller/Jack Sense polling interval (1-1000 ms)
.It Va dev.hdac.%d.pindump
Setting this to a non-zero value dumps the current pin configuration, main
capabilities and jack sense status to console and syslog.
.It Va dev.hdaa.%d.config
Run-time equivalent of the
.Va hint.hdaa.%d.config
tunable.
.It Va dev.hdaa.%d.gpi_state
Current state of GPI lines.
.It Va dev.hdaa.%d.gpio_state
Current state of GPIO lines.
.It Va dev.hdaa.%d.gpio_config
Run-time equivalent of the
.Va hint.hdaa.%d.gpio.config
tunable.
.It Va dev.hdaa.%d.gpo_state
Current state of GPO lines.
.It Va dev.hdaa.%d.nid%d_config
Run-time equivalent of the
.Va hint.hdaa.%d.nid%d.config
tunable.
.It Va dev.hdaa.%d.nid%d_original
Original pin configuration written by BIOS.
.It Va dev.hdaa.%d.reconfig
Setting this to a non-zero value makes driver to destroy existing pcm devices
and process new pins configuration set via
.Va dev.hdaa.%d.nid%d_config.
.El
.Sh EXAMPLES
Taking HP Compaq DX2300 with Realtek ALC888 HDA codec for example.
@ -307,22 +371,23 @@ So high codec uniformity and flexibility allow driver to configure it in many
different ways, depending on requested pins usage described by pins configuration.
The driver reports such default pin configuration when verbose messages enabled:
.Bd -literal
hdac0: nid 20 0x01014020 as 2 seq 0 Line-out Jack jack 1 loc 1 color Green misc 0
hdac0: nid 21 0x99130110 as 1 seq 0 Speaker Fixed jack 3 loc 25 color Unknown misc 1
hdac0: nid 22 0x411111f0 as 15 seq 0 Speaker None jack 1 loc 1 color Black misc 1
hdac0: nid 23 0x411111f0 as 15 seq 0 Speaker None jack 1 loc 1 color Black misc 1
hdac0: nid 24 0x01a19830 as 3 seq 0 Mic Jack jack 1 loc 1 color Pink misc 8
hdac0: nid 25 0x02a1983f as 3 seq 15 Mic Jack jack 1 loc 2 color Pink misc 8
hdac0: nid 26 0x01813031 as 3 seq 1 Line-in Jack jack 1 loc 1 color Blue misc 0
hdac0: nid 27 0x0221401f as 1 seq 15 Headphones Jack jack 1 loc 2 color Green misc 0
hdac0: nid 28 0x411111f0 as 15 seq 0 Speaker None jack 1 loc 1 color Black misc 1
hdac0: nid 30 0x411111f0 as 15 seq 0 Speaker None jack 1 loc 1 color Black misc 1
hdac0: nid 31 0x411111f0 as 15 seq 0 Speaker None jack 1 loc 1 color Black misc 1
hdaa0: nid 0x as seq device conn jack loc color misc
hdaa0: 20 01014020 2 0 Line-out Jack 1/8 Rear Green 0
hdaa0: 21 99130110 1 0 Speaker Fixed ATAPI Onboard Unknown 1
hdaa0: 22 411111f0 15 0 Speaker None 1/8 Rear Black 1 DISA
hdaa0: 23 411111f0 15 0 Speaker None 1/8 Rear Black 1 DISA
hdaa0: 24 01a19830 3 0 Mic Jack 1/8 Rear Pink 8
hdaa0: 25 02a1983f 3 15 Mic Jack 1/8 Front Pink 8
hdaa0: 26 01813031 3 1 Line-in Jack 1/8 Rear Blue 0
hdaa0: 27 0221401f 1 15 Headphones Jack 1/8 Front Green 0
hdaa0: 28 411111f0 15 0 Speaker None 1/8 Rear Black 1 DISA
hdaa0: 30 411111f0 15 0 Speaker None 1/8 Rear Black 1 DISA
hdaa0: 31 411111f0 15 0 Speaker None 1/8 Rear Black 1 DISA
.Ed
.Pp
Here we can see, that the nodes with ID (nid) 25 and 27 are front panel
connectors (Jack, loc 2), nids 20, 24 and 26 are rear panel connectors
(Jack, loc 1) and nid 21 is a built-in speaker (Fixed, loc 25).
connectors (Jack, Front), nids 20, 24 and 26 are rear panel connectors
(Jack, Rear) and nid 21 is a built-in speaker (Fixed, Onboard).
Pins with nids 22, 23, 28, 30 and 31 will be disabled by driver due to "None"
connectivity. So the pin count and description matches to connectors that
we have.
@ -330,15 +395,15 @@ we have.
Using association (as) and sequence (seq) fields values pins are grouped into
3 associations:
.Bd -literal
hdac0: Association 0 (1) out:
hdac0: Pin nid=21 seq=0
hdac0: Pin nid=27 seq=15
hdac0: Association 1 (2) out:
hdac0: Pin nid=20 seq=0
hdac0: Association 2 (3) in:
hdac0: Pin nid=24 seq=0
hdac0: Pin nid=26 seq=1
hdac0: Pin nid=25 seq=15
hdaa0: Association 0 (1) out:
hdaa0: Pin nid=21 seq=0
hdaa0: Pin nid=27 seq=15
hdaa0: Association 1 (2) out:
hdaa0: Pin nid=20 seq=0
hdaa0: Association 2 (3) in:
hdaa0: Pin nid=24 seq=0
hdaa0: Pin nid=26 seq=1
hdaa0: Pin nid=25 seq=15
.Ed
.Pp
Each
@ -497,148 +562,14 @@ Most of controls use logarithmic scale.
.Sh HARDWARE
The
.Nm
driver supports many Intel HDA compatible audio chipsets including the
following:
driver supports controllers having PCI class 4 (multimedia) and
subclass 3 (HDA), compatible with Intel HDA specification.
.Pp
.Bl -bullet -compact
.It
ATI SB450
.It
ATI SB600
.It
Intel 631x/632xESB
.It
Intel 82801F (ICH6)
.It
Intel 82801G (ICH7)
.It
Intel 82801H (ICH8)
.It
Intel 82801I (ICH9)
.It
Intel 82801J (ICH10)
.It
Intel US15W (SCH)
.It
nVidia MCP51
.It
nVidia MCP55
.It
nVidia MCP61A
.It
nVidia MCP61B
.It
nVidia MCP63
.It
nVidia MCP65A
.It
nVidia MCP65B
.It
nVidia MCP67A
.It
nVidia MCP67B
.It
nVidia MCP68
.It
nVidia MCP69
.It
nVidia MCP73
.It
nVidia MCP78
.It
nVidia MCP79
.It
nVidia MCP89
.It
SiS 966
.It
VIA VT8251/8237A
.El
.Pp
The following and many other codecs have been verified to work:
.Pp
.Bl -bullet -compact
.It
Analog Devices AD1981HD
.It
Analog Devices AD1983
.It
Analog Devices AD1984
.It
Analog Devices AD1986A
.It
Analog Devices AD1988
.It
Analog Devices AD1988B
.It
CMedia CMI9880
.It
Conexant CX20549 (Venice)
.It
Conexant CX20551 (Waikiki)
.It
Conexant CX20561 (Hermosa)
.It
Realtek ALC260
.It
Realtek ALC262
.It
Realtek ALC268
.It
Realtek ALC660
.It
Realtek ALC861
.It
Realtek ALC861VD
.It
Realtek ALC880
.It
Realtek ALC882
.It
Realtek ALC883
.It
Realtek ALC885
.It
Realtek ALC888
.It
Realtek ALC889
.It
Sigmatel STAC9205
.It
Sigmatel STAC9220
.It
Sigmatel STAC9220D / 9223D
.It
Sigmatel STAC9221
.It
Sigmatel STAC9221D
.It
Sigmatel STAC9227D
.It
Sigmatel STAC9227X
.It
Sigmatel STAC9228D
.It
Sigmatel STAC9228X
.It
Sigmatel STAC9229D
.It
Sigmatel STAC9229X
.It
Sigmatel STAC9230D
.It
Sigmatel STAC9230X
.It
Sigmatel STAC9271D
.It
Sigmatel STAC9872AK
.It
VIA VT1708
.It
VIA VT1708B
.It
VIA VT1709
.El
The
.Nm
driver supports more then two hundred different controllers and CODECs.
There is no sense to list all of them here, as in most cases specific CODEC
configuration and wiring are more important then type of the CODEC itself.
.Sh SEE ALSO
.Xr sound 4 ,
.Xr snd_ich 4 ,
@ -665,19 +596,17 @@ This manual page was written by
and
.An Giorgos Keramidas Aq keramida@FreeBSD.org .
.Sh BUGS
A few Hardware/OEM vendors tend to screw up BIOS settings, thus
rendering the
.Nm
driver useless.
This usually results in a state where the
Some Hardware/OEM vendors tend to screw up BIOS settings or use custom
unusual CODEC wiring that create problems to the driver.
This may result in missing pcm devices, or a state where the
.Nm
driver seems to attach and work, but no sound is played.
Some cases can be solved by tuning
.Pa loader.conf
variables.
Before trying to fix problem that way, make sure that there really is a problem
and that the PCM audio device in use really corresponds to the expected
audio connector.
But before trying to fix problem that way, make sure that there really is
a problem and that the PCM audio device in use really corresponds to the
expected audio connector.
.Pp
Some vendors use non-standardized General Purpose I/O (GPIO) pins of the codec
to control external amplifiers.

4
sys/conf/files
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@ -1750,7 +1750,11 @@ dev/sound/pci/t4dwave.c optional snd_t4dwave pci
dev/sound/pci/via8233.c optional snd_via8233 pci
dev/sound/pci/via82c686.c optional snd_via82c686 pci
dev/sound/pci/vibes.c optional snd_vibes pci
dev/sound/pci/hda/hdaa.c optional snd_hda pci
dev/sound/pci/hda/hdaa_patches.c optional snd_hda pci
dev/sound/pci/hda/hdac.c optional snd_hda pci
dev/sound/pci/hda/hdac_if.m optional snd_hda pci
dev/sound/pci/hda/hdacc.c optional snd_hda pci
dev/sound/pcm/ac97.c optional sound
dev/sound/pcm/ac97_if.m optional sound
dev/sound/pcm/ac97_patch.c optional sound

1
sys/conf/kmod.mk
View File

@ -345,6 +345,7 @@ MFILES?= dev/acpica/acpi_if.m dev/acpi_support/acpi_wmi_if.m \
dev/mii/miibus_if.m dev/mvs/mvs_if.m dev/ofw/ofw_bus_if.m \
dev/pccard/card_if.m dev/pccard/power_if.m dev/pci/pci_if.m \
dev/pci/pcib_if.m dev/ppbus/ppbus_if.m dev/smbus/smbus_if.m \
dev/sound/pci/hda/hdac_if.m \
dev/sound/pcm/ac97_if.m dev/sound/pcm/channel_if.m \
dev/sound/pcm/feeder_if.m dev/sound/pcm/mixer_if.m \
dev/sound/midi/mpu_if.m dev/sound/midi/mpufoi_if.m \

8
sys/dev/sound/pci/hda/hda_reg.h
View File

@ -400,7 +400,7 @@
HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT)
#define HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE 0x80
#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK 0x1f
#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK 0x3f
#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT 0
#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG(param) \
@ -418,14 +418,10 @@
(HDA_CMD_12BIT((cad), (nid), \
HDA_CMD_VERB_SET_PIN_SENSE, (payload)))
#define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT_MASK 0x80000000
#define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT_SHIFT 31
#define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT 0x80000000
#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK 0x7fffffff
#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT 0
#define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(rsp) \
(((rsp) & HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT_MASK) >> \
HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT_SHIFT)
#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE(rsp) \
(((rsp) & HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK) >> \
HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT)

5901
sys/dev/sound/pci/hda/hdaa.c Normal file
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File diff suppressed because it is too large Load Diff

230
sys/dev/sound/pci/hda/hdaa.h Normal file
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@ -0,0 +1,230 @@
/*-7
* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
* Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
* Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* Intel High Definition Audio (Audio function quirks) driver for FreeBSD.
*/
#ifndef _HDAA_QUIRKS_H_
#define _HDAA_QUIRKS_H_
#define HDAA_GPIO_SHIFT(n) (n * 3)
#define HDAA_GPIO_MASK(n) (0x7 << (n * 3))
#define HDAA_GPIO_KEEP(n) (0x0 << (n * 3))
#define HDAA_GPIO_SET(n) (0x1 << (n * 3))
#define HDAA_GPIO_CLEAR(n) (0x2 << (n * 3))
#define HDAA_GPIO_DISABLE(n) (0x3 << (n * 3))
#define HDAA_GPIO_INPUT(n) (0x4 << (n * 3))
/* 9 - 25 = anything else */
#define HDAA_QUIRK_SOFTPCMVOL (1 << 9)
#define HDAA_QUIRK_FIXEDRATE (1 << 10)
#define HDAA_QUIRK_FORCESTEREO (1 << 11)
#define HDAA_QUIRK_EAPDINV (1 << 12)
#define HDAA_QUIRK_SENSEINV (1 << 14)
/* 26 - 31 = vrefs */
#define HDAA_QUIRK_IVREF50 (1 << 26)
#define HDAA_QUIRK_IVREF80 (1 << 27)
#define HDAA_QUIRK_IVREF100 (1 << 28)
#define HDAA_QUIRK_OVREF50 (1 << 29)
#define HDAA_QUIRK_OVREF80 (1 << 30)
#define HDAA_QUIRK_OVREF100 (1 << 31)
#define HDAA_QUIRK_IVREF (HDAA_QUIRK_IVREF50 | HDAA_QUIRK_IVREF80 | \
HDAA_QUIRK_IVREF100)
#define HDAA_QUIRK_OVREF (HDAA_QUIRK_OVREF50 | HDAA_QUIRK_OVREF80 | \
HDAA_QUIRK_OVREF100)
#define HDAA_QUIRK_VREF (HDAA_QUIRK_IVREF | HDAA_QUIRK_OVREF)
#define HDAA_AMP_VOL_DEFAULT (-1)
#define HDAA_AMP_MUTE_DEFAULT (0xffffffff)
#define HDAA_AMP_MUTE_NONE (0)
#define HDAA_AMP_MUTE_LEFT (1 << 0)
#define HDAA_AMP_MUTE_RIGHT (1 << 1)
#define HDAA_AMP_MUTE_ALL (HDAA_AMP_MUTE_LEFT | HDAA_AMP_MUTE_RIGHT)
#define HDAA_AMP_LEFT_MUTED(v) ((v) & (HDAA_AMP_MUTE_LEFT))
#define HDAA_AMP_RIGHT_MUTED(v) (((v) & HDAA_AMP_MUTE_RIGHT) >> 1)
#define HDAA_ADC_MONITOR (1 << 0)
#define HDAA_CTL_OUT 1
#define HDAA_CTL_IN 2
#define HDA_MAX_CONNS 32
#define HDA_MAX_NAMELEN 32
struct hdaa_widget {
nid_t nid;
int type;
int enable;
int nconns, selconn;
int waspin;
uint32_t pflags;
int bindas;
int bindseqmask;
int ossdev;
uint32_t ossmask;
nid_t conns[HDA_MAX_CONNS];
u_char connsenable[HDA_MAX_CONNS];
char name[HDA_MAX_NAMELEN];
struct hdaa_devinfo *devinfo;
struct {
uint32_t widget_cap;
uint32_t outamp_cap;
uint32_t inamp_cap;
uint32_t supp_stream_formats;
uint32_t supp_pcm_size_rate;
uint32_t eapdbtl;
} param;
union {
struct {
uint32_t config;
uint32_t original;
uint32_t newconf;
uint32_t cap;
uint32_t ctrl;
} pin;
} wclass;
};
struct hdaa_audio_ctl {
struct hdaa_widget *widget, *childwidget;
int enable;
int index, dir, ndir;
int mute, step, size, offset;
int left, right, forcemute;
uint32_t muted;
uint32_t ossmask, possmask;
};
/* Association is a group of pins bound for some special function. */
struct hdaa_audio_as {
u_char enable;
u_char index;
u_char dir;
u_char pincnt;
u_char fakeredir;
u_char digital;
uint16_t pinset;
nid_t hpredir;
nid_t pins[16];
nid_t dacs[2][16];
int num_chans;
int chans[2];
int unsol;
int location; /* Pins location, if all have the same */
int mixed; /* Mixed/multiplexed recording, not multichannel. */
};
struct hdaa_pcm_devinfo {
device_t dev;
struct hdaa_devinfo *devinfo;
int index;
int registered;
int playas, recas;
u_char left[SOUND_MIXER_NRDEVICES];
u_char right[SOUND_MIXER_NRDEVICES];
int chan_size;
int chan_blkcnt;
u_char digital;
};
struct hdaa_devinfo {
device_t dev;
struct mtx *lock;
nid_t nid;
nid_t startnode, endnode;
uint32_t outamp_cap;
uint32_t inamp_cap;
uint32_t supp_stream_formats;
uint32_t supp_pcm_size_rate;
uint32_t gpio_cap;
uint32_t quirks;
uint32_t newquirks;
uint32_t gpio;
uint32_t newgpio;
uint32_t gpo;
uint32_t newgpo;
int nodecnt;
int ctlcnt;
int ascnt;
int num_devs;
int num_chans;
struct hdaa_widget *widget;
struct hdaa_audio_ctl *ctl;
struct hdaa_audio_as *as;
struct hdaa_pcm_devinfo *devs;
struct hdaa_chan *chans;
struct callout poll_jack;
int poll_ival;
};
#define HDAA_CHN_RUNNING 0x00000001
#define HDAA_CHN_SUSPEND 0x00000002
struct hdaa_chan {
struct snd_dbuf *b;
struct pcm_channel *c;
struct pcmchan_caps caps;
struct hdaa_devinfo *devinfo;
struct hdaa_pcm_devinfo *pdevinfo;
uint32_t spd, fmt, fmtlist[16], pcmrates[16];
uint32_t supp_stream_formats, supp_pcm_size_rate;
uint32_t ptr, prevptr, blkcnt, blksz;
uint32_t *dmapos;
uint32_t flags;
int dir;
int off;
int sid;
int bit16, bit32;
int channels; /* Number of audio channels. */
int as; /* Number of association. */
int asindex; /* Index within association. */
nid_t io[16];
};
#define hdaa_codec_id(devinfo) \
(((uint32_t)hda_get_vendor_id(devinfo->dev) << 16) + \
hda_get_device_id(devinfo->dev))
#define hdaa_subvendor_id(devinfo) \
(((uint32_t)hda_get_subvendor_id(devinfo->dev) << 16) + \
hda_get_subdevice_id(devinfo->dev))
struct hdaa_widget *hdaa_widget_get(struct hdaa_devinfo *, nid_t);
uint32_t hdaa_widget_pin_patch(uint32_t config, const char *str);
uint32_t hdaa_gpio_patch(uint32_t gpio, const char *str);
void hdaa_patch(struct hdaa_devinfo *devinfo);
void hdaa_patch_direct(struct hdaa_devinfo *devinfo);
#endif

638
sys/dev/sound/pci/hda/hdaa_patches.c Normal file
View File

@ -0,0 +1,638 @@
/*-
* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
* Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
* Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Intel High Definition Audio (Audio function quirks) driver for FreeBSD.
*/
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_snd.h"
#endif
#include <dev/sound/pcm/sound.h>
#include <sys/ctype.h>
#include <dev/sound/pci/hda/hdac.h>
#include <dev/sound/pci/hda/hdaa.h>
#include <dev/sound/pci/hda/hda_reg.h>
SND_DECLARE_FILE("$FreeBSD$");
static const struct {
uint32_t model;
uint32_t id;
uint32_t set, unset;
uint32_t gpio;
} hdac_quirks[] = {
/*
* XXX Force stereo quirk. Monoural recording / playback
* on few codecs (especially ALC880) seems broken or
* perhaps unsupported.
*/
{ HDA_MATCH_ALL, HDA_MATCH_ALL,
HDAA_QUIRK_FORCESTEREO | HDAA_QUIRK_IVREF, 0,
0 },
{ ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
0, 0,
HDAA_GPIO_SET(0) },
{ ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660,
0, 0,
HDAA_GPIO_SET(0) },
{ ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
0, 0,
HDAA_GPIO_SET(0) },
{ ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
0, 0,
HDAA_GPIO_SET(0) },
{ ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
0, 0,
HDAA_GPIO_SET(0) },
{ ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
0, 0,
HDAA_GPIO_SET(0) },
{ ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
HDAA_QUIRK_EAPDINV, 0,
0 },
{ ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A,
HDAA_QUIRK_EAPDINV, 0,
0 },
{ ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
HDAA_QUIRK_OVREF, 0,
0 },
{ UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
HDAA_QUIRK_OVREF, 0,
0 },
/*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
HDAA_QUIRK_IVREF80, HDAA_QUIRK_IVREF50 | HDAA_QUIRK_IVREF100,
0 },*/
{ MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
0, 0,
HDAA_GPIO_SET(1) },
{ LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
HDAA_QUIRK_EAPDINV | HDAA_QUIRK_SENSEINV, 0,
0 },
{ SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
HDAA_QUIRK_EAPDINV, 0,
0 },
{ APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885,
HDAA_QUIRK_OVREF50, 0,
HDAA_GPIO_SET(0) },
{ APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
0, 0,
HDAA_GPIO_SET(0) | HDAA_GPIO_SET(1) },
{ APPLE_MACBOOKPRO55, HDA_CODEC_CS4206,
0, 0,
HDAA_GPIO_SET(1) | HDAA_GPIO_SET(3) },
{ DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X,
0, 0,
HDAA_GPIO_SET(0) },
{ DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X,
0, 0,
HDAA_GPIO_SET(2) },
{ DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X,
0, 0,
HDAA_GPIO_SET(0) },
{ HDA_MATCH_ALL, HDA_CODEC_AD1988,
HDAA_QUIRK_IVREF80, HDAA_QUIRK_IVREF50 | HDAA_QUIRK_IVREF100,
0 },
{ HDA_MATCH_ALL, HDA_CODEC_AD1988B,
HDAA_QUIRK_IVREF80, HDAA_QUIRK_IVREF50 | HDAA_QUIRK_IVREF100,
0 },
{ HDA_MATCH_ALL, HDA_CODEC_CX20549,
0, HDAA_QUIRK_FORCESTEREO,
0 }
};
#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
static void
hdac_pin_patch(struct hdaa_widget *w)
{
const char *patch = NULL;
uint32_t config, orig, id, subid;
nid_t nid = w->nid;
config = orig = w->wclass.pin.config;
id = hdaa_codec_id(w->devinfo);
subid = hdaa_subvendor_id(w->devinfo);
/* XXX: Old patches require complete review.
* Now they may create more problem then solve due to
* incorrect associations.
*/
if (id == HDA_CODEC_ALC880 && subid == LG_LW20_SUBVENDOR) {
switch (nid) {
case 26:
config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
break;
case 27:
config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
break;
default:
break;
}
} else if (id == HDA_CODEC_ALC880 &&
(subid == CLEVO_D900T_SUBVENDOR ||
subid == ASUS_M5200_SUBVENDOR)) {
/*
* Super broken BIOS
*/
switch (nid) {
case 24: /* MIC1 */
config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
break;
case 25: /* XXX MIC2 */
config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
break;
case 26: /* LINE1 */
config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
break;
case 27: /* XXX LINE2 */
config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
break;
case 28: /* CD */
config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
break;
}
} else if (id == HDA_CODEC_ALC883 &&
(subid == MSI_MS034A_SUBVENDOR ||
HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, subid))) {
switch (nid) {
case 25:
config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
break;
case 28:
config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
break;
}
} else if (id == HDA_CODEC_CX20549 && subid ==
HP_V3000_SUBVENDOR) {
switch (nid) {
case 18:
config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
break;
case 20:
config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
break;
case 21:
config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
break;
}
} else if (id == HDA_CODEC_CX20551 && subid ==
HP_DV5000_SUBVENDOR) {
switch (nid) {
case 20:
case 21:
config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
break;
}
} else if (id == HDA_CODEC_ALC861 && subid ==
ASUS_W6F_SUBVENDOR) {
switch (nid) {
case 11:
config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
break;
case 12:
case 14:
case 16:
case 31:
case 32:
config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
break;
case 15:
config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
break;
}
} else if (id == HDA_CODEC_ALC861 && subid ==
UNIWILL_9075_SUBVENDOR) {
switch (nid) {
case 15:
config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
break;
}
}
/* New patches */
if (id == HDA_CODEC_AD1986A &&
(subid == ASUS_M2NPVMX_SUBVENDOR ||
subid == ASUS_A8NVMCSM_SUBVENDOR ||
subid == ASUS_P5PL2_SUBVENDOR)) {
switch (nid) {
case 26: /* Headphones with redirection */
patch = "as=1 seq=15";
break;
case 28: /* 5.1 out => 2.0 out + 1 input */
patch = "device=Line-in as=8 seq=1";
break;
case 29: /* Can't use this as input, as the only available mic
* preamplifier is busy by front panel mic (nid 31).
* If you want to use this rear connector as mic input,
* you have to disable the front panel one. */
patch = "as=0";
break;
case 31: /* Lot of inputs configured with as=15 and unusable */
patch = "as=8 seq=3";
break;
case 32:
patch = "as=8 seq=4";
break;
case 34:
patch = "as=8 seq=5";
break;
case 36:
patch = "as=8 seq=6";
break;
}
} else if (id == HDA_CODEC_ALC260 &&
HDA_DEV_MATCH(SONY_S5_SUBVENDOR, subid)) {
switch (nid) {
case 16:
patch = "seq=15 device=Headphones";
break;
}
} else if (id == HDA_CODEC_ALC268) {
if (subid == ACER_T5320_SUBVENDOR) {
switch (nid) {
case 20: /* Headphones Jack */
patch = "as=1 seq=15";
break;
}
}
} else if (id == HDA_CODEC_CX20561 &&
subid == LENOVO_B450_SUBVENDOR) {
switch (nid) {
case 22:
patch = "as=1 seq=15";
break;
}
}
if (patch != NULL)
config = hdaa_widget_pin_patch(config, patch);
HDA_BOOTVERBOSE(
if (config != orig)
device_printf(w->devinfo->dev,
"Patching pin config nid=%u 0x%08x -> 0x%08x\n",
nid, orig, config);
);
w->wclass.pin.config = config;
}
static void
hdaa_widget_patch(struct hdaa_widget *w)
{
struct hdaa_devinfo *devinfo = w->devinfo;
uint32_t orig;
nid_t beeper = -1;
orig = w->param.widget_cap;
/* On some codecs beeper is an input pin, but it is not recordable
alone. Also most of BIOSes does not declare beeper pin.
Change beeper pin node type to beeper to help parser. */
switch (hdaa_codec_id(devinfo)) {
case HDA_CODEC_AD1882:
case HDA_CODEC_AD1883:
case HDA_CODEC_AD1984:
case HDA_CODEC_AD1984A:
case HDA_CODEC_AD1984B:
case HDA_CODEC_AD1987:
case HDA_CODEC_AD1988:
case HDA_CODEC_AD1988B:
case HDA_CODEC_AD1989B:
beeper = 26;
break;
case HDA_CODEC_ALC260:
beeper = 23;
break;
}
if (hda_get_vendor_id(devinfo->dev) == REALTEK_VENDORID &&
hdaa_codec_id(devinfo) != HDA_CODEC_ALC260)
beeper = 29;
if (w->nid == beeper) {
w->param.widget_cap &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
w->param.widget_cap |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
w->waspin = 1;
}
HDA_BOOTVERBOSE(
if (w->param.widget_cap != orig) {
device_printf(w->devinfo->dev,
"Patching widget caps nid=%u 0x%08x -> 0x%08x\n",
w->nid, orig, w->param.widget_cap);
}
);
if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
hdac_pin_patch(w);
}
void
hdaa_patch(struct hdaa_devinfo *devinfo)
{
struct hdaa_widget *w;
uint32_t id, subid;
int i;
id = hdaa_codec_id(devinfo);
subid = hdaa_subvendor_id(devinfo);
/*
* Quirks
*/
for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subid) &&
HDA_DEV_MATCH(hdac_quirks[i].id, id)))
continue;
if (hdac_quirks[i].set != 0)
devinfo->quirks |=
hdac_quirks[i].set;
if (hdac_quirks[i].unset != 0)
devinfo->quirks &=
~(hdac_quirks[i].unset);
}
/* Apply per-widget patch. */
for (i = devinfo->startnode; i < devinfo->endnode; i++) {
w = hdaa_widget_get(devinfo, i);
if (w == NULL)
continue;
hdaa_widget_patch(w);
}
switch (id) {
case HDA_CODEC_AD1983:
/*
* This CODEC has several possible usages, but none
* fit the parser best. Help parser to choose better.
*/
/* Disable direct unmixed playback to get pcm volume. */
w = hdaa_widget_get(devinfo, 5);
if (w != NULL)
w->connsenable[0] = 0;
w = hdaa_widget_get(devinfo, 6);
if (w != NULL)
w->connsenable[0] = 0;
w = hdaa_widget_get(devinfo, 11);
if (w != NULL)
w->connsenable[0] = 0;
/* Disable mic and line selectors. */
w = hdaa_widget_get(devinfo, 12);
if (w != NULL)
w->connsenable[1] = 0;
w = hdaa_widget_get(devinfo, 13);
if (w != NULL)
w->connsenable[1] = 0;
/* Disable recording from mono playback mix. */
w = hdaa_widget_get(devinfo, 20);
if (w != NULL)
w->connsenable[3] = 0;
break;
case HDA_CODEC_AD1986A:
/*
* This CODEC has overcomplicated input mixing.
* Make some cleaning there.
*/
/* Disable input mono mixer. Not needed and not supported. */
w = hdaa_widget_get(devinfo, 43);
if (w != NULL)
w->enable = 0;
/* Disable any with any input mixing mesh. Use separately. */
w = hdaa_widget_get(devinfo, 39);
if (w != NULL)
w->enable = 0;
w = hdaa_widget_get(devinfo, 40);
if (w != NULL)
w->enable = 0;
w = hdaa_widget_get(devinfo, 41);
if (w != NULL)
w->enable = 0;
w = hdaa_widget_get(devinfo, 42);
if (w != NULL)
w->enable = 0;
/* Disable duplicate mixer node connector. */
w = hdaa_widget_get(devinfo, 15);
if (w != NULL)
w->connsenable[3] = 0;
/* There is only one mic preamplifier, use it effectively. */
w = hdaa_widget_get(devinfo, 31);
if (w != NULL) {
if ((w->wclass.pin.config &
HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) {
w = hdaa_widget_get(devinfo, 16);
if (w != NULL)
w->connsenable[2] = 0;
} else {
w = hdaa_widget_get(devinfo, 15);
if (w != NULL)
w->connsenable[0] = 0;
}
}
w = hdaa_widget_get(devinfo, 32);
if (w != NULL) {
if ((w->wclass.pin.config &
HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) {
w = hdaa_widget_get(devinfo, 16);
if (w != NULL)
w->connsenable[0] = 0;
} else {
w = hdaa_widget_get(devinfo, 15);
if (w != NULL)
w->connsenable[1] = 0;
}
}
if (subid == ASUS_A8X_SUBVENDOR) {
/*
* This is just plain ridiculous.. There
* are several A8 series that share the same
* pci id but works differently (EAPD).
*/
w = hdaa_widget_get(devinfo, 26);
if (w != NULL && w->type ==
HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
(w->wclass.pin.config &
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) !=
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
devinfo->quirks &=
~HDAA_QUIRK_EAPDINV;
}
break;
case HDA_CODEC_AD1981HD:
/*
* This CODEC has very unusual design with several
* points inappropriate for the present parser.
*/
/* Disable recording from mono playback mix. */
w = hdaa_widget_get(devinfo, 21);
if (w != NULL)
w->connsenable[3] = 0;
/* Disable rear to front mic mixer, use separately. */
w = hdaa_widget_get(devinfo, 31);
if (w != NULL)
w->enable = 0;
/* Disable direct playback, use mixer. */
w = hdaa_widget_get(devinfo, 5);
if (w != NULL)
w->connsenable[0] = 0;
w = hdaa_widget_get(devinfo, 6);
if (w != NULL)
w->connsenable[0] = 0;
w = hdaa_widget_get(devinfo, 9);
if (w != NULL)
w->connsenable[0] = 0;
w = hdaa_widget_get(devinfo, 24);
if (w != NULL)
w->connsenable[0] = 0;
break;
case HDA_CODEC_CX20582:
case HDA_CODEC_CX20583:
case HDA_CODEC_CX20584:
case HDA_CODEC_CX20585:
case HDA_CODEC_CX20590:
/*
* These codecs have extra connectivity on record side
* too reach for the present parser.
*/
w = hdaa_widget_get(devinfo, 20);
if (w != NULL)
w->connsenable[1] = 0;
w = hdaa_widget_get(devinfo, 21);
if (w != NULL)
w->connsenable[1] = 0;
w = hdaa_widget_get(devinfo, 22);
if (w != NULL)
w->connsenable[0] = 0;
break;
case HDA_CODEC_VT1708S_0:
case HDA_CODEC_VT1708S_1:
case HDA_CODEC_VT1708S_2:
case HDA_CODEC_VT1708S_3:
case HDA_CODEC_VT1708S_4:
case HDA_CODEC_VT1708S_5:
case HDA_CODEC_VT1708S_6:
case HDA_CODEC_VT1708S_7:
/*
* These codecs have hidden mic boost controls.
*/
w = hdaa_widget_get(devinfo, 26);
if (w != NULL)
w->param.inamp_cap =
(40 << HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT) |
(3 << HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT) |
(0 << HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT);
w = hdaa_widget_get(devinfo, 30);
if (w != NULL)
w->param.inamp_cap =
(40 << HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT) |
(3 << HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT) |
(0 << HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT);
break;
}
}
void
hdaa_patch_direct(struct hdaa_devinfo *devinfo)
{
device_t dev = devinfo->dev;
uint32_t id, subid, val;
id = hdaa_codec_id(devinfo);
subid = hdaa_subvendor_id(devinfo);
switch (id) {
case HDA_CODEC_VT1708S_0:
case HDA_CODEC_VT1708S_1:
case HDA_CODEC_VT1708S_2:
case HDA_CODEC_VT1708S_3:
case HDA_CODEC_VT1708S_4:
case HDA_CODEC_VT1708S_5:
case HDA_CODEC_VT1708S_6:
case HDA_CODEC_VT1708S_7:
/* Enable Mic Boost Volume controls. */
hda_command(dev, HDA_CMD_12BIT(0, devinfo->nid,
0xf98, 0x01));
/* Don't bypass mixer. */
hda_command(dev, HDA_CMD_12BIT(0, devinfo->nid,
0xf88, 0xc0));
break;
}
if (subid == APPLE_INTEL_MAC)
hda_command(dev, HDA_CMD_12BIT(0, devinfo->nid,
0x7e7, 0));
if (id == HDA_CODEC_ALC269) {
if (subid == 0x104316e3 || subid == 0x1043831a ||
subid == 0x1043834a || subid == 0x10438398 ||
subid == 0x104383ce) {
/*
* The ditital mics on some Asus laptops produce
* differential signals instead of expected stereo.
* That results in silence if downmix it to mono.
* To workaround, make codec to handle signal as mono.
*/
hda_command(dev, HDA_CMD_SET_COEFF_INDEX(0, 0x20, 0x07));
val = hda_command(dev, HDA_CMD_GET_PROCESSING_COEFF(0, 0x20));
hda_command(dev, HDA_CMD_SET_COEFF_INDEX(0, 0x20, 0x07));
hda_command(dev, HDA_CMD_SET_PROCESSING_COEFF(0, 0x20, val|0x80));
}
}
}

7860
sys/dev/sound/pci/hda/hdac.c
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File diff suppressed because it is too large Load Diff

542
sys/dev/sound/pci/hda/hdac.h
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@ -29,40 +29,546 @@
#ifndef _HDAC_H_
#define _HDAC_H_
#include "hdac_if.h"
#if 0
/****************************************************************************
* Miscellanious defines
****************************************************************************/
/* Controller models */
#define HDA_MODEL_CONSTRUCT(vendor, model) \
(((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
/* Intel */
#define INTEL_VENDORID 0x8086
#define HDA_INTEL_CPT HDA_MODEL_CONSTRUCT(INTEL, 0x1c20)
#define HDA_INTEL_PATSBURG HDA_MODEL_CONSTRUCT(INTEL, 0x1d20)
#define HDA_INTEL_PPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x1e20)
#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e)
#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e)
#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e)
#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56)
#define HDA_INTEL_PCH2 HDA_MODEL_CONSTRUCT(INTEL, 0x3b57)
#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b)
#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
/* Nvidia */
#define NVIDIA_VENDORID 0x10de
#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c)
#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d)
#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774)
#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775)
#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776)
#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777)
#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc)
#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd)
#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0)
#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1)
#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2)
#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3)
#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94)
#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95)
#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96)
#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97)
#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
/* ATI */
#define ATI_VENDORID 0x1002
#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b)
#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919)
#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f)
#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00)
#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08)
#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10)
#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18)
#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20)
#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28)
#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30)
#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38)
#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40)
#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48)
#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
/* RDC */
#define RDC_VENDORID 0x17f3
#define HDA_RDC_M3010 HDA_MODEL_CONSTRUCT(RDC, 0x3010)
/* VIA */
#define VIA_VENDORID 0x1106
#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
/* SiS */
#define SIS_VENDORID 0x1039
#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
/* ULI */
#define ULI_VENDORID 0x10b9
#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461)
#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff)
/* OEM/subvendors */
/* Intel */
#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
/* HP/Compaq */
#define HP_VENDORID 0x103c
#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801)
#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802)
#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
/* What is wrong with XN 2563 anyway? (Got the picture ?) */
#define HP_NX6325_SUBVENDORX 0x103c30b0
/* Dell */
#define DELL_VENDORID 0x1028
#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9)
#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227)
#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228)
#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
/* Clevo */
#define CLEVO_VENDORID 0x1558
#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
/* Acer */
#define ACER_VENDORID 0x1025
#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127)
#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f)
#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133)
#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b)
#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f)
#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
/* Asus */
#define ASUS_VENDORID 0x1043
#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339)
#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f)
#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
/* IBM / Lenovo */
#define IBM_VENDORID 0x1014
#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
/* Lenovo */
#define LENOVO_VENDORID 0x17aa
#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e)
#define LENOVO_B450_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x3a0d)
#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)
#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
/* Samsung */
#define SAMSUNG_VENDORID 0x144d
#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
/* Medion ? */
#define MEDION_VENDORID 0x161f
#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
/* Apple Computer Inc. */
#define APPLE_VENDORID 0x106b
#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1)
/* Sony */
#define SONY_VENDORID 0x104d
#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc)
#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff)
/*
* Apple Intel MacXXXX seems using Sigmatel codec/vendor id
* instead of their own, which is beyond my comprehension
* (see HDA_CODEC_STAC9221 below).
*/
#define APPLE_INTEL_MAC 0x76808384
#define APPLE_MACBOOKPRO55 0xcb7910de
/* LG Electronics */
#define LG_VENDORID 0x1854
#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
/* Fujitsu Siemens */
#define FS_VENDORID 0x1734
#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd)
#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
/* Fujitsu Limited */
#define FL_VENDORID 0x10cf
#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326)
#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d)
#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff)
/* Toshiba */
#define TOSHIBA_VENDORID 0x1179
#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01)
#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
/* Micro-Star International (MSI) */
#define MSI_VENDORID 0x1462
#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a)
#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
/* Giga-Byte Technology */
#define GB_VENDORID 0x1458
#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022)
#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff)
/* Uniwill ? */
#define UNIWILL_VENDORID 0x1584
#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
/* All codecs you can eat... */
#define HDA_CODEC_CONSTRUCT(vendor, id) \
(((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
/* Cirrus Logic */
#define CIRRUSLOGIC_VENDORID 0x1013
#define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206)
#define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207)
#define HDA_CODEC_CS4210 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4210)
#define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff)
/* Realtek */
#define REALTEK_VENDORID 0x10ec
#define HDA_CODEC_ALC221 HDA_CODEC_CONSTRUCT(REALTEK, 0x0221)
#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267)
#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)
#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269)
#define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270)
#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272)
#define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273)
#define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275)
#define HDA_CODEC_ALC276 HDA_CODEC_CONSTRUCT(REALTEK, 0x0276)
#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662)
#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663)
#define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665)
#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
#define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887)
#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889)
#define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892)
#define HDA_CODEC_ALC899 HDA_CODEC_CONSTRUCT(REALTEK, 0x0899)
#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
/* Analog Devices */
#define ANALOGDEVICES_VENDORID 0x11d4
#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a)
#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882)
#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883)
#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884)
#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a)
#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b)
#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984)
#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987)
#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a)
#define HDA_CODEC_AD1989A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989a)
#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b)
#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
/* CMedia */
#define CMEDIA_VENDORID 0x434d
#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
/* Sigmatel */
#define SIGMATEL_VENDORID 0x8384
#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612)
#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613)
#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614)
#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615)
#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616)
#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617)
#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619)
#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620)
#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621)
#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622)
#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623)
#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624)
#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625)
#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626)
#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628)
#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629)
#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634)
#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636)
#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638)
#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639)
#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645)
#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646)
#define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661)
#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662)
#define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664)
#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682)
#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691)
#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698)
#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699)
#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0)
#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1)
#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2)
#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3)
#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880)
#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882)
#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
/* IDT */
#define IDT_VENDORID 0x111d
#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603)
#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604)
#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605)
#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608)
#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674)
#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675)
#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676)
#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0)
#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2)
#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6)
#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4)
#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5)
#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff)
/* Silicon Image */
#define SII_VENDORID 0x1095
#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390)
#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392)
#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff)
/* Lucent/Agere */
#define AGERE_VENDORID 0x11c1
#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff)
/* Conexant */
#define CONEXANT_VENDORID 0x14f1
#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051)
#define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066)
#define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067)
#define HDA_CODEC_CX20584 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5068)
#define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069)
#define HDA_CODEC_CX20588 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506c)
#define HDA_CODEC_CX20590 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506e)
#define HDA_CODEC_CX20631 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5097)
#define HDA_CODEC_CX20632 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5098)
#define HDA_CODEC_CX20641 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a1)
#define HDA_CODEC_CX20642 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a2)
#define HDA_CODEC_CX20651 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ab)
#define HDA_CODEC_CX20652 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ac)
#define HDA_CODEC_CX20664 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b8)
#define HDA_CODEC_CX20665 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b9)
#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
/* VIA */
#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720)
#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721)
#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722)
#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723)
#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724)
#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725)
#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726)
#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727)
#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397)
#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397)
#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397)
#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397)
#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397)
#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397)
#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397)
#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397)
#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398)
#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398)
#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398)
#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398)
#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398)
#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398)
#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398)
#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398)
#define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433)
#define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721)
#define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428)
#define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428)
#define HDA_CODEC_VT1802_0 HDA_CODEC_CONSTRUCT(VIA, 0x0446)
#define HDA_CODEC_VT1802_1 HDA_CODEC_CONSTRUCT(VIA, 0x8446)
#define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448)
#define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440)
#define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441)
#define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438)
#define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438)
#define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441)
#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
/* ATI */
#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c)
#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919)
#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a)
#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01)
#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff)
/* NVIDIA */
#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002)
#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006)
#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007)
#define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a)
#define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b)
#define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c)
#define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d)
#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067)
#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001)
#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff)
/* INTEL */
#define HDA_CODEC_INTELIP HDA_CODEC_CONSTRUCT(INTEL, 0x0054)
#define HDA_CODEC_INTELBL HDA_CODEC_CONSTRUCT(INTEL, 0x2801)
#define HDA_CODEC_INTELCA HDA_CODEC_CONSTRUCT(INTEL, 0x2802)
#define HDA_CODEC_INTELEL HDA_CODEC_CONSTRUCT(INTEL, 0x2803)
#define HDA_CODEC_INTELIP2 HDA_CODEC_CONSTRUCT(INTEL, 0x2804)
#define HDA_CODEC_INTELCPT HDA_CODEC_CONSTRUCT(INTEL, 0x2805)
#define HDA_CODEC_INTELPPT HDA_CODEC_CONSTRUCT(INTEL, 0x2806)
#define HDA_CODEC_INTELCL HDA_CODEC_CONSTRUCT(INTEL, 0x29fb)
#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff)
/****************************************************************************
* Helper Macros
****************************************************************************/
#define HDA_DMA_ALIGNMENT 128
#define HDA_GPIO_MAX 8
#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
(fl) == 0xffffffff || \
(((fl) & 0xffff0000) == 0xffff0000 && \
((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
(((fl) & 0x0000ffff) == 0x0000ffff && \
((fl) & 0xffff0000) == ((v) & 0xffff0000)))
#define HDA_MATCH_ALL 0xffffffff
#define HDA_INVALID 0xffffffff
#define HDA_BOOTVERBOSE(stmt) do { \
if (bootverbose != 0 || snd_verbose > 3) { \
stmt \
} \
} while (0)
#define HDA_BOOTHVERBOSE(stmt) do { \
if (snd_verbose > 3) { \
stmt \
} \
} while (0)
#define hda_command(dev, verb) \
HDAC_CODEC_COMMAND(device_get_parent(dev), (dev), (verb))
typedef int nid_t;
/****************************************************************************
* Simplified Accessors for HDA devices
****************************************************************************/
enum hdac_device_ivars {
HDAC_IVAR_CODEC_ID,
HDAC_IVAR_NODE_ID,
HDAC_IVAR_VENDOR_ID,
HDAC_IVAR_DEVICE_ID,
HDAC_IVAR_REVISION_ID,
HDAC_IVAR_STEPPING_ID,
HDAC_IVAR_NODE_TYPE,
HDA_IVAR_CODEC_ID,
HDA_IVAR_NODE_ID,
HDA_IVAR_VENDOR_ID,
HDA_IVAR_DEVICE_ID,
HDA_IVAR_REVISION_ID,
HDA_IVAR_STEPPING_ID,
HDA_IVAR_SUBVENDOR_ID,
HDA_IVAR_SUBDEVICE_ID,
HDA_IVAR_SUBSYSTEM_ID,
HDA_IVAR_NODE_TYPE,
HDA_IVAR_DMA_NOCACHE,
};
#define HDAC_ACCESSOR(var, ivar, type) \
__BUS_ACCESSOR(hdac, var, HDAC, ivar, type)
#define HDA_ACCESSOR(var, ivar, type) \
__BUS_ACCESSOR(hda, var, HDA, ivar, type)
HDAC_ACCESSOR(codec_id, CODEC_ID, uint8_t);
HDAC_ACCESSOR(node_id, NODE_ID, uint8_t);
HDAC_ACCESSOR(vendor_id, VENDOR_ID, uint16_t);
HDAC_ACCESSOR(device_id, DEVICE_ID, uint16_t);
HDAC_ACCESSOR(revision_id, REVISION_ID, uint8_t);
HDAC_ACCESSOR(stepping_id, STEPPING_ID, uint8_t);
HDAC_ACCESSOR(node_type, NODE_TYPE, uint8_t);
#endif
HDA_ACCESSOR(codec_id, CODEC_ID, uint8_t);
HDA_ACCESSOR(node_id, NODE_ID, uint8_t);
HDA_ACCESSOR(vendor_id, VENDOR_ID, uint16_t);
HDA_ACCESSOR(device_id, DEVICE_ID, uint16_t);
HDA_ACCESSOR(revision_id, REVISION_ID, uint8_t);
HDA_ACCESSOR(stepping_id, STEPPING_ID, uint8_t);
HDA_ACCESSOR(subvendor_id, SUBVENDOR_ID, uint16_t);
HDA_ACCESSOR(subdevice_id, SUBDEVICE_ID, uint16_t);
HDA_ACCESSOR(node_type, NODE_TYPE, uint8_t);
HDA_ACCESSOR(dma_nocache, DMA_NOCACHE, uint8_t);
#define PCIS_MULTIMEDIA_HDA 0x03

114
sys/dev/sound/pci/hda/hdac_if.m Normal file
View File

@ -0,0 +1,114 @@
# Copyright (c) 2012 Alexander Motin <mav@FreeBSD.org>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer,
# without modification, immediately at the beginning of the file.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# $FreeBSD$
#include <sys/rman.h>
INTERFACE hdac;
METHOD struct mtx * get_mtx {
device_t dev;
device_t child;
};
METHOD uint32_t codec_command {
device_t dev;
device_t child;
uint32_t verb;
};
METHOD int stream_alloc {
device_t dev;
device_t child;
int dir;
int format;
uint32_t **dmapos;
};
METHOD void stream_free {
device_t dev;
device_t child;
int dir;
int stream;
};
METHOD int stream_start {
device_t dev;
device_t child;
int dir;
int stream;
bus_addr_t buf;
int blksz;
int blkcnt;
};
METHOD void stream_stop {
device_t dev;
device_t child;
int dir;
int stream;
};
METHOD void stream_reset {
device_t dev;
device_t child;
int dir;
int stream;
};
METHOD uint32_t stream_getptr {
device_t dev;
device_t child;
int dir;
int stream;
};
METHOD void stream_intr {
device_t dev;
int dir;
int stream;
};
METHOD int unsol_alloc {
device_t dev;
device_t child;
int wanted;
};
METHOD void unsol_free {
device_t dev;
device_t child;
int tag;
};
METHOD void unsol_intr {
device_t dev;
uint32_t resp;
};
METHOD void pindump {
device_t dev;
};

220
sys/dev/sound/pci/hda/hdac_private.h
View File

@ -1,5 +1,6 @@
/*-
* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
* Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -29,15 +30,11 @@
#ifndef _HDAC_PRIVATE_H_
#define _HDAC_PRIVATE_H_
/****************************************************************************
* Miscellaneous defines
****************************************************************************/
#define HDAC_DMA_ALIGNMENT 128
#define HDAC_CODEC_MAX 16
#define HDAC_MTX_NAME "hdac driver mutex"
/****************************************************************************
* Helper Macros
****************************************************************************/
@ -82,7 +79,6 @@
#define HDAC_BSDBDPL(sc, n) (_HDAC_BSDBDPL((n), (sc)->num_iss, (sc)->num_oss))
#define HDAC_BSDBDPU(sc, n) (_HDAC_BSDBDPU((n), (sc)->num_iss, (sc)->num_oss))
/****************************************************************************
* Custom hdac malloc type
****************************************************************************/
@ -145,22 +141,6 @@ struct hdac_rirb {
(((response_ex) & HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK) >> \
HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET)
/****************************************************************************
* struct hdac_command_list
*
* This structure holds the list of verbs that are to be sent to the codec
* via the corb and the responses received via the rirb. It's allocated by
* the codec driver and is owned by it.
****************************************************************************/
struct hdac_command_list {
int num_commands;
uint32_t *verbs;
uint32_t *responses;
};
typedef int nid_t;
struct hdac_softc;
struct hdac_bdle {
volatile uint32_t addrl;
volatile uint32_t addrh;
@ -168,181 +148,36 @@ struct hdac_bdle {
volatile uint32_t ioc;
} __packed;
#define HDA_MAX_CONNS 32
#define HDA_MAX_NAMELEN 32
struct hdac_widget {
nid_t nid;
int type;
int enable;
int nconns, selconn;
int waspin;
uint32_t pflags;
int bindas;
int bindseqmask;
int ossdev;
uint32_t ossmask;
nid_t conns[HDA_MAX_CONNS];
u_char connsenable[HDA_MAX_CONNS];
char name[HDA_MAX_NAMELEN];
struct hdac_devinfo *devinfo;
struct {
uint32_t widget_cap;
uint32_t outamp_cap;
uint32_t inamp_cap;
uint32_t supp_stream_formats;
uint32_t supp_pcm_size_rate;
uint32_t eapdbtl;
} param;
union {
struct {
uint32_t config;
uint32_t cap;
uint32_t ctrl;
} pin;
} wclass;
struct hdac_stream {
device_t dev;
struct hdac_dma bdl;
int dir;
int stream;
int blksz;
int running;
uint16_t format;
};
struct hdac_audio_ctl {
struct hdac_widget *widget, *childwidget;
int enable;
int index, dir, ndir;
int mute, step, size, offset;
int left, right, forcemute;
uint32_t muted;
uint32_t ossmask, possmask;
};
/* Association is a group of pins bound for some special function. */
struct hdac_audio_as {
u_char enable;
u_char index;
u_char dir;
u_char pincnt;
u_char fakeredir;
u_char digital;
uint16_t pinset;
nid_t hpredir;
nid_t pins[16];
nid_t dacs[16];
int chan;
};
struct hdac_pcm_devinfo {
device_t dev;
struct hdac_devinfo *devinfo;
int index;
int registered;
int play, rec;
u_char left[SOUND_MIXER_NRDEVICES];
u_char right[SOUND_MIXER_NRDEVICES];
int chan_size;
int chan_blkcnt;
u_char digital;
};
/****************************************************************************
* struct hdac_devinfo
*
* Holds all the parameters of a given codec function group. This is stored
* in the ivar of each child of the hdac bus
****************************************************************************/
struct hdac_devinfo {
uint8_t node_type;
nid_t nid;
nid_t startnode, endnode;
int nodecnt;
struct hdac_codec *codec;
struct hdac_widget *widget;
union {
struct {
uint32_t outamp_cap;
uint32_t inamp_cap;
uint32_t supp_stream_formats;
uint32_t supp_pcm_size_rate;
int ctlcnt, ascnt;
struct hdac_audio_ctl *ctl;
struct hdac_audio_as *as;
uint32_t quirks;
uint32_t gpio;
struct hdac_pcm_devinfo *devs;
int num_devs;
} audio;
/* XXX undefined: modem, hdmi. */
} function;
};
#define HDAC_CHN_RUNNING 0x00000001
#define HDAC_CHN_SUSPEND 0x00000002
struct hdac_chan {
struct snd_dbuf *b;
struct pcm_channel *c;
struct pcmchan_caps caps;
struct hdac_devinfo *devinfo;
struct hdac_pcm_devinfo *pdevinfo;
struct hdac_dma bdl_dma;
uint32_t spd, fmt, fmtlist[16], pcmrates[16];
uint32_t supp_stream_formats, supp_pcm_size_rate;
uint32_t ptr, prevptr, blkcnt, blksz;
uint32_t *dmapos;
uint32_t flags;
int dir;
int off;
int sid;
int bit16, bit32;
int as;
nid_t io[16];
};
/****************************************************************************
* struct hdac_codec
*
****************************************************************************/
struct hdac_codec {
int verbs_sent;
int responses_received;
nid_t cad;
uint16_t vendor_id;
uint16_t device_id;
uint8_t revision_id;
uint8_t stepping_id;
struct hdac_command_list *commands;
struct hdac_softc *sc;
struct hdac_devinfo *fgs;
int num_fgs;
};
/****************************************************************************
* struct hdac_softc
*
* This structure holds the current state of the hdac driver.
****************************************************************************/
#define HDAC_F_DMA_NOCACHE 0x00000001
#define HDAC_F_MSI 0x00000002
struct hdac_softc {
device_t dev;
device_t hdabus;
struct mtx *lock;
struct intr_config_hook intrhook;
struct hdac_mem mem;
struct hdac_irq irq;
uint32_t pci_subvendor;
uint32_t quirks_on;
uint32_t quirks_off;
uint32_t flags;
#define HDAC_F_DMA_NOCACHE 0x00000001
struct hdac_chan *chans;
int num_chans;
int num_iss;
int num_oss;
int num_bss;
int num_ss;
int num_sdo;
int support_64bit;
int streamcnt;
int corb_size;
struct hdac_dma corb_dma;
@ -356,18 +191,13 @@ struct hdac_softc {
bus_dma_tag_t chan_dmat;
/*
* Polling
*/
/* Polling */
int polling;
int poll_ticks;
int poll_ival;
struct callout poll_hda;
struct callout poll_hdac;
struct callout poll_jack;
struct callout poll_callout;
int unsol_registered;
struct task unsolq_task;
#define HDAC_UNSOLQ_MAX 64
#define HDAC_UNSOLQ_READY 0
#define HDAC_UNSOLQ_BUSY 1
@ -376,13 +206,17 @@ struct hdac_softc {
int unsolq_st;
uint32_t unsolq[HDAC_UNSOLQ_MAX];
struct hdac_codec *codecs[HDAC_CODEC_MAX];
struct hdac_stream *streams;
struct {
device_t dev;
uint16_t vendor_id;
uint16_t device_id;
uint8_t revision_id;
uint8_t stepping_id;
int pending;
uint32_t response;
} codecs[HDAC_CODEC_MAX];
};
/****************************************************************************
* struct hdac_command flags
****************************************************************************/
#define HDAC_COMMAND_FLAG_WAITOK 0x0000
#define HDAC_COMMAND_FLAG_NOWAIT 0x0001
#endif

8
sys/dev/sound/pci/hda/hdac_reg.h
View File

@ -254,10 +254,10 @@
#define HDAC_SDCTL_IOCE 0x000004
#define HDAC_SDCTL_FEIE 0x000008
#define HDAC_SDCTL_DEIE 0x000010
#define HDAC_SDCTL_STRIPE_MASK 0x030000
#define HDAC_SDCTL_STRIPE_SHIFT 16
#define HDAC_SDCTL_TP 0x040000
#define HDAC_SDCTL_DIR 0x080000
#define HDAC_SDCTL2_STRIPE_MASK 0x03
#define HDAC_SDCTL2_STRIPE_SHIFT 0
#define HDAC_SDCTL2_TP 0x04
#define HDAC_SDCTL2_DIR 0x08
#define HDAC_SDCTL2_STRM_MASK 0xf0
#define HDAC_SDCTL2_STRM_SHIFT 4

662
sys/dev/sound/pci/hda/hdacc.c Normal file
View File

@ -0,0 +1,662 @@
/*-
* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
* Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
* Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Intel High Definition Audio (CODEC) driver for FreeBSD.
*/
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_snd.h"
#endif
#include <dev/sound/pcm/sound.h>
#include <sys/ctype.h>
#include <dev/sound/pci/hda/hda_reg.h>
#include <dev/sound/pci/hda/hdac.h>
SND_DECLARE_FILE("$FreeBSD$");
struct hdacc_fg {
device_t dev;
nid_t nid;
uint8_t type;
uint32_t subsystem_id;
};
struct hdacc_softc {
device_t dev;
struct mtx *lock;
nid_t cad;
device_t streams[2][16];
device_t tags[64];
int fgcnt;
struct hdacc_fg *fgs;
};
#define hdacc_lock(codec) snd_mtxlock((codec)->lock)
#define hdacc_unlock(codec) snd_mtxunlock((codec)->lock)
#define hdacc_lockassert(codec) snd_mtxassert((codec)->lock)
#define hdacc_lockowned(codec) mtx_owned((codec)->lock)
MALLOC_DEFINE(M_HDACC, "hdacc", "HDA CODEC");
/* CODECs */
static const struct {
uint32_t id;
uint16_t revid;
char *name;
} hdacc_codecs[] = {
{ HDA_CODEC_CS4206, 0, "Cirrus Logic CS4206" },
{ HDA_CODEC_CS4207, 0, "Cirrus Logic CS4207" },
{ HDA_CODEC_CS4210, 0, "Cirrus Logic CS4210" },
{ HDA_CODEC_ALC221, 0, "Realtek ALC221" },
{ HDA_CODEC_ALC260, 0, "Realtek ALC260" },
{ HDA_CODEC_ALC262, 0, "Realtek ALC262" },
{ HDA_CODEC_ALC267, 0, "Realtek ALC267" },
{ HDA_CODEC_ALC268, 0, "Realtek ALC268" },
{ HDA_CODEC_ALC269, 0, "Realtek ALC269" },
{ HDA_CODEC_ALC270, 0, "Realtek ALC270" },
{ HDA_CODEC_ALC272, 0, "Realtek ALC272" },
{ HDA_CODEC_ALC273, 0, "Realtek ALC273" },
{ HDA_CODEC_ALC275, 0, "Realtek ALC275" },
{ HDA_CODEC_ALC276, 0, "Realtek ALC276" },
{ HDA_CODEC_ALC660, 0, "Realtek ALC660-VD" },
{ HDA_CODEC_ALC662, 0x0002, "Realtek ALC662 rev2" },
{ HDA_CODEC_ALC662, 0, "Realtek ALC662" },
{ HDA_CODEC_ALC663, 0, "Realtek ALC663" },
{ HDA_CODEC_ALC665, 0, "Realtek ALC665" },
{ HDA_CODEC_ALC861, 0x0340, "Realtek ALC660" },
{ HDA_CODEC_ALC861, 0, "Realtek ALC861" },
{ HDA_CODEC_ALC861VD, 0, "Realtek ALC861-VD" },
{ HDA_CODEC_ALC880, 0, "Realtek ALC880" },
{ HDA_CODEC_ALC882, 0, "Realtek ALC882" },
{ HDA_CODEC_ALC883, 0, "Realtek ALC883" },
{ HDA_CODEC_ALC885, 0x0101, "Realtek ALC889A" },
{ HDA_CODEC_ALC885, 0x0103, "Realtek ALC889A" },
{ HDA_CODEC_ALC885, 0, "Realtek ALC885" },
{ HDA_CODEC_ALC887, 0, "Realtek ALC887" },
{ HDA_CODEC_ALC888, 0x0101, "Realtek ALC1200" },
{ HDA_CODEC_ALC888, 0, "Realtek ALC888" },
{ HDA_CODEC_ALC889, 0, "Realtek ALC889" },
{ HDA_CODEC_ALC892, 0, "Realtek ALC892" },
{ HDA_CODEC_ALC899, 0, "Realtek ALC899" },
{ HDA_CODEC_AD1882, 0, "Analog Devices AD1882" },
{ HDA_CODEC_AD1882A, 0, "Analog Devices AD1882A" },
{ HDA_CODEC_AD1883, 0, "Analog Devices AD1883" },
{ HDA_CODEC_AD1884, 0, "Analog Devices AD1884" },
{ HDA_CODEC_AD1884A, 0, "Analog Devices AD1884A" },
{ HDA_CODEC_AD1981HD, 0, "Analog Devices AD1981HD" },
{ HDA_CODEC_AD1983, 0, "Analog Devices AD1983" },
{ HDA_CODEC_AD1984, 0, "Analog Devices AD1984" },
{ HDA_CODEC_AD1984A, 0, "Analog Devices AD1984A" },
{ HDA_CODEC_AD1984B, 0, "Analog Devices AD1984B" },
{ HDA_CODEC_AD1986A, 0, "Analog Devices AD1986A" },
{ HDA_CODEC_AD1987, 0, "Analog Devices AD1987" },
{ HDA_CODEC_AD1988, 0, "Analog Devices AD1988A" },
{ HDA_CODEC_AD1988B, 0, "Analog Devices AD1988B" },
{ HDA_CODEC_AD1989A, 0, "Analog Devices AD1989A" },
{ HDA_CODEC_AD1989B, 0, "Analog Devices AD1989B" },
{ HDA_CODEC_CMI9880, 0, "CMedia CMI9880" },
{ HDA_CODEC_CXD9872RDK, 0, "Sigmatel CXD9872RD/K" },
{ HDA_CODEC_CXD9872AKD, 0, "Sigmatel CXD9872AKD" },
{ HDA_CODEC_STAC9200D, 0, "Sigmatel STAC9200D" },
{ HDA_CODEC_STAC9204X, 0, "Sigmatel STAC9204X" },
{ HDA_CODEC_STAC9204D, 0, "Sigmatel STAC9204D" },
{ HDA_CODEC_STAC9205X, 0, "Sigmatel STAC9205X" },
{ HDA_CODEC_STAC9205D, 0, "Sigmatel STAC9205D" },
{ HDA_CODEC_STAC9220, 0, "Sigmatel STAC9220" },
{ HDA_CODEC_STAC9220_A1, 0, "Sigmatel STAC9220_A1" },
{ HDA_CODEC_STAC9220_A2, 0, "Sigmatel STAC9220_A2" },
{ HDA_CODEC_STAC9221, 0, "Sigmatel STAC9221" },
{ HDA_CODEC_STAC9221_A2, 0, "Sigmatel STAC9221_A2" },
{ HDA_CODEC_STAC9221D, 0, "Sigmatel STAC9221D" },
{ HDA_CODEC_STAC922XD, 0, "Sigmatel STAC9220D/9223D" },
{ HDA_CODEC_STAC9227X, 0, "Sigmatel STAC9227X" },
{ HDA_CODEC_STAC9227D, 0, "Sigmatel STAC9227D" },
{ HDA_CODEC_STAC9228X, 0, "Sigmatel STAC9228X" },
{ HDA_CODEC_STAC9228D, 0, "Sigmatel STAC9228D" },
{ HDA_CODEC_STAC9229X, 0, "Sigmatel STAC9229X" },
{ HDA_CODEC_STAC9229D, 0, "Sigmatel STAC9229D" },
{ HDA_CODEC_STAC9230X, 0, "Sigmatel STAC9230X" },
{ HDA_CODEC_STAC9230D, 0, "Sigmatel STAC9230D" },
{ HDA_CODEC_STAC9250, 0, "Sigmatel STAC9250" },
{ HDA_CODEC_STAC9251, 0, "Sigmatel STAC9251" },
{ HDA_CODEC_STAC9271X, 0, "Sigmatel STAC9271X" },
{ HDA_CODEC_STAC9271D, 0, "Sigmatel STAC9271D" },
{ HDA_CODEC_STAC9272X, 0, "Sigmatel STAC9272X" },
{ HDA_CODEC_STAC9272D, 0, "Sigmatel STAC9272D" },
{ HDA_CODEC_STAC9273X, 0, "Sigmatel STAC9273X" },
{ HDA_CODEC_STAC9273D, 0, "Sigmatel STAC9273D" },
{ HDA_CODEC_STAC9274, 0, "Sigmatel STAC9274" },
{ HDA_CODEC_STAC9274D, 0, "Sigmatel STAC9274D" },
{ HDA_CODEC_STAC9274X5NH, 0, "Sigmatel STAC9274X5NH" },
{ HDA_CODEC_STAC9274D5NH, 0, "Sigmatel STAC9274D5NH" },
{ HDA_CODEC_STAC9872AK, 0, "Sigmatel STAC9872AK" },
{ HDA_CODEC_IDT92HD005, 0, "IDT 92HD005" },
{ HDA_CODEC_IDT92HD005D, 0, "IDT 92HD005D" },
{ HDA_CODEC_IDT92HD206X, 0, "IDT 92HD206X" },
{ HDA_CODEC_IDT92HD206D, 0, "IDT 92HD206D" },
{ HDA_CODEC_IDT92HD700X, 0, "IDT 92HD700X" },
{ HDA_CODEC_IDT92HD700D, 0, "IDT 92HD700D" },
{ HDA_CODEC_IDT92HD71B5, 0, "IDT 92HD71B5" },
{ HDA_CODEC_IDT92HD71B7, 0, "IDT 92HD71B7" },
{ HDA_CODEC_IDT92HD71B8, 0, "IDT 92HD71B8" },
{ HDA_CODEC_IDT92HD73C1, 0, "IDT 92HD73C1" },
{ HDA_CODEC_IDT92HD73D1, 0, "IDT 92HD73D1" },
{ HDA_CODEC_IDT92HD73E1, 0, "IDT 92HD73E1" },
{ HDA_CODEC_IDT92HD75B3, 0, "IDT 92HD75B3" },
{ HDA_CODEC_IDT92HD75BX, 0, "IDT 92HD75BX" },
{ HDA_CODEC_IDT92HD81B1C, 0, "IDT 92HD81B1C" },
{ HDA_CODEC_IDT92HD81B1X, 0, "IDT 92HD81B1X" },
{ HDA_CODEC_IDT92HD83C1C, 0, "IDT 92HD83C1C" },
{ HDA_CODEC_IDT92HD83C1X, 0, "IDT 92HD83C1X" },
{ HDA_CODEC_CX20549, 0, "Conexant CX20549 (Venice)" },
{ HDA_CODEC_CX20551, 0, "Conexant CX20551 (Waikiki)" },
{ HDA_CODEC_CX20561, 0, "Conexant CX20561 (Hermosa)" },
{ HDA_CODEC_CX20582, 0, "Conexant CX20582 (Pebble)" },
{ HDA_CODEC_CX20583, 0, "Conexant CX20583 (Pebble HSF)" },
{ HDA_CODEC_CX20584, 0, "Conexant CX20584" },
{ HDA_CODEC_CX20585, 0, "Conexant CX20585" },
{ HDA_CODEC_CX20588, 0, "Conexant CX20588" },
{ HDA_CODEC_CX20590, 0, "Conexant CX20590" },
{ HDA_CODEC_CX20631, 0, "Conexant CX20631" },
{ HDA_CODEC_CX20632, 0, "Conexant CX20632" },
{ HDA_CODEC_CX20641, 0, "Conexant CX20641" },
{ HDA_CODEC_CX20642, 0, "Conexant CX20642" },
{ HDA_CODEC_CX20651, 0, "Conexant CX20651" },
{ HDA_CODEC_CX20652, 0, "Conexant CX20652" },
{ HDA_CODEC_CX20664, 0, "Conexant CX20664" },
{ HDA_CODEC_CX20665, 0, "Conexant CX20665" },
{ HDA_CODEC_VT1708_8, 0, "VIA VT1708_8" },
{ HDA_CODEC_VT1708_9, 0, "VIA VT1708_9" },
{ HDA_CODEC_VT1708_A, 0, "VIA VT1708_A" },
{ HDA_CODEC_VT1708_B, 0, "VIA VT1708_B" },
{ HDA_CODEC_VT1709_0, 0, "VIA VT1709_0" },
{ HDA_CODEC_VT1709_1, 0, "VIA VT1709_1" },
{ HDA_CODEC_VT1709_2, 0, "VIA VT1709_2" },
{ HDA_CODEC_VT1709_3, 0, "VIA VT1709_3" },
{ HDA_CODEC_VT1709_4, 0, "VIA VT1709_4" },
{ HDA_CODEC_VT1709_5, 0, "VIA VT1709_5" },
{ HDA_CODEC_VT1709_6, 0, "VIA VT1709_6" },
{ HDA_CODEC_VT1709_7, 0, "VIA VT1709_7" },
{ HDA_CODEC_VT1708B_0, 0, "VIA VT1708B_0" },
{ HDA_CODEC_VT1708B_1, 0, "VIA VT1708B_1" },
{ HDA_CODEC_VT1708B_2, 0, "VIA VT1708B_2" },
{ HDA_CODEC_VT1708B_3, 0, "VIA VT1708B_3" },
{ HDA_CODEC_VT1708B_4, 0, "VIA VT1708B_4" },
{ HDA_CODEC_VT1708B_5, 0, "VIA VT1708B_5" },
{ HDA_CODEC_VT1708B_6, 0, "VIA VT1708B_6" },
{ HDA_CODEC_VT1708B_7, 0, "VIA VT1708B_7" },
{ HDA_CODEC_VT1708S_0, 0, "VIA VT1708S_0" },
{ HDA_CODEC_VT1708S_1, 0, "VIA VT1708S_1" },
{ HDA_CODEC_VT1708S_2, 0, "VIA VT1708S_2" },
{ HDA_CODEC_VT1708S_3, 0, "VIA VT1708S_3" },
{ HDA_CODEC_VT1708S_4, 0, "VIA VT1708S_4" },
{ HDA_CODEC_VT1708S_5, 0, "VIA VT1708S_5" },
{ HDA_CODEC_VT1708S_6, 0, "VIA VT1708S_6" },
{ HDA_CODEC_VT1708S_7, 0, "VIA VT1708S_7" },
{ HDA_CODEC_VT1702_0, 0, "VIA VT1702_0" },
{ HDA_CODEC_VT1702_1, 0, "VIA VT1702_1" },
{ HDA_CODEC_VT1702_2, 0, "VIA VT1702_2" },
{ HDA_CODEC_VT1702_3, 0, "VIA VT1702_3" },
{ HDA_CODEC_VT1702_4, 0, "VIA VT1702_4" },
{ HDA_CODEC_VT1702_5, 0, "VIA VT1702_5" },
{ HDA_CODEC_VT1702_6, 0, "VIA VT1702_6" },
{ HDA_CODEC_VT1702_7, 0, "VIA VT1702_7" },
{ HDA_CODEC_VT1716S_0, 0, "VIA VT1716S_0" },
{ HDA_CODEC_VT1716S_1, 0, "VIA VT1716S_1" },
{ HDA_CODEC_VT1718S_0, 0, "VIA VT1718S_0" },
{ HDA_CODEC_VT1718S_1, 0, "VIA VT1718S_1" },
{ HDA_CODEC_VT1802_0, 0, "VIA VT1802_0" },
{ HDA_CODEC_VT1802_1, 0, "VIA VT1802_1" },
{ HDA_CODEC_VT1812, 0, "VIA VT1812" },
{ HDA_CODEC_VT1818S, 0, "VIA VT1818S" },
{ HDA_CODEC_VT1828S, 0, "VIA VT1828S" },
{ HDA_CODEC_VT2002P_0, 0, "VIA VT2002P_0" },
{ HDA_CODEC_VT2002P_1, 0, "VIA VT2002P_1" },
{ HDA_CODEC_VT2020, 0, "VIA VT2020" },
{ HDA_CODEC_ATIRS600_1, 0, "ATI RS600" },
{ HDA_CODEC_ATIRS600_2, 0, "ATI RS600" },
{ HDA_CODEC_ATIRS690, 0, "ATI RS690/780" },
{ HDA_CODEC_ATIR6XX, 0, "ATI R6xx" },
{ HDA_CODEC_NVIDIAMCP67, 0, "NVIDIA MCP67" },
{ HDA_CODEC_NVIDIAMCP73, 0, "NVIDIA MCP73" },
{ HDA_CODEC_NVIDIAMCP78, 0, "NVIDIA MCP78" },
{ HDA_CODEC_NVIDIAMCP78_2, 0, "NVIDIA MCP78" },
{ HDA_CODEC_NVIDIAMCP7A, 0, "NVIDIA MCP7A" },
{ HDA_CODEC_NVIDIAGT220, 0, "NVIDIA GT220" },
{ HDA_CODEC_NVIDIAGT21X, 0, "NVIDIA GT21x" },
{ HDA_CODEC_NVIDIAMCP89, 0, "NVIDIA MCP89" },
{ HDA_CODEC_NVIDIAGT240, 0, "NVIDIA GT240" },
{ HDA_CODEC_INTELIP, 0, "Intel Ibex Peak" },
{ HDA_CODEC_INTELBL, 0, "Intel Bearlake" },
{ HDA_CODEC_INTELCA, 0, "Intel Cantiga" },
{ HDA_CODEC_INTELEL, 0, "Intel Eaglelake" },
{ HDA_CODEC_INTELIP2, 0, "Intel Ibex Peak" },
{ HDA_CODEC_INTELCPT, 0, "Intel Cougar Point" },
{ HDA_CODEC_INTELPPT, 0, "Intel Panther Point" },
{ HDA_CODEC_INTELCL, 0, "Intel Crestline" },
{ HDA_CODEC_SII1390, 0, "Silicon Image SiI1390" },
{ HDA_CODEC_SII1392, 0, "Silicon Image SiI1392" },
/* Unknown CODECs */
{ HDA_CODEC_ALCXXXX, 0, "Realtek (Unknown)" },
{ HDA_CODEC_ADXXXX, 0, "Analog Devices (Unknown)" },
{ HDA_CODEC_CSXXXX, 0, "Cirrus Logic (Unknown)" },
{ HDA_CODEC_CMIXXXX, 0, "CMedia (Unknown)" },
{ HDA_CODEC_STACXXXX, 0, "Sigmatel (Unknown)" },
{ HDA_CODEC_SIIXXXX, 0, "Silicon Image (Unknown)" },
{ HDA_CODEC_AGEREXXXX, 0, "Lucent/Agere Systems (Unknown)" },
{ HDA_CODEC_CXXXXX, 0, "Conexant (Unknown)" },
{ HDA_CODEC_VTXXXX, 0, "VIA (Unknown)" },
{ HDA_CODEC_ATIXXXX, 0, "ATI (Unknown)" },
{ HDA_CODEC_NVIDIAXXXX, 0, "NVIDIA (Unknown)" },
{ HDA_CODEC_INTELXXXX, 0, "Intel (Unknown)" },
{ HDA_CODEC_IDTXXXX, 0, "IDT (Unknown)" },
};
#define HDACC_CODECS_LEN (sizeof(hdacc_codecs) / sizeof(hdacc_codecs[0]))
/****************************************************************************
* Function prototypes
****************************************************************************/
static char *
hdacc_codec_name(uint32_t id, uint16_t revid)
{
int i;
for (i = 0; i < HDACC_CODECS_LEN; i++) {
if (!HDA_DEV_MATCH(hdacc_codecs[i].id, id))
continue;
if (hdacc_codecs[i].revid != 0 &&
hdacc_codecs[i].revid != revid)
continue;
return (hdacc_codecs[i].name);
}
return ((id == 0x00000000) ? "NULL CODEC" : "Unknown CODEC");
}
static int
hdacc_suspend(device_t dev)
{
HDA_BOOTHVERBOSE(
device_printf(dev, "Suspend...\n");
);
bus_generic_suspend(dev);
HDA_BOOTHVERBOSE(
device_printf(dev, "Suspend done\n");
);
return (0);
}
static int
hdacc_resume(device_t dev)
{
HDA_BOOTHVERBOSE(
device_printf(dev, "Resume...\n");
);
bus_generic_resume(dev);
HDA_BOOTHVERBOSE(
device_printf(dev, "Resume done\n");
);
return (0);
}
static int
hdacc_probe(device_t dev)
{
uint32_t id, revid;
char buf[128];
id = ((uint32_t)hda_get_vendor_id(dev) << 16) + hda_get_device_id(dev);
revid = ((uint32_t)hda_get_revision_id(dev) << 8) + hda_get_stepping_id(dev);
snprintf(buf, sizeof(buf), "%s HDA CODEC", hdacc_codec_name(id, revid));
device_set_desc_copy(dev, buf);
return (BUS_PROBE_DEFAULT);
}
static int
hdacc_attach(device_t dev)
{
struct hdacc_softc *codec = device_get_softc(dev);
device_t child;
int cad = (intptr_t)device_get_ivars(dev);
uint32_t subnode;
int startnode;
int endnode;
int i, n;
codec->lock = HDAC_GET_MTX(device_get_parent(dev), dev);
codec->dev = dev;
codec->cad = cad;
hdacc_lock(codec);
subnode = hda_command(dev,
HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_SUB_NODE_COUNT));
hdacc_unlock(codec);
if (subnode == HDA_INVALID)
return (EIO);
codec->fgcnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
endnode = startnode + codec->fgcnt;
HDA_BOOTVERBOSE(
device_printf(dev,
"Root Node at nid=0: %d subnodes %d-%d\n",
HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode),
startnode, endnode - 1);
);
codec->fgs = malloc(sizeof(struct hdacc_fg) * codec->fgcnt,
M_HDACC, M_ZERO | M_WAITOK);
for (i = startnode, n = 0; i < endnode; i++, n++) {
codec->fgs[n].nid = i;
hdacc_lock(codec);
codec->fgs[n].type =
HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hda_command(dev,
HDA_CMD_GET_PARAMETER(0, i, HDA_PARAM_FCT_GRP_TYPE)));
codec->fgs[n].subsystem_id = hda_command(dev,
HDA_CMD_GET_SUBSYSTEM_ID(0, i));
hdacc_unlock(codec);
codec->fgs[n].dev = child = device_add_child(dev, NULL, -1);
if (child == NULL) {
device_printf(dev, "Failed to add function device\n");
continue;
}
device_set_ivars(child, &codec->fgs[n]);
}
bus_generic_attach(dev);
return (0);
}
static int
hdacc_detach(device_t dev)
{
return (device_delete_children(dev));
}
static int
hdacc_child_location_str(device_t dev, device_t child, char *buf,
size_t buflen)
{
struct hdacc_fg *fg = device_get_ivars(child);
snprintf(buf, buflen, "nid=%d", fg->nid);
return (0);
}
static int
hdacc_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
size_t buflen)
{
struct hdacc_fg *fg = device_get_ivars(child);
snprintf(buf, buflen, "type=0x%02x subsystem=0x%08x",
fg->type, fg->subsystem_id);
return (0);
}
static int
hdacc_print_child(device_t dev, device_t child)
{
struct hdacc_fg *fg = device_get_ivars(child);
int retval;
retval = bus_print_child_header(dev, child);
retval += printf(" at nid %d", fg->nid);
retval += bus_print_child_footer(dev, child);
return (retval);
}
static void
hdacc_probe_nomatch(device_t dev, device_t child)
{
struct hdacc_softc *codec = device_get_softc(dev);
struct hdacc_fg *fg = device_get_ivars(child);
device_printf(child, "<%s %s Function Group> at nid %d on %s "
"(no driver attached)\n",
device_get_desc(dev),
fg->type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ? "Audio" :
(fg->type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM ? "Modem" :
"Unknown"), fg->nid, device_get_nameunit(dev));
HDA_BOOTHVERBOSE(
device_printf(dev, "Power down FG nid=%d to the D3 state...\n",
fg->nid);
);
hdacc_lock(codec);
hda_command(dev, HDA_CMD_SET_POWER_STATE(0,
fg->nid, HDA_CMD_POWER_STATE_D3));
hdacc_unlock(codec);
}
static int
hdacc_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
struct hdacc_fg *fg = device_get_ivars(child);
switch (which) {
case HDA_IVAR_NODE_ID:
*result = fg->nid;
break;
case HDA_IVAR_NODE_TYPE:
*result = fg->type;
break;
case HDA_IVAR_SUBSYSTEM_ID:
*result = fg->subsystem_id;
break;
default:
return(BUS_READ_IVAR(device_get_parent(dev), dev,
which, result));
}
return (0);
}
static struct mtx *
hdacc_get_mtx(device_t dev, device_t child)
{
struct hdacc_softc *codec = device_get_softc(dev);
return (codec->lock);
}
static uint32_t
hdacc_codec_command(device_t dev, device_t child, uint32_t verb)
{
return (HDAC_CODEC_COMMAND(device_get_parent(dev), dev, verb));
}
static int
hdacc_stream_alloc(device_t dev, device_t child, int dir, int format,
uint32_t **dmapos)
{
struct hdacc_softc *codec = device_get_softc(dev);
int stream;
stream = HDAC_STREAM_ALLOC(device_get_parent(dev), dev,
dir, format, dmapos);
if (stream > 0)
codec->streams[dir][stream] = child;
return (stream);
}
static void
hdacc_stream_free(device_t dev, device_t child, int dir, int stream)
{
struct hdacc_softc *codec = device_get_softc(dev);
codec->streams[dir][stream] = NULL;
HDAC_STREAM_FREE(device_get_parent(dev), dev, dir, stream);
}
static int
hdacc_stream_start(device_t dev, device_t child,
int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
{
return (HDAC_STREAM_START(device_get_parent(dev), dev,
dir, stream, buf, blksz, blkcnt));
}
static void
hdacc_stream_stop(device_t dev, device_t child, int dir, int stream)
{
HDAC_STREAM_STOP(device_get_parent(dev), dev, dir, stream);
}
static void
hdacc_stream_reset(device_t dev, device_t child, int dir, int stream)
{
HDAC_STREAM_RESET(device_get_parent(dev), dev, dir, stream);
}
static uint32_t
hdacc_stream_getptr(device_t dev, device_t child, int dir, int stream)
{
return (HDAC_STREAM_GETPTR(device_get_parent(dev), dev, dir, stream));
}
static void
hdacc_stream_intr(device_t dev, int dir, int stream)
{
struct hdacc_softc *codec = device_get_softc(dev);
device_t child;
if ((child = codec->streams[dir][stream]) != NULL);
HDAC_STREAM_INTR(child, dir, stream);
}
static int
hdacc_unsol_alloc(device_t dev, device_t child, int wanted)
{
struct hdacc_softc *codec = device_get_softc(dev);
int tag;
wanted &= 0x3f;
tag = wanted;
do {
if (codec->tags[tag] == NULL) {
codec->tags[tag] = child;
HDAC_UNSOL_ALLOC(device_get_parent(dev), dev, tag);
return (tag);
}
tag++;
tag &= 0x3f;
} while (tag != wanted);
return (-1);
}
static void
hdacc_unsol_free(device_t dev, device_t child, int tag)
{
struct hdacc_softc *codec = device_get_softc(dev);
KASSERT(tag >= 0 && tag <= 0x3f, ("Wrong tag value %d\n", tag));
codec->tags[tag] = NULL;
HDAC_UNSOL_FREE(device_get_parent(dev), dev, tag);
}
static void
hdacc_unsol_intr(device_t dev, uint32_t resp)
{
struct hdacc_softc *codec = device_get_softc(dev);
device_t child;
int tag;
tag = resp >> 26;
if ((child = codec->tags[tag]) != NULL)
HDAC_UNSOL_INTR(child, resp);
else
device_printf(codec->dev, "Unexpected unsolicited "
"response with tag %d: %08x\n", tag, resp);
}
static void
hdacc_pindump(device_t dev)
{
device_t *devlist;
int devcount, i;
if (device_get_children(dev, &devlist, &devcount) != 0)
return;
for (i = 0; i < devcount; i++)
HDAC_PINDUMP(devlist[i]);
free(devlist, M_TEMP);
}
static device_method_t hdacc_methods[] = {
/* device interface */
DEVMETHOD(device_probe, hdacc_probe),
DEVMETHOD(device_attach, hdacc_attach),
DEVMETHOD(device_detach, hdacc_detach),
DEVMETHOD(device_suspend, hdacc_suspend),
DEVMETHOD(device_resume, hdacc_resume),
/* Bus interface */
DEVMETHOD(bus_child_location_str, hdacc_child_location_str),
DEVMETHOD(bus_child_pnpinfo_str, hdacc_child_pnpinfo_str_method),
DEVMETHOD(bus_print_child, hdacc_print_child),
DEVMETHOD(bus_probe_nomatch, hdacc_probe_nomatch),
DEVMETHOD(bus_read_ivar, hdacc_read_ivar),
DEVMETHOD(hdac_get_mtx, hdacc_get_mtx),
DEVMETHOD(hdac_codec_command, hdacc_codec_command),
DEVMETHOD(hdac_stream_alloc, hdacc_stream_alloc),
DEVMETHOD(hdac_stream_free, hdacc_stream_free),
DEVMETHOD(hdac_stream_start, hdacc_stream_start),
DEVMETHOD(hdac_stream_stop, hdacc_stream_stop),
DEVMETHOD(hdac_stream_reset, hdacc_stream_reset),
DEVMETHOD(hdac_stream_getptr, hdacc_stream_getptr),
DEVMETHOD(hdac_stream_intr, hdacc_stream_intr),
DEVMETHOD(hdac_unsol_alloc, hdacc_unsol_alloc),
DEVMETHOD(hdac_unsol_free, hdacc_unsol_free),
DEVMETHOD(hdac_unsol_intr, hdacc_unsol_intr),
DEVMETHOD(hdac_pindump, hdacc_pindump),
{ 0, 0 }
};
static driver_t hdacc_driver = {
"hdacc",
hdacc_methods,
sizeof(struct hdacc_softc),
};
static devclass_t hdacc_devclass;
DRIVER_MODULE(snd_hda, hdac, hdacc_driver, hdacc_devclass, 0, 0);

5
sys/modules/sound/driver/hda/Makefile
View File

@ -3,7 +3,8 @@
.PATH: ${.CURDIR}/../../../../dev/sound/pci/hda
KMOD= snd_hda
SRCS= device_if.h bus_if.h pci_if.h channel_if.h mixer_if.h
SRCS+= hdac.c hdac_private.h hdac_reg.h hda_reg.h hdac.h
SRCS= device_if.h bus_if.h pci_if.h channel_if.h mixer_if.h hdac_if.h
SRCS+= hdaa.c hdaa.h hdaa_patches.c hdac.c hdac_if.h hdac_if.c
SRCS+= hdacc.c hdac_private.h hdac_reg.h hda_reg.h hdac.h
.include <bsd.kmod.mk>