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The private peripheral interrupts start at offset 16, not 0. Also, use

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names rather than inline mystery constants for these offsets.

Pointed out by:	andrew
This commit is contained in:
Ian Lepore 2014-09-15 15:36:00 +00:00
parent 9c7116e195
commit 7cb146ae26
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=271630
1 changed files with 7 additions and 3 deletions
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10
sys/arm/arm/gic.c
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@ -83,7 +83,11 @@ __FBSDID("$FreeBSD$");
#define GICC_ABPR 0x001C /* v1 ICCABPR */
#define GICC_IIDR 0x00FC /* v1 ICCIIDR*/
#define GIC_LAST_IPI 15 /* Irqs 0-15 are IPIs. */
#define GIC_FIRST_IPI 0 /* Irqs 0-15 are SGIs/IPIs. */
#define GIC_LAST_IPI 15
#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */
#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */
#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */
/* First bit is a polarity bit (0 - low, 1 - high) */
#define GICD_ICFGR_POL_LOW (0 << 0)
@ -205,9 +209,9 @@ gic_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt,
*pol = INTR_POLARITY_CONFORM;
} else {
if (intr[0] == 0)
*interrupt = fdt32_to_cpu(intr[1]) + 32;
*interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_SPI;
else
*interrupt = fdt32_to_cpu(intr[1]);
*interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_PPI;
/*
* In intr[2], bits[3:0] are trigger type and level flags.
* 1 = low-to-high edge triggered