ARM: SEV/WFE instructions are implemented starting from ARMv6K,
use it directly. MFC after: 1 week
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parent
55e447c98c
commit
7cc70732a3
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=306756
@ -193,7 +193,8 @@ aw_mp_start_ap(platform_t plat)
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val |= (1 << i);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val);
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armv7_sev();
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, cpucfg, CPUCFG_SIZE);
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if (soc_family != ALLWINNERSOC_SUN7I)
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bus_space_unmap(fdtbus_bs_tag, prcm, PRCM_SIZE);
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@ -279,7 +280,8 @@ a83t_mp_start_ap(platform_t plat)
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panic("Couldn't map the PRCM\n");
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aw_mc_mp_start_ap(cpuscfg, cpuxcfg, prcm);
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armv7_sev();
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, cpuxcfg, CPUXCFG_SIZE);
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bus_space_unmap(fdtbus_bs_tag, cpuscfg, CPUCFG_SIZE);
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bus_space_unmap(fdtbus_bs_tag, prcm, PRCM_SIZE);
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@ -151,7 +151,8 @@ platform_mp_start_ap(void)
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/* Put CPU1 out from reset */
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bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);
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armv7_sev();
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
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bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
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@ -487,7 +487,8 @@ platform_mp_start_ap(void)
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CPUCONF_BARRIER(AML_CPUCONF_CONTROL_REG);
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/* Wakeup the now enabled APs */
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armv7_sev();
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dsb();
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sev();
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/*
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* Free the resources which are not needed after startup.
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@ -165,10 +165,3 @@ ENTRY(armv7_drain_writebuf)
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dsb
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RET
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END(armv7_drain_writebuf)
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ENTRY(armv7_sev)
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dsb
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sev
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nop
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RET
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END(armv7_sev)
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@ -467,9 +467,8 @@ release_aps(void *dummy __unused)
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#endif
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atomic_store_rel_int(&aps_ready, 1);
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/* Wake the other threads up */
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#if __ARM_ARCH >= 7
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armv7_sev();
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#endif
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dsb();
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sev();
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printf("Release APs\n");
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@ -135,7 +135,8 @@ bcm2836_mp_start_ap(platform_t plat)
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} while (1);
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/* dsb and sev */
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armv7_sev();
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dsb();
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sev();
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/* recode AP in CPU map */
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CPU_SET(i, &all_cpus);
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@ -150,7 +150,8 @@ platform_mp_start_ap(void)
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}
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bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val);
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armv7_sev();
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
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bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
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@ -56,6 +56,8 @@ extern uint32_t ccnt_hi[MAXCPU];
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extern int pmu_attched;
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#endif /* DEV_PMU */
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#define sev() __asm __volatile("sev" : : : "memory")
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#define wfe() __asm __volatile("wfe" : : : "memory")
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/*
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* Macros to generate CP15 (system control processor) read/write functions.
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@ -284,7 +284,6 @@ void armv7_idcache_wbinv_all (void);
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void armv7_cpu_sleep (int);
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void armv7_setup (void);
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void armv7_drain_writebuf (void);
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void armv7_sev (void);
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void armadaxp_idcache_wbinv_all (void);
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@ -146,7 +146,8 @@ pmsu_boot_secondary_cpu(void)
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pmap_kextract((vm_offset_t)mpentry));
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dcache_wbinv_poc_all();
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armv7_sev();
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, vaddr, MV_PMSU_REGS_LEN);
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@ -121,7 +121,8 @@ tegra124_mp_start_ap(platform_t plat)
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}
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}
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armv7_sev();
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, pmc, PMC_SIZE);
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bus_space_unmap(fdtbus_bs_tag, exvec, TEGRA_EXCEPTION_VECTORS_SIZE);
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}
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@ -163,7 +163,8 @@ platform_mp_start_ap(void)
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val &= ~(1 << i);
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bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
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armv7_sev();
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
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bus_space_unmap(fdtbus_bs_tag, imem, IMEM_SIZE);
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@ -124,7 +124,8 @@ platform_mp_start_ap(void)
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dcache_wbinv_poc_all();
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armv7_sev();
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, sysram, 0x100);
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bus_space_unmap(fdtbus_bs_tag, pmu, 0x20000);
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}
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@ -64,6 +64,7 @@ platform_mp_start_ap(void)
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ti_smc0(0x200, 0xfffffdff, MODIFY_AUX_CORE_0);
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ti_smc0(pmap_kextract((vm_offset_t)mpentry), 0, WRITE_AUX_CORE_1);
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armv7_sev();
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, scu_addr, 0x1000);
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}
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@ -94,5 +94,6 @@ platform_mp_start_ap(void)
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dcache_wbinv_poc_all();
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/* Wake up CPU1. */
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armv7_sev();
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dsb();
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sev();
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}
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