pci: Add an ioctl to perform I/O to BARs
This is useful for bhyve, which otherwise has to use /dev/io to handle accesses to I/O port BARs when PCI passthrough is in use. Reviewed by: imp, kib Discussed with: jhb MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D31307
This commit is contained in:
Mark Johnston
parent
a3d932dfef
commit
7e14be0b07
@ -24,7 +24,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd July 27, 2021
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.Dd August 13, 2021
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.Dt PCI 4
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.Os
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.Sh NAME
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@ -430,6 +430,40 @@ even on reads.
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of mapping.
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Currently attempt to mmap an inactive BAR results in error.
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.El
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.It PCIOCBARIO
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This
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.Xr ioctl 2
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command allows users to read from and write to BARs.
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The I/O request parameters are passed in a
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.Va struct pci_bar_ioreq
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structure, which has the following fields:
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.Bl -tag
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.It Vt struct pcisel pbi_sel
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Describes the device to operate on.
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.It Vt int pbi_op
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The operation to perform.
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Currently supported values are
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.Dv PCIBARIO_READ
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and
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.Dv PCIBARIO_WRITE .
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.It Vt uint32_t pbi_bar
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The index of the BAR on which to operate.
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.It Vt uint32_t pbi_offset
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The offset into the BAR at which to operate.
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.It Vt uint32_t pbi_width
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The size, in bytes, of the I/O operation.
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1-byte, 2-byte, 4-byte and 8-byte perations are supported.
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.It Vt uint32_t pbi_value
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For reads, the value is returned in this field.
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For writes, the caller specifies the value to be written in this field.
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.Pp
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Note that this operation maps and unmaps the corresponding resource and
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so is relatively expensive for memory BARs.
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The
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.Va PCIOCBARMMAP
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.Xr ioctl 2
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can be used to create a persistent userspace mapping for such BARs instead.
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.El
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.El
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.Sh LOADER TUNABLES
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Tunables can be set at the
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@ -923,6 +923,92 @@ pci_bar_mmap(device_t pcidev, struct pci_bar_mmap *pbm)
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return (error);
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}
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static int
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pci_bar_io(device_t pcidev, struct pci_bar_ioreq *pbi)
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{
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struct pci_map *pm;
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struct resource *res;
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uint32_t offset, width;
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int bar, error, type;
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if (pbi->pbi_op != PCIBARIO_READ &&
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pbi->pbi_op != PCIBARIO_WRITE)
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return (EINVAL);
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bar = PCIR_BAR(pbi->pbi_bar);
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pm = pci_find_bar(pcidev, bar);
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if (pm == NULL)
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return (EINVAL);
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offset = pbi->pbi_offset;
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width = pbi->pbi_width;
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if (offset + width < offset ||
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((pci_addr_t)1 << pm->pm_size) < offset + width)
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return (EINVAL);
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type = PCI_BAR_MEM(pm->pm_value) ? SYS_RES_MEMORY : SYS_RES_IOPORT;
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/*
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* This will fail if a driver has allocated the resource. This could be
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* worked around by detecting that case and using bus_map_resource() to
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* populate the handle, but so far this is not needed.
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*/
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res = bus_alloc_resource_any(pcidev, type, &bar, RF_ACTIVE);
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if (res == NULL)
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return (ENOENT);
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error = 0;
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switch (pbi->pbi_op) {
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case PCIBARIO_READ:
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switch (pbi->pbi_width) {
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case 1:
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pbi->pbi_value = bus_read_1(res, offset);
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break;
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case 2:
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pbi->pbi_value = bus_read_2(res, offset);
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break;
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case 4:
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pbi->pbi_value = bus_read_4(res, offset);
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break;
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#ifndef __i386__
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case 8:
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pbi->pbi_value = bus_read_8(res, offset);
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break;
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#endif
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default:
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error = EINVAL;
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break;
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}
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break;
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case PCIBARIO_WRITE:
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switch (pbi->pbi_width) {
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case 1:
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bus_write_1(res, offset, pbi->pbi_value);
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break;
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case 2:
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bus_write_2(res, offset, pbi->pbi_value);
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break;
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case 4:
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bus_write_4(res, offset, pbi->pbi_value);
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break;
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#ifndef __i386__
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case 8:
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bus_write_8(res, offset, pbi->pbi_value);
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break;
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#endif
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default:
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error = EINVAL;
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break;
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}
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break;
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}
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bus_release_resource(pcidev, type, bar, res);
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return (error);
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}
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static int
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pci_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag, struct thread *td)
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{
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@ -932,6 +1018,7 @@ pci_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag, struct thread *t
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struct pci_conf_io *cio = NULL;
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struct pci_devinfo *dinfo;
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struct pci_io *io;
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struct pci_bar_ioreq *pbi;
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struct pci_bar_io *bio;
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struct pci_list_vpd_io *lvio;
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struct pci_match_conf *pattern_buf;
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@ -1307,6 +1394,19 @@ pci_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag, struct thread *t
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error = pcidev == NULL ? ENODEV : pci_bar_mmap(pcidev, pbm);
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break;
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case PCIOCBARIO:
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pbi = (struct pci_bar_ioreq *)data;
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pcidev = pci_find_dbsf(pbi->pbi_sel.pc_domain,
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pbi->pbi_sel.pc_bus, pbi->pbi_sel.pc_dev,
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pbi->pbi_sel.pc_func);
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if (pcidev == NULL) {
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error = ENODEV;
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break;
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}
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error = pci_bar_io(pcidev, pbi);
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break;
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default:
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error = ENOTTY;
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break;
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@ -151,6 +151,17 @@ struct pci_bar_mmap {
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int pbm_memattr;
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};
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struct pci_bar_ioreq {
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struct pcisel pbi_sel; /* device to operate on */
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#define PCIBARIO_READ 0x1
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#define PCIBARIO_WRITE 0x2
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int pbi_op;
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uint32_t pbi_bar;
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uint32_t pbi_offset;
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uint32_t pbi_width;
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uint32_t pbi_value;
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};
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#define PCIIO_BAR_MMAP_FIXED 0x01
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#define PCIIO_BAR_MMAP_EXCL 0x02
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#define PCIIO_BAR_MMAP_RW 0x04
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@ -163,5 +174,6 @@ struct pci_bar_mmap {
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#define PCIOCGETBAR _IOWR('p', 6, struct pci_bar_io)
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#define PCIOCLISTVPD _IOWR('p', 7, struct pci_list_vpd_io)
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#define PCIOCBARMMAP _IOWR('p', 8, struct pci_bar_mmap)
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#define PCIOCBARIO _IOWR('p', 9, struct pci_bar_ioreq)
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#endif /* !_SYS_PCIIO_H_ */
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