Replace use of "0" constraints in inline asm with "+" constraints,
when an operand is used both for input and output. Reviewed by: jhb
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@ -66,13 +66,13 @@
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* which registers contain sum & w.
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*/
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#define ADD(n) __asm __volatile \
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("addl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
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("addl " #n "(%1), %0" : "+r" (sum) : "r" (w))
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#define ADDC(n) __asm __volatile \
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("adcl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
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("adcl " #n "(%1), %0" : "+r" (sum) : "r" (w))
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#define LOAD(n) __asm __volatile \
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("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
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("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
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#define MOP __asm __volatile \
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("adcl $0, %0" : "=r" (sum) : "0" (sum))
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("adcl $0, %0" : "+r" (sum))
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u_short
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in_cksum_skip(m, len, skip)
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