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o Add gain-level control registers.

Browse Source 
o Fix style.

Sponsored by:	Machdep, Inc.
This commit is contained in:
Ruslan Bukin 2016-01-23 13:34:55 +00:00
parent 79e910e9cb
commit 7eae0d9fbd
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=294632
1 changed files with 79 additions and 53 deletions
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132
sys/dev/sound/pci/hdspe.h
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@ -1,5 +1,5 @@
/*-
* Copyright (c) 2012 Ruslan Bukin <br@bsdpad.com>
* Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -26,71 +26,97 @@
* $FreeBSD$
*/
#define PCI_VENDOR_XILINX 0x10ee
#define PCI_DEVICE_XILINX_HDSPE 0x3fc6 /* AIO, MADI, AES, RayDAT */
#define PCI_CLASS_REVISION 0x08
#define PCI_REVISION_AIO 212
#define PCI_REVISION_RAYDAT 211
#define PCI_VENDOR_XILINX 0x10ee
#define PCI_DEVICE_XILINX_HDSPE 0x3fc6 /* AIO, MADI, AES, RayDAT */
#define PCI_CLASS_REVISION 0x08
#define PCI_REVISION_AIO 212
#define PCI_REVISION_RAYDAT 211
#define AIO 0
#define RAYDAT 1
#define AIO 0
#define RAYDAT 1
/* Hardware mixer */
#define HDSPE_OUT_ENABLE_BASE 512
#define HDSPE_IN_ENABLE_BASE 768
#define HDSPE_MIXER_BASE 32768
#define HDSPE_MAX_GAIN 32768
#define HDSPE_OUT_ENABLE_BASE 512
#define HDSPE_IN_ENABLE_BASE 768
#define HDSPE_MIXER_BASE 32768
#define HDSPE_MAX_GAIN 32768
/* Buffer */
#define HDSPE_PAGE_ADDR_BUF_OUT 8192
#define HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4)
#define HDSPE_BUF_POSITION_MASK 0x000FFC0
#define HDSPE_PAGE_ADDR_BUF_OUT 8192
#define HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4)
#define HDSPE_BUF_POSITION_MASK 0x000FFC0
/* Frequency */
#define HDSPE_FREQ_0 (1<<6)
#define HDSPE_FREQ_1 (1<<7)
#define HDSPE_FREQ_DOUBLE (1<<8)
#define HDSPE_FREQ_QUAD (1<<31)
#define HDSPE_FREQ_0 (1 << 6)
#define HDSPE_FREQ_1 (1 << 7)
#define HDSPE_FREQ_DOUBLE (1 << 8)
#define HDSPE_FREQ_QUAD (1 << 31)
#define HDSPE_FREQ_32000 HDSPE_FREQ_0
#define HDSPE_FREQ_44100 HDSPE_FREQ_1
#define HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1)
#define HDSPE_FREQ_MASK (HDSPE_FREQ_0 | HDSPE_FREQ_1 | \
#define HDSPE_FREQ_32000 HDSPE_FREQ_0
#define HDSPE_FREQ_44100 HDSPE_FREQ_1
#define HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1)
#define HDSPE_FREQ_MASK (HDSPE_FREQ_0 | HDSPE_FREQ_1 | \
HDSPE_FREQ_DOUBLE | HDSPE_FREQ_QUAD)
#define HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000
#define HDSPE_FREQ_REG 256
#define HDSPE_FREQ_AIO 104857600000000ULL
#define HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000
#define HDSPE_FREQ_REG 256
#define HDSPE_FREQ_AIO 104857600000000ULL
#define HDSPE_SPEED_DEFAULT 48000
#define HDSPE_SPEED_DEFAULT 48000
/* Latency */
#define HDSPE_LAT_0 (1<<1)
#define HDSPE_LAT_1 (1<<2)
#define HDSPE_LAT_2 (1<<3)
#define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2)
#define HDSPE_LAT_BYTES_MAX (4096 * 4)
#define HDSPE_LAT_BYTES_MIN (32 * 4)
#define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK)
#define HDSPE_LAT_0 (1 << 1)
#define HDSPE_LAT_1 (1 << 2)
#define HDSPE_LAT_2 (1 << 3)
#define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2)
#define HDSPE_LAT_BYTES_MAX (4096 * 4)
#define HDSPE_LAT_BYTES_MIN (32 * 4)
#define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK)
/* Gain */
#define HDSP_ADGain0 (1 << 25)
#define HDSP_ADGain1 (1 << 26)
#define HDSP_DAGain0 (1 << 27)
#define HDSP_DAGain1 (1 << 28)
#define HDSP_PhoneGain0 (1 << 29)
#define HDSP_PhoneGain1 (1 << 30)
#define HDSP_ADGainMask (HDSP_ADGain0 | HDSP_ADGain1)
#define HDSP_ADGainMinus10dBV (HDSP_ADGainMask)
#define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
#define HDSP_ADGainLowGain 0
#define HDSP_DAGainMask (HDSP_DAGain0 | HDSP_DAGain1)
#define HDSP_DAGainHighGain (HDSP_DAGainMask)
#define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
#define HDSP_DAGainMinus10dBV 0
#define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
#define HDSP_PhoneGain0dB HDSP_PhoneGainMask
#define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
#define HDSP_PhoneGainMinus12dB 0
#define HDSPM_statusRegister 0
#define HDSPM_statusRegister2 192
/* Settings */
#define HDSPE_SETTINGS_REG 0
#define HDSPE_CONTROL_REG 64
#define HDSPE_STATUS_REG 0
#define HDSPE_ENABLE (1<<0)
#define HDSPM_CLOCK_MODE_MASTER (1<<4)
#define HDSPE_SETTINGS_REG 0
#define HDSPE_CONTROL_REG 64
#define HDSPE_STATUS_REG 0
#define HDSPE_ENABLE (1 << 0)
#define HDSPM_CLOCK_MODE_MASTER (1 << 4)
/* Interrupts */
#define HDSPE_AUDIO_IRQ_PENDING (1<<0)
#define HDSPE_AUDIO_INT_ENABLE (1<<5)
#define HDSPE_INTERRUPT_ACK 96
#define HDSPE_AUDIO_IRQ_PENDING (1 << 0)
#define HDSPE_AUDIO_INT_ENABLE (1 << 5)
#define HDSPE_INTERRUPT_ACK 96
/* Channels */
#define HDSPE_MAX_SLOTS 64 /* Mono channels */
#define HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2) /* Stereo pairs */
#define HDSPE_MAX_SLOTS 64 /* Mono channels */
#define HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2) /* Stereo pairs */
#define HDSPE_CHANBUF_SAMPLES (16 * 1024)
#define HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES)
#define HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS)
#define HDSPE_CHANBUF_SAMPLES (16 * 1024)
#define HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES)
#define HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS)
struct hdspe_channel {
uint32_t left;
@ -164,16 +190,16 @@ struct sc_info {
uint32_t speed;
};
#define hdspe_read_1(sc, regno) \
#define hdspe_read_1(sc, regno) \
bus_space_read_1((sc)->cst, (sc)->csh, (regno))
#define hdspe_read_2(sc, regno) \
#define hdspe_read_2(sc, regno) \
bus_space_read_2((sc)->cst, (sc)->csh, (regno))
#define hdspe_read_4(sc, regno) \
#define hdspe_read_4(sc, regno) \
bus_space_read_4((sc)->cst, (sc)->csh, (regno))
#define hdspe_write_1(sc, regno, data) \
#define hdspe_write_1(sc, regno, data) \
bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data))
#define hdspe_write_2(sc, regno, data) \
#define hdspe_write_2(sc, regno, data) \
bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data))
#define hdspe_write_4(sc, regno, data) \
#define hdspe_write_4(sc, regno, data) \
bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data))