Major overhaul of common trap code

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- remove unused 601 and tlb exception code
 - remove interrupt-time PTE spill code. The pmap code
   will now take care of pinning kernel PTEs, and there
   are no longer issues about physical mapping of PTE
   data structures
 - All segment registers are switched on kernel entry/exit,
   allowing the kernel to have more virtual space and for
   user virtual space to extend to 4G.
 - The temporary register save area has been shifted from
   unused exception vector space to the per-cpu data area.
   This allows interrupts to be delivered to multiple CPUs
 - ISI traps no longer spill to BAT tables. It is assumed
   that all of kernel instruction memory is pinned.
 - shift from 'ldmw/stmw' instructions to individual register
   loads/stores when saving context. All PPC manuals indicate
   this should be much faster.
 - use '%r' for register names throughout.

TODO: need to test if DSI traps were the result of kernel stack
guard-page hits.

Reworked from:  NetBSD

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This commit is contained in:

grehan 2004-02-04 13:10:25 +00:00

parent 6bb94b3066

commit 7f45d5ab80

2 changed files with 760 additions and 1666 deletions

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sys/powerpc/aim/trap_subr.S

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sys/powerpc/powerpc/trap_subr.S

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