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e1000: introduce DPGFR register

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Defined DPGFR, Dynamic Power Gate Force Control Register.

Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>

Approved by:	imp
Obtained from:	DPDK (1469e5aceffbdcebe834292aadb40b1bd1602867)
MFC after:	1 week
This commit is contained in:
Guinan Sun 2020-07-06 08:12:19 +00:00 committed by Kevin Bowling
parent de965d042f
commit 7fb2111413
1 changed files with 1 additions and 0 deletions
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sys/dev/e1000/e1000_regs.h
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@ -71,6 +71,7 @@
#define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */
#define E1000_FEXTNVM12 0x5BC0 /* Future Extended NVM 12 - RW */
#define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */
#define E1000_DPGFR 0x00FAC /* Dynamic Power Gate Force Control Register */
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */