Teach pciconf how to dump out SR-IOV capability
Differential Revision: https://reviews.freebsd.org/D1639 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
This commit is contained in:
Ryan Stone
parent
bdc48af264
commit
7fdbba5e46
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=279466
@ -37,6 +37,7 @@ static const char rcsid[] =
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#include <err.h>
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#include <stdio.h>
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#include <strings.h>
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#include <sys/agpio.h>
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#include <sys/pciio.h>
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@ -636,7 +637,7 @@ ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
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printf(" %d fatal", bitcount32(sta & mask));
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printf(" %d non-fatal", bitcount32(sta & ~mask));
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sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4);
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printf(" %d corrected", bitcount32(sta));
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printf(" %d corrected\n", bitcount32(sta));
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}
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static void
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@ -652,6 +653,7 @@ ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
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if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0)
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printf(" lowpri VC0-VC%d",
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(cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4);
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printf("\n");
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}
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static void
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@ -664,7 +666,7 @@ ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
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return;
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low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4);
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high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4);
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printf(" %08x%08x", high, low);
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printf(" %08x%08x\n", high, low);
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}
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static void
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@ -676,7 +678,7 @@ ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
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if (ver < 1)
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return;
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val = read_config(fd, &p->pc_sel, ptr + 4, 4);
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printf(" ID %d", val & 0xffff);
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printf(" ID %d\n", val & 0xffff);
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}
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static void
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@ -688,7 +690,69 @@ ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
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if (ver < 1)
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return;
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val = read_config(fd, &p->pc_sel, ptr + 8, 4);
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printf(" lane errors %#x", val);
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printf(" lane errors %#x\n", val);
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}
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static const char *
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check_enabled(int value)
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{
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return (value ? "enabled" : "disabled");
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}
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static void
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ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
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{
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const char *comma, *enabled;
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uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did;
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uint32_t page_caps, page_size, page_shift, size;
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int i;
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printf("SR-IOV %d ", ver);
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iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2);
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printf("IOV %s, Memory Space %s, ARI %s\n",
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check_enabled(iov_ctl & PCIM_SRIOV_VF_EN),
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check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE),
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check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN));
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total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2);
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num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2);
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printf(" ");
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printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs);
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vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2);
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vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2);
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printf(" ");
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printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset,
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vf_stride);
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vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2);
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printf(" VF Device ID 0x%04x\n", vf_did);
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page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4);
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page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4);
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printf(" ");
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printf("Page Sizes: ");
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comma = "";
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while (page_caps != 0) {
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page_shift = ffs(page_caps) - 1;
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if (page_caps & page_size)
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enabled = " (enabled)";
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else
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enabled = "";
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size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT));
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printf("%s%d%s", comma, size, enabled);
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comma = ", ";
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page_caps &= ~(1 << page_shift);
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}
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printf("\n");
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for (i = 0; i <= PCIR_MAX_BAR_0; i++)
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print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i));
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}
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struct {
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@ -704,7 +768,6 @@ struct {
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{ PCIZ_ACS, "ACS" },
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{ PCIZ_ARI, "ARI" },
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{ PCIZ_ATS, "ATS" },
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{ PCIZ_SRIOV, "SRIOV" },
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{ PCIZ_MULTICAST, "Multicast" },
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{ PCIZ_RESIZE_BAR, "Resizable BAR" },
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{ PCIZ_DPA, "DPA" },
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@ -743,6 +806,9 @@ list_ecaps(int fd, struct pci_conf *p)
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case PCIZ_SEC_PCIE:
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ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap));
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break;
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case PCIZ_SRIOV:
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ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap));
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break;
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default:
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name = "unknown";
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for (i = 0; ecap_names[i].name != NULL; i++)
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@ -750,10 +816,9 @@ list_ecaps(int fd, struct pci_conf *p)
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name = ecap_names[i].name;
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break;
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}
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printf("%s %d", name, PCI_EXTCAP_VER(ecap));
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printf("%s %d\n", name, PCI_EXTCAP_VER(ecap));
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break;
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}
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printf("\n");
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ptr = PCI_EXTCAP_NEXTPTR(ecap);
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if (ptr == 0)
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break;
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@ -263,10 +263,7 @@ list_devs(const char *name, int verbose, int bars, int caps, int errors,
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static void
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list_bars(int fd, struct pci_conf *p)
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{
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struct pci_bar_io bar;
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uint64_t base;
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const char *type;
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int i, range, max;
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int i, max;
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switch (p->pc_hdr & PCIM_HDRTYPE) {
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case PCIM_HDRTYPE_NORMAL:
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@ -282,40 +279,50 @@ list_bars(int fd, struct pci_conf *p)
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return;
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}
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for (i = 0; i <= max; i++) {
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bar.pbi_sel = p->pc_sel;
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bar.pbi_reg = PCIR_BAR(i);
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if (ioctl(fd, PCIOCGETBAR, &bar) < 0)
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continue;
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if (PCI_BAR_IO(bar.pbi_base)) {
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type = "I/O Port";
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for (i = 0; i <= max; i++)
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print_bar(fd, p, "bar ", PCIR_BAR(i));
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}
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void
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print_bar(int fd, struct pci_conf *p, const char *label, uint16_t bar_offset)
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{
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uint64_t base;
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const char *type;
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struct pci_bar_io bar;
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int range;
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bar.pbi_sel = p->pc_sel;
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bar.pbi_reg = bar_offset;
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if (ioctl(fd, PCIOCGETBAR, &bar) < 0)
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return;
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if (PCI_BAR_IO(bar.pbi_base)) {
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type = "I/O Port";
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range = 32;
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base = bar.pbi_base & PCIM_BAR_IO_BASE;
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} else {
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if (bar.pbi_base & PCIM_BAR_MEM_PREFETCH)
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type = "Prefetchable Memory";
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else
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type = "Memory";
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switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
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case PCIM_BAR_MEM_32:
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range = 32;
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base = bar.pbi_base & PCIM_BAR_IO_BASE;
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} else {
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if (bar.pbi_base & PCIM_BAR_MEM_PREFETCH)
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type = "Prefetchable Memory";
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else
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type = "Memory";
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switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
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case PCIM_BAR_MEM_32:
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range = 32;
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break;
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case PCIM_BAR_MEM_1MB:
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range = 20;
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break;
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case PCIM_BAR_MEM_64:
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range = 64;
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break;
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default:
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range = -1;
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}
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base = bar.pbi_base & ~((uint64_t)0xf);
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break;
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case PCIM_BAR_MEM_1MB:
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range = 20;
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break;
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case PCIM_BAR_MEM_64:
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range = 64;
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break;
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default:
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range = -1;
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}
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printf(" bar [%02x] = type %s, range %2d, base %#jx, ",
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PCIR_BAR(i), type, range, (uintmax_t)base);
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printf("size %ju, %s\n", (uintmax_t)bar.pbi_length,
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bar.pbi_enabled ? "enabled" : "disabled");
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base = bar.pbi_base & ~((uint64_t)0xf);
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}
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printf(" %s[%02x] = type %s, range %2d, base %#jx, ",
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label, bar_offset, type, range, (uintmax_t)base);
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printf("size %ju, %s\n", (uintmax_t)bar.pbi_length,
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bar.pbi_enabled ? "enabled" : "disabled");
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}
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static void
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@ -37,6 +37,7 @@ void list_caps(int fd, struct pci_conf *p);
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void list_errors(int fd, struct pci_conf *p);
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uint8_t pci_find_cap(int fd, struct pci_conf *p, uint8_t id);
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uint16_t pcie_find_cap(int fd, struct pci_conf *p, uint16_t id);
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void print_bar(int fd, struct pci_conf *p, const char *label, uint16_t bar);
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uint32_t read_config(int fd, struct pcisel *sel, long reg, int width);
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#endif
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