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H3/A83T: Use PLL_PERIPH/2 for AHB2 parent clock.

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Reviewed by:	manu
This commit is contained in:
Jared McNeill 2016-07-13 20:44:02 +00:00
parent be39349169
commit 814f548cd5
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=302785
1 changed files with 6 additions and 7 deletions
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13
sys/arm/allwinner/clk/aw_ahbclk.c
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@ -140,10 +140,14 @@ aw_ahbclk_init(struct clknode *clk, device_t dev)
A83T_AHB1_CLK_SRC_SEL_SHIFT; A83T_AHB1_CLK_SRC_SEL_SHIFT;
break; break;
case AW_H3_AHB2: case AW_H3_AHB2:
/* Set source to PLL_PERIPH/2 */
index = H3_AHB2_CLK_CFG_PLL_PERIPH_DIV2;
DEVICE_LOCK(sc); DEVICE_LOCK(sc);
AHBCLK_READ(sc, &val); AHBCLK_READ(sc, &val);
val &= ~H3_AHB2_CLK_CFG;
val |= (index << H3_AHB2_CLK_CFG_SHIFT);
AHBCLK_WRITE(sc, val);
DEVICE_UNLOCK(sc); DEVICE_UNLOCK(sc);
index = (val & H3_AHB2_CLK_CFG) >> H3_AHB2_CLK_CFG_SHIFT;
break; break;
default: default:
return (ENXIO); return (ENXIO);
@ -189,12 +193,7 @@ aw_ahbclk_recalc_freq(struct clknode *clk, uint64_t *freq)
pre_div = 1; pre_div = 1;
break; break;
case AW_H3_AHB2: case AW_H3_AHB2:
src_sel = (val & H3_AHB2_CLK_CFG) >> H3_AHB2_CLK_CFG_SHIFT; div = pre_div = 1;
if (src_sel == H3_AHB2_CLK_CFG_PLL_PERIPH_DIV2)
div = 2;
else
div = 1;
pre_div = 1;
break; break;
default: default:
div = 1 << ((val & A10_AHB_CLK_DIV_RATIO) >> div = 1 << ((val & A10_AHB_CLK_DIV_RATIO) >>