[ig4] Add support for CannonLake controllers
They are clocked at 216MHz rate, much higher than previous models. PR: 240485 Submitted by: Neel Chauhan <neel@neelc.org>
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81e8183814
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=354320
@ -115,6 +115,10 @@ static const struct ig4_hw ig4iic_hw[] = {
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.scl_fall_time = 208,
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.sda_hold_time = 207,
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},
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[IG4_CANNONLAKE] = {
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.ic_clock_rate = 216,
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.sda_hold_time = 230,
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},
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};
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static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset);
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@ -912,7 +916,7 @@ ig4iic_set_config(ig4iic_softc_t *sc, bool reset)
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uint32_t v;
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v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
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if (sc->version == IG4_SKYLAKE && (v & IG4_RESTORE_REQUIRED) ) {
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if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) {
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reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED);
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reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);
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pause("i2crst", 1);
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@ -922,7 +926,7 @@ ig4iic_set_config(ig4iic_softc_t *sc, bool reset)
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if ((sc->version == IG4_HASWELL || sc->version == IG4_ATOM) && reset) {
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reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
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reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
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} else if (sc->version == IG4_SKYLAKE && reset) {
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} else if (IG4_HAS_ADDREGS(sc->version) && reset) {
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reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
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reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
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}
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@ -948,7 +952,7 @@ ig4iic_set_config(ig4iic_softc_t *sc, bool reset)
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if (sc->version == IG4_HASWELL) {
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v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
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v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
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} else if (sc->version == IG4_SKYLAKE) {
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} else if (IG4_HAS_ADDREGS(sc->version)) {
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v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
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v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
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}
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@ -1011,7 +1015,7 @@ ig4iic_attach(ig4iic_softc_t *sc)
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ig4iic_get_config(sc);
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error = ig4iic_set_config(sc, sc->version == IG4_SKYLAKE);
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error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version));
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if (error)
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goto done;
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@ -1089,7 +1093,7 @@ ig4iic_suspend(ig4iic_softc_t *sc)
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sx_xlock(&sc->call_lock);
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set_controller(sc, 0);
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if (sc->version == IG4_SKYLAKE) {
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if (IG4_HAS_ADDREGS(sc->version)) {
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/*
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* Place the device in the idle state, just to be safe
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*/
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@ -1111,7 +1115,7 @@ int ig4iic_resume(ig4iic_softc_t *sc)
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int error;
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sx_xlock(&sc->call_lock);
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if (ig4iic_set_config(sc, sc->version == IG4_SKYLAKE))
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if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)))
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device_printf(sc->dev, "controller error during resume\n");
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sx_xunlock(&sc->call_lock);
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@ -1183,7 +1187,7 @@ ig4iic_dump(ig4iic_softc_t *sc)
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if (sc->version == IG4_HASWELL) {
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REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
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REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
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} else if (sc->version == IG4_SKYLAKE) {
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} else if (IG4_HAS_ADDREGS(sc->version)) {
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REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);
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REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);
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}
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@ -90,6 +90,16 @@ static int ig4iic_pci_detach(device_t dev);
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#define PCI_CHIP_APL_I2C_5 0x5ab68086
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#define PCI_CHIP_APL_I2C_6 0x5ab88086
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#define PCI_CHIP_APL_I2C_7 0x5aba8086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086
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#define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086
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#define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086
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#define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086
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#define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086
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struct ig4iic_pci_device {
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uint32_t devid;
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@ -121,7 +131,17 @@ static struct ig4iic_pci_device ig4iic_pci_devices[] = {
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{ PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL},
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{ PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL},
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{ PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL},
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{ PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL}
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{ PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL},
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{ PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE},
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{ PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE},
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{ PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE},
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{ PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE},
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{ PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE},
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{ PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE},
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{ PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE},
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{ PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE},
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{ PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE},
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{ PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE},
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};
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static int
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@ -117,7 +117,7 @@
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#define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */
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/* Available at least on Atom SoCs */
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#define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */
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/* Available on Skylake-U/Y and Kaby Lake-U/Y */
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/* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */
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#define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */
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#define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */
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#define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */
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@ -43,7 +43,10 @@
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#include "pci_if.h"
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#include "iicbus_if.h"
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enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL };
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enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL, IG4_CANNONLAKE };
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/* Controller has additional registers */
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#define IG4_HAS_ADDREGS(vers) ((vers) == IG4_SKYLAKE || \
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(vers) == IG4_CANNONLAKE)
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struct ig4_hw {
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uint32_t ic_clock_rate; /* MHz */
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