Add support for 8 byte hardware watches in long mode. Kernel hardware
watches support 8 byte watches. For userland, we disallow 8 byte watches for 32-bit tasks.
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4fca587ae7
commit
81efc3d94c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=164365
@ -562,7 +562,7 @@ amd64_set_watch(watchnum, watchaddr, size, access, d)
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}
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/*
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* we can watch a 1, 2, or 4 byte sized location
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* we can watch a 1, 2, 4, or 8 byte sized location
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*/
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switch (size) {
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case 1:
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@ -574,6 +574,9 @@ amd64_set_watch(watchnum, watchaddr, size, access, d)
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case 4:
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len = DBREG_DR7_LEN_4;
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break;
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case 8:
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len = DBREG_DR7_LEN_8;
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break;
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default:
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return (-1);
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}
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@ -624,12 +627,14 @@ db_md_set_watchpoint(addr, size)
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avail++;
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}
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if (avail * 4 < size)
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if (avail * 8 < size)
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return (-1);
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for (i = 0; i < 4 && (size > 0); i++) {
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if (!DBREG_DR7_ENABLED(d.dr[7], i)) {
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if (size > 2)
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if (size >= 8 || (avail == 1 && size > 4))
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wsize = 8;
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else if (size > 2)
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wsize = 4;
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else
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wsize = size;
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@ -637,6 +642,7 @@ db_md_set_watchpoint(addr, size)
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DBREG_DR7_WRONLY, &d);
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addr += wsize;
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size -= wsize;
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avail--;
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}
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}
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@ -699,8 +705,12 @@ db_md_list_watchpoints()
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if (DBREG_DR7_ENABLED(d.dr[7], i)) {
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type = DBREG_DR7_ACCESS(d.dr[7], i);
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len = DBREG_DR7_LEN(d.dr[7], i);
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if (len == DBREG_DR7_LEN_8)
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len = 8;
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else
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len++;
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db_printf(" %-5d %-8s %10s %3d ",
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i, "enabled", watchtype_str(type), len + 1);
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i, "enabled", watchtype_str(type), len);
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db_printsym((db_addr_t)DBREG_DRX((&d), i), DB_STGY_ANY);
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db_printf("\n");
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} else {
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@ -1711,7 +1711,8 @@ set_dbregs(struct thread *td, struct dbreg *dbregs)
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for (i = 0; i < 4; i++) {
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if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02)
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return (EINVAL);
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if (DBREG_DR7_LEN(dbregs->dr[7], i) == 0x02)
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if (td->td_frame->tf_cs == _ucode32sel &&
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DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8)
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return (EINVAL);
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}
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if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 ||
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@ -97,6 +97,7 @@ struct dbreg {
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#define DBREG_DR7_LEN_1 0x00 /* 1 byte length */
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#define DBREG_DR7_LEN_2 0x01
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#define DBREG_DR7_LEN_4 0x03
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#define DBREG_DR7_LEN_8 0x02
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#define DBREG_DR7_EXEC 0x00 /* break on execute */
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#define DBREG_DR7_WRONLY 0x01 /* break on write */
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#define DBREG_DR7_RDWR 0x03 /* break on read or write */
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