rtsx: Number of tweaks for RTS5260.
MFC after: 2 weeks
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68b0a79b7c
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8290c14420
@ -24,7 +24,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd February 10, 2022
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.Dd April 26, 2022
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.Dt RTSX 4
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.Os
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.Sh NAME
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@ -34,18 +34,18 @@
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To compile this driver into the kernel, place the following
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lines in the kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device mmc"
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.Cd "device mmcsd"
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.Cd "device rtsx"
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.Cd device mmc
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.Cd device mmcsd
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.Cd device rtsx
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.Ed
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.Pp
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Alternatively, to load the driver as a module at boot time,
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place the following lines in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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mmc_load="YES"
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mmcsd_load="YES"
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rtsx_load="YES"
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.Cd mmc_load="YES"
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.Cd mmcsd_load="YES"
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.Cd rtsx_load="YES"
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.Ed
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.Sh DESCRIPTION
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The
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@ -136,4 +136,10 @@ If this automation is wrong, it can be avoided by adding in
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Mounting a filesystem with write access on a card write protected may involve a kernel crash.
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.It
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Suspend/Resume do not work under MMCCAM.
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.It
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For some chips (e.g. RTS5260) after
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.Cd devctl disable/enable
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or
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.Cd kldunload/kldload
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the driver can't detect a card correctly.
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.El
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@ -172,23 +172,23 @@ struct rtsx_softc {
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#define RTSX_RTL8411 0x5289
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#define RTSX_RTL8411B 0x5287
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#define RTSX_VERSION "2.1f-1"
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#define RTSX_VERSION "2.1g"
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static const struct rtsx_device {
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uint16_t vendor_id;
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uint16_t device_id;
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const char *desc;
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} rtsx_devices[] = {
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{ RTSX_REALTEK, RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS5260, RTSX_VERSION " Realtek RTS5260 PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe MMC/SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTS5260, RTSX_VERSION " Realtek RTS5260 PCIe SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe SD Card Reader"},
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{ RTSX_REALTEK, RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe SD Card Reader"},
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{ 0, 0, NULL}
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};
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@ -886,7 +886,7 @@ rtsx_init(struct rtsx_softc *sc)
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device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags);
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/* Enable interrupts. */
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sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN | RTSX_MS_INT_EN;
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sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN;
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WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled);
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/* Power on SSC clock. */
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@ -1035,8 +1035,12 @@ rtsx_init(struct rtsx_softc *sc)
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/* Enable interrupt write-clear (default is read-clear). */
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RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR);
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if (sc->rtsx_device_id == RTSX_RTS525A)
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switch (sc->rtsx_device_id) {
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case RTSX_RTS525A:
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case RTSX_RTS5260:
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RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, 1, 1);
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break;
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}
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/* OC power down. */
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RTSX_BITOP(sc, RTSX_FPDCTL, RTSX_SD_OC_POWER_DOWN, RTSX_SD_OC_POWER_DOWN);
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@ -1208,22 +1212,33 @@ rtsx_init(struct rtsx_softc *sc)
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/* Set mcu_cnt to 7 to ensure data can be sampled properly. */
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RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07);
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RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, 0x5D);
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/* force no MDIO*/
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/* Force no MDIO */
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RTSX_WRITE(sc, RTSX_RTS5260_AUTOLOAD_CFG4, RTSX_RTS5260_MIMO_DISABLE);
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/*Modify SDVCC Tune Default Parameters!*/
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/* Modify SDVCC Tune Default Parameters! */
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RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33);
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RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL);
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RTSX_BITOP(sc, RTSX_L1SUB_CONFIG1, RTSX_AUX_CLK_ACTIVE_SEL_MASK, RTSX_MAC_CKSW_DONE);
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/* Rest L1SUB Config */
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RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xFF);
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RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, RTSX_CLK_PM_EN, RTSX_CLK_PM_EN);
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RTSX_WRITE(sc, RTSX_PWD_SUSPEND_EN, 0xFF);
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RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_PWR_GATE_EN, RTSX_PWR_GATE_EN);
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RTSX_BITOP(sc, RTSX_RB_FLUSH, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE);
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RTSX_BITOP(sc, RTSX_REG_VREF, RTSX_PWD_SUSPND_EN, RTSX_PWD_SUSPND_EN);
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RTSX_BITOP(sc, RTSX_RBCTL, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE);
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if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
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RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0);
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else
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RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80);
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RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_DISABLE);
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RTSX_CLR(sc, RTSX_RTS5260_DVCC_CTRL, RTSX_RTS5260_DVCC_OCP_EN | RTSX_RTS5260_DVCC_OCP_CL_EN);
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/* CLKREQ# PIN will be forced to drive low. */
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RTSX_BITOP(sc, RTSX_PETXCFG, RTSX_FORCE_CLKREQ_DELINK_MASK, RTSX_FORCE_CLKREQ_LOW);
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RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10);
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break;
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case RTSX_RTL8402:
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case RTSX_RTL8411:
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@ -1472,6 +1487,13 @@ rtsx_bus_power_off(struct rtsx_softc *sc)
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RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK);
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break;
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case RTSX_RTS5260:
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rtsx_stop_cmd(sc);
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/* Switch vccq to 330 */
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RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1);
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RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33);
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RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8);
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rtsx_rts5260_fill_driving(sc);
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RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_OFF);
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RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWEROFF);
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break;
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@ -1675,12 +1697,19 @@ rtsx_bus_power_on(struct rtsx_softc *sc)
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DELAY(20000);
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RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK | RTSX_SD_ASYNC_FIFO_NOT_RST,
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RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST);
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RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CLK_LOW_FREQ);
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RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE,
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RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1);
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RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ);
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/* Initialize SD_CFG1 register */
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RTSX_WRITE(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128 | RTSX_SD20_MODE);
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RTSX_WRITE(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_POS_EDGE);
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RTSX_CLR(sc, RTSX_SD_PUSH_POINT_CTL, 0xff);
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RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_MS_STOP | RTSX_SD_CLR_ERR,
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RTSX_MS_STOP | RTSX_SD_CLR_ERR);
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RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR,
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RTSX_SD_STOP | RTSX_SD_CLR_ERR);
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/* Reset SD_CFG3 register */
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RTSX_CLR(sc, RTSX_SD_CFG3, RTSX_SD30_CLK_END_EN);
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RTSX_CLR(sc, RTSX_REG_SD_STOP_SDCLK_CFG,
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@ -2266,11 +2295,12 @@ rtsx_stop_cmd(struct rtsx_softc *sc)
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RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST);
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rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
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break;
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}
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rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST);
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default:
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rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST);
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rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
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rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
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break;
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}
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}
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/*
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@ -3286,6 +3316,7 @@ rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused)
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case RTSX_RTS5260:
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RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1);
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RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33);
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RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8);
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if ((error = rtsx_rts5260_fill_driving(sc)))
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return (error);
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break;
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@ -725,12 +725,16 @@
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#define RTSX_DUMMY_REG 0xFE90
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#define RTSX_REG_VREF 0xFE97
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#define RTSX_PWD_SUSPND_EN 0x10
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#define RTSX_RTS5260_DMA_RST_CTL_0 0xFEBF
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#define RTSX_RTS5260_DMA_RST 0x80
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#define RTSX_RTS5260_ADMA3_RST 0x40
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#define RTSX_PETXCFG 0xFF03 /* was 0xFE49 in OpenBSD */
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#define RTSX_PETXCFG_CLKREQ_PIN 0x08
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#define RTSX_FORCE_CLKREQ_DELINK_MASK 0x80
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#define RTSX_FORCE_CLKREQ_LOW 0x80
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#define RTSX_RREF_CFG 0xFF6C
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#define RTSX_RREF_VBGSEL_MASK 0x38
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@ -775,6 +779,11 @@
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#define RTSX_LDO_POW_SDVDD1_ON 0x08
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#define RTSX_LDO_POW_SDVDD1_OFF 0x00
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#define RTSX_RTS5260_DVCC_CTRL 0xFF73
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#define RTSX_RTS5260_DVCC_OCP_EN (0x01 << 7)
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#define RTSX_RTS5260_DVCC_OCP_THD_MASK (0x07 << 4)
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#define RTSX_RTS5260_DVCC_POWERON (0x01 << 3)
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#define RTSX_RTS5260_DVCC_OCP_CL_EN (0x01 << 2)
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#define RTSX_LDO_VIO_CFG 0xFF75
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#define RTSX_LDO_VIO_TUNE_MASK 0x07
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