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Reduce default shift used to calculate the max frequency for the TSC

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timecounter to 1, and correspondingly increase the precision of the
gettimeofday(2) and related functions in the default configuration.

The motivation for the TSC-low timecounter, as described in the
r222866, seems to provide a workaround for the non-serializing
behaviour of the RDTSC on some Intel hardware.  Tests demonstrate that
even with the pre-shift of 8, the cross-core non-monotonicity of the
RDTSC is still observed reliably, e.g. on the Nehalems.  The r238755
and r238973 implemented the proper fix for the issue.

The pre-shift of 1 is applied to keep TSC not overflowing for the
frequency of hardclock down to 2 sec/intr.  The pre-shift is made a
tunable to allow the easy debugging of the issues users could see with
the shift being too low.

Reviewed by:	bde
MFC after:	2 weeks
This commit is contained in:
Konstantin Belousov 2013-01-30 12:43:10 +00:00
parent 7e7b1248d1
commit 82c3d173cc
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=246116
1 changed files with 7 additions and 1 deletions
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8
sys/x86/x86/tsc.c
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@ -65,6 +65,12 @@ static int smp_tsc;
SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc, CTLFLAG_RDTUN, &smp_tsc, 0,
"Indicates whether the TSC is safe to use in SMP mode");
TUNABLE_INT("kern.timecounter.smp_tsc", &smp_tsc);
static int smp_tsc_shift = 1;
SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc_shift, CTLFLAG_RDTUN,
&smp_tsc_shift, 0,
"Shift to pre-apply for the maximum TSC frequency in SMP mode");
TUNABLE_INT("kern.timecounter.smp_tsc_shift", &smp_tsc_shift);
#endif
static int tsc_disabled;
@ -506,7 +512,7 @@ init_TSC_tc(void)
tsc_timecounter.tc_quality = -100;
} else {
tsc_timecounter.tc_quality = test_smp_tsc();
max_freq >>= 8;
max_freq >>= smp_tsc_shift;
}
} else
#endif