diff --git a/sys/arm/freescale/imx/imx_machdep.c b/sys/arm/freescale/imx/imx_machdep.c
index 3c607140c605..12e41720d25c 100644
--- a/sys/arm/freescale/imx/imx_machdep.c
+++ b/sys/arm/freescale/imx/imx_machdep.c
@@ -69,11 +69,18 @@ imx_wdog_cpu_reset(vm_offset_t wdcr_physaddr)
 	 * Trigger an immediate reset by clearing the SRS bit in the watchdog
 	 * control register.  The reset happens on the next cycle of the wdog
 	 * 32KHz clock, so hang out in a spin loop until the reset takes effect.
+	 *
+	 * Imx6 erratum ERR004346 says the SRS bit has to be cleared twice
+	 * within the same cycle of the 32khz clock to reliably trigger the
+	 * reset.  Writing it 3 times in a row ensures at least 2 of the writes
+	 * happen in the same 32k clock cycle.
 	 */
 	if ((pcr = devmap_ptov(wdcr_physaddr, sizeof(*pcr))) == NULL) {
 		printf("cpu_reset() can't find its control register... locking up now.");
 	} else {
 		*pcr &= ~WDOG_CR_SRS;
+		*pcr &= ~WDOG_CR_SRS;
+		*pcr &= ~WDOG_CR_SRS;
 	}
 	for (;;)
 		continue;