From 83ae3d5531a95eb3b75469c3c6e0e2face5c6eb9 Mon Sep 17 00:00:00 2001 From: Nathan Whitehorn Date: Sun, 22 Apr 2012 20:23:34 +0000 Subject: [PATCH] On non-64-bit systems (which generally don't have lwsync), use eieio and isync to implement read and write barriers, following Appendix B.2 of Book II of the architecture manual. This provides a 25% speed increase to fork() on the PowerPC G4. --- sys/powerpc/include/atomic.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/sys/powerpc/include/atomic.h b/sys/powerpc/include/atomic.h index 9a77dc221c08..5ff64fb2482e 100644 --- a/sys/powerpc/include/atomic.h +++ b/sys/powerpc/include/atomic.h @@ -38,8 +38,13 @@ /* NOTE: lwsync is equivalent to sync on systems without lwsync */ #define mb() __asm __volatile("lwsync" : : : "memory") +#ifdef __powerpc64__ #define wmb() __asm __volatile("lwsync" : : : "memory") #define rmb() __asm __volatile("lwsync" : : : "memory") +#else +#define wmb() __asm __volatile("eieio" : : : "memory") +#define rmb() __asm __volatile("isync" : : : "memory") +#endif /* * atomic_add(p, v)