Add another hardware bug workaround for Yukon II controllers that
have hardware ram buffer. The silicon bug seem to be triggered by pause frames if receive buffer is not aligned on FIFO word(8 bytes). To workaround the issue, make sure to align Rx buffers on 8 bytes. Unfortunately this workaround requires yet another Rx fixup for strict alignment architecture machines to align IP header. For newer hardwares that lacks ram buffer may not have this bug so check number of available ram buffer size to see the existence of ram buffer. Reported by: Ian Freislich (ianf <at> clue dot co dot za), das Tested by: Ian Freislich (ianf <at> clue dot co dot za)
This commit is contained in:
Pyun YongHyeon
parent
4e01238d67
commit
83c04c93b6
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=183346
@ -244,6 +244,9 @@ static __inline void msk_rxput(struct msk_if_softc *);
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static int msk_handle_events(struct msk_softc *);
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static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
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static void msk_intr_hwerr(struct msk_softc *);
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#ifndef __NO_STRICT_ALIGNMENT
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static __inline void msk_fixup_rx(struct mbuf *);
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#endif
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static void msk_rxeof(struct msk_if_softc *, uint32_t, int);
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static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int);
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static void msk_txeof(struct msk_if_softc *, int);
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@ -783,7 +786,12 @@ msk_newbuf(struct msk_if_softc *sc_if, int idx)
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return (ENOBUFS);
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m->m_len = m->m_pkthdr.len = MCLBYTES;
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m_adj(m, ETHER_ALIGN);
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if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
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m_adj(m, ETHER_ALIGN);
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#ifndef __NO_STRICT_ALIGNMENT
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else
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m_adj(m, MSK_RX_BUF_ALIGN);
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#endif
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if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
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sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
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@ -840,7 +848,12 @@ msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
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return (ENOBUFS);
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}
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m->m_pkthdr.len = m->m_len = MSK_JLEN;
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m_adj(m, ETHER_ALIGN);
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if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
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m_adj(m, ETHER_ALIGN);
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#ifndef __NO_STRICT_ALIGNMENT
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else
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m_adj(m, MSK_RX_BUF_ALIGN);
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#endif
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if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
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sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
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@ -1041,14 +1054,16 @@ mskc_setup_rambuffer(struct msk_softc *sc)
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{
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int next;
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int i;
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uint8_t val;
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/* Get adapter SRAM size. */
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val = CSR_READ_1(sc, B2_E_0);
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sc->msk_ramsize = (val == 0) ? 128 : val * 4;
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sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
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if (bootverbose)
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device_printf(sc->msk_dev,
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"RAM buffer size : %dKB\n", sc->msk_ramsize);
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if (sc->msk_ramsize == 0)
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return (0);
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sc->msk_pflags |= MSK_FLAG_RAMBUF;
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/*
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* Give receiver 2/3 of memory and round down to the multiple
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* of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple
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@ -1412,6 +1427,7 @@ msk_attach(device_t dev)
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sc_if->msk_if_dev = dev;
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sc_if->msk_port = port;
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sc_if->msk_softc = sc;
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sc_if->msk_flags = sc->msk_pflags;
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sc->msk_if[port] = sc_if;
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/* Setup Tx/Rx queue register offsets. */
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if (port == MSK_PORT_A) {
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@ -1976,6 +1992,7 @@ msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
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struct msk_rxdesc *jrxd;
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struct msk_jpool_entry *entry;
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uint8_t *ptr;
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bus_size_t rxalign;
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int error, i;
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mtx_init(&sc_if->msk_jlist_mtx, "msk_jlist_mtx", NULL, MTX_DEF);
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@ -2107,9 +2124,16 @@ msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
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goto fail;
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}
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rxalign = 1;
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/*
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* Workaround hardware hang which seems to happen when Rx buffer
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* is not aligned on multiple of FIFO word(8 bytes).
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*/
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if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
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rxalign = MSK_RX_BUF_ALIGN;
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/* Create tag for Rx buffers. */
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error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
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1, 0, /* alignment, boundary */
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rxalign, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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@ -2918,6 +2942,23 @@ mskc_resume(device_t dev)
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return (0);
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}
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#ifndef __NO_STRICT_ALIGNMENT
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static __inline void
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msk_fixup_rx(struct mbuf *m)
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{
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int i;
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uint16_t *src, *dst;
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src = mtod(m, uint16_t *);
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dst = src - 3;
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for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
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*dst++ = *src++;
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m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN);
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}
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#endif
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static void
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msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
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{
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@ -2955,6 +2996,10 @@ msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
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}
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m->m_pkthdr.rcvif = ifp;
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m->m_pkthdr.len = m->m_len = len;
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#ifndef __NO_STRICT_ALIGNMENT
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if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
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msk_fixup_rx(m);
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#endif
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ifp->if_ipackets++;
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/* Check for VLAN tagged packets. */
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if ((status & GMR_FS_VLAN) != 0 &&
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@ -3008,6 +3053,10 @@ msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
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}
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m->m_pkthdr.rcvif = ifp;
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m->m_pkthdr.len = m->m_len = len;
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#ifndef __NO_STRICT_ALIGNMENT
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if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
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msk_fixup_rx(m);
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#endif
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ifp->if_ipackets++;
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/* Check for VLAN tagged packets. */
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if ((status & GMR_FS_VLAN) != 0 &&
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@ -3677,7 +3726,7 @@ msk_init_locked(struct msk_if_softc *sc_if)
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/* Configure hardware VLAN tag insertion/stripping. */
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msk_setvlan(sc_if, ifp);
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if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
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if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
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/* Set Rx Pause threshould. */
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CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
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MSK_ECU_LLPP);
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@ -3790,6 +3839,8 @@ msk_set_rambuffer(struct msk_if_softc *sc_if)
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int ltpp, utpp;
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sc = sc_if->msk_softc;
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if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
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return;
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/* Setup Rx Queue. */
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CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
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@ -2158,6 +2158,7 @@ struct msk_stat_desc {
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#define MSK_TX_RING_CNT 256
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#define MSK_RX_RING_CNT 256
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#define MSK_RX_BUF_ALIGN 8
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#define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT
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#define MSK_STAT_RING_CNT ((1 + 3) * (MSK_TX_RING_CNT + MSK_RX_RING_CNT))
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#define MSK_MAXTXSEGS 32
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@ -2307,6 +2308,7 @@ struct msk_softc {
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uint32_t msk_coppertype;
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uint32_t msk_intrmask;
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uint32_t msk_intrhwemask;
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uint32_t msk_pflags;
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int msk_suspended;
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int msk_clock;
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int msk_msi;
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@ -2348,6 +2350,8 @@ struct msk_if_softc {
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int msk_phytype;
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int msk_phyaddr;
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int msk_link;
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uint32_t msk_flags;
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#define MSK_FLAG_RAMBUF 0x0010
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struct callout msk_tick_ch;
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int msk_watchdog_timer;
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uint32_t msk_txq; /* Tx. Async Queue offset */
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