Two more mxge watchdog fixes:
1) Restore the PCI Express control register after a watchdog reset. This is required because the device will come out of watchdog reset with the pectl reg at its default state, and important BIOS configuration (like max payload size) could be lost. 2) Call mxge_start_locked() for every tx queue before dropping the lock in the watchdog handler. This is required, as the queue's buf ring may have filled during the reset.
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commit
83d54b590f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=197645
@ -3701,10 +3701,16 @@ mxge_setup_cfg_space(mxge_softc_t *sc)
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if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
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lnk = pci_read_config(dev, reg + 0x12, 2);
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sc->link_width = (lnk >> 4) & 0x3f;
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pectl = pci_read_config(dev, reg + 0x8, 2);
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pectl = (pectl & ~0x7000) | (5 << 12);
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pci_write_config(dev, reg + 0x8, pectl, 2);
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if (sc->pectl == 0) {
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pectl = pci_read_config(dev, reg + 0x8, 2);
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pectl = (pectl & ~0x7000) | (5 << 12);
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pci_write_config(dev, reg + 0x8, pectl, 2);
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sc->pectl = pectl;
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} else {
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/* restore saved pectl after watchdog reset */
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pci_write_config(dev, reg + 0x8, sc->pectl, 2);
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}
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}
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/* Enable DMA and Memory space access */
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@ -3816,6 +3822,9 @@ mxge_watchdog_reset(mxge_softc_t *sc, int slice)
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/* release all TX locks */
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for (s = 0; s < num_tx_slices; s++) {
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ss = &sc->ss[s];
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#ifdef IFNET_BUF_RING
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mxge_start_locked(ss);
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#endif
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mtx_unlock(&ss->tx.mtx);
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}
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}
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@ -274,6 +274,7 @@ struct mxge_softc {
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struct sysctl_ctx_list slice_sysctl_ctx;
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char *mac_addr_string;
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uint8_t mac_addr[6]; /* eeprom mac address */
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uint16_t pectl; /* save PCIe CTL state */
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char product_code_string[64];
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char serial_number_string[64];
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char cmd_mtx_name[16];
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