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Update DPAA SDK to SDK 2.0

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This adds some support for ARM as well as 64-bit.  64-bit on PowerPC is
currently not working, and ARM support has not been completed or tested on the
FreeBSD side.

As this was imported from a Linux tree, it includes some Linux-isms
(ioread/iowrite), so compile with the LinuxKPI for now.  This may change in the
future.
This commit is contained in:
Justin Hibbits 2017-10-30 03:41:04 +00:00
parent 50ee2e2aab
commit 852ba10081
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=325118
147 changed files with 54490 additions and 22761 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
sys/contrib/ncsw/Peripherals/BM/bm.h
View File

@ -41,6 +41,7 @@
#ifndef __BM_H
#define __BM_H
#include "xx_common.h"
#include "bm_ext.h"
#include "mm_ext.h"
@ -261,7 +262,7 @@ typedef struct {
t_Handle h_Bm;
struct bm_portal *p_BmPortalLow;
t_BmPortalCallbacks cbs[BM_NUM_OF_RINGS];
int irq;
uintptr_t irq;
int cpu; /* This is used for any "core-affine" portals, ie. default portals
* associated to the corresponding cpu. -1 implies that there is no core
* affinity configured. */
@ -303,7 +304,7 @@ typedef struct {
uint32_t exceptions;
t_BmExceptionsCallback *f_Exception;
t_Handle h_App;
int errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */
uintptr_t errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */
t_BmDriverParams *p_BmDriverParams;
} t_Bm;
@ -339,7 +340,7 @@ static __inline__ void BmCommit(t_BmPortal *p_BmPortal, bmRingType_t type, uint8
static __inline__ uint32_t BmBpidGet(t_Bm *p_Bm, bool force, uint32_t base)
{
uint64_t ans, size = 1;
uint32_t alignment = 1;
uint64_t alignment = 1;
if (force)
{
@ -347,7 +348,7 @@ static __inline__ uint32_t BmBpidGet(t_Bm *p_Bm, bool force, uint32_t base)
{
ans = MM_GetForce(p_Bm->h_BpidMm,
base,
(int)size,
size,
"BM BPID MEM");
ans = base;
}
@ -394,6 +395,7 @@ static __inline__ uint32_t BmBpidGet(t_Bm *p_Bm, bool force, uint32_t base)
size,
alignment,
"BM BPID MEM");
KASSERT(ans < UINT32_MAX, ("Oops, %lx > UINT32_MAX!\n", ans));
return (uint32_t)ans;
}

20
sys/contrib/ncsw/Peripherals/BM/bm_pool.c
View File

@ -545,26 +545,6 @@ t_Handle BM_POOL_GetBufferContext(t_Handle h_BmPool, void *p_Buff)
return *(t_Handle *)PTR_MOVE(p_Buff, -(sizeof(t_Handle)));
}
void * BM_POOL_PhysToVirt(t_Handle h_BmPool, physAddress_t addr)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_VALUE(p_BmPool, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE, NULL);
return p_BmPool->bufferPoolInfo.f_PhysToVirt(addr);
}
physAddress_t BM_POOL_VirtToPhys(t_Handle h_BmPool, void *p_Buff)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_VALUE(p_BmPool, E_INVALID_HANDLE, (physAddress_t)0);
SANITY_CHECK_RETURN_VALUE(!p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE, (physAddress_t)0);
return p_BmPool->bufferPoolInfo.f_VirtToPhys(p_Buff);
}
uint32_t BM_POOL_GetCounter(t_Handle h_BmPool, e_BmPoolCounters counter)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;

12
sys/contrib/ncsw/Peripherals/BM/bman_low.c
View File

@ -38,6 +38,10 @@
@Description BM low-level implementation
*//***************************************************************************/
#include <sys/cdefs.h>
#include <sys/types.h>
#include <machine/atomic.h>
#include "std_ext.h"
#include "core_ext.h"
#include "xx_ext.h"
@ -259,7 +263,7 @@ void bm_rcr_pci_commit(struct bm_portal *portal, uint8_t myverb)
rcr->cursor->__dont_write_directly__verb = (uint8_t)(myverb | rcr->vbit);
RCR_INC(rcr);
rcr->available--;
hwsync();
mb();
bm_out(RCR_PI_CINH, RCR_PTR2IDX(rcr->cursor));
#ifdef BM_CHECKING
rcr->busy = 0;
@ -281,7 +285,7 @@ void bm_rcr_pce_commit(struct bm_portal *portal, uint8_t myverb)
rcr->cursor->__dont_write_directly__verb = (uint8_t)(myverb | rcr->vbit);
RCR_INC(rcr);
rcr->available--;
lwsync();
wmb();
bm_cl_out(RCR_PI, RCR_PTR2IDX(rcr->cursor));
#ifdef BM_CHECKING
rcr->busy = 0;
@ -294,7 +298,7 @@ void bm_rcr_pvb_commit(struct bm_portal *portal, uint8_t myverb)
struct bm_rcr_entry *rcursor;
ASSERT_COND(rcr->busy);
ASSERT_COND(rcr->pmode == e_BmPortalPVB);
lwsync();
rmb();
rcursor = rcr->cursor;
rcursor->__dont_write_directly__verb = (uint8_t)(myverb | rcr->vbit);
dcbf_64(rcursor);
@ -432,7 +436,7 @@ void bm_mc_commit(struct bm_portal *portal, uint8_t myverb)
{
register struct bm_mc *mc = &portal->mc;
ASSERT_COND(mc->state == mc_user);
lwsync();
rmb();
mc->cr->__dont_write_directly__verb = (uint8_t)(myverb | mc->vbit);
dcbf_64(mc->cr);
dcbit_ro(mc->rr + mc->rridx);

85
sys/contrib/ncsw/Peripherals/BM/bman_private.h
View File

@ -54,76 +54,13 @@
* and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or
* execution reordering with respect to other code/instructions that manipulate
* the same cacheline. */
#ifdef CORE_E500MC
#if defined(_DIAB_TOOL)
#define hwsync() \
do { \
__asm__ __volatile__ ("sync"); \
} while(0)
#define lwsync() \
do { \
__asm__ __volatile__ ("lwsync"); \
} while(0)
__asm__ __volatile__ void dcbf (volatile void * addr)
{
%reg addr
dcbf r0, addr
}
__asm__ __volatile__ void dcbt_ro (volatile void * addr)
{
%reg addr
dcbt r0, addr
}
__asm__ __volatile__ void dcbt_rw (volatile void * addr)
{
%reg addr
dcbtst r0, addr
}
__asm__ __volatile__ void dcbzl (volatile void * addr)
{
%reg addr
dcbzl r0, addr
}
#define dcbz_64(p) \
do { \
dcbzl(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbt_ro(p); \
} while (0)
#else /* GNU C */
#define hwsync() \
do { \
__asm__ __volatile__ ("sync" : : : "memory"); \
} while(0)
#define lwsync() \
do { \
__asm__ __volatile__ ("lwsync" : : : "memory"); \
} while(0)
#define dcbf(addr) \
do { \
__asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \
} while(0)
#ifdef CORE_E500MC
#define dcbt_ro(addr) \
do { \
__asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \
@ -156,46 +93,34 @@ __asm__ __volatile__ void dcbzl (volatile void * addr)
dcbt_ro(p); \
} while (0)
#endif /* _DIAB_TOOL */
#else
#define hwsync CORE_MemoryBarrier
#define lwsync hwsync
#define dcbf(p) \
do { \
__asm__ __volatile__ ("dcbf 0,%0" : : "r" (p)); \
} while(0)
#define dcbt_ro(p) \
do { \
__asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \
lwsync(); \
} while(0)
#define dcbt_rw(p) \
do { \
__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \
} while(0)
#define dcbz(p) \
do { \
__asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \
} while (0)
#define dcbz_64(p) \
do { \
dcbz((uint32_t)p + 32); \
dcbz((char *)p + 32); \
dcbz(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf((uint32_t)p + 32); \
dcbf((char *)p + 32); \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbi((uint32_t)p + 32); \
dcbi((char *)p + 32); \
dcbt_ro(p); \
dcbt_ro((uint32_t)p + 32); \
dcbt_ro((char *)p + 32); \
} while (0)
#endif /* CORE_E500MC */

1505
sys/contrib/ncsw/Peripherals/FM/HC/hc.c
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File diff suppressed because it is too large Load Diff

1659
sys/contrib/ncsw/Peripherals/FM/MAC/dtsec.c
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File diff suppressed because it is too large Load Diff

518
sys/contrib/ncsw/Peripherals/FM/MAC/dtsec.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -41,81 +41,58 @@
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "enet_ext.h"
#include "dtsec_mii_acc.h"
#include "fm_mac.h"
#define PEMASK_TSRE 0x00010000
#define DEFAULT_exceptions \
((uint32_t)(DTSEC_IMASK_BREN | \
DTSEC_IMASK_RXCEN | \
DTSEC_IMASK_BTEN | \
DTSEC_IMASK_TXCEN | \
DTSEC_IMASK_TXEEN | \
DTSEC_IMASK_ABRTEN | \
DTSEC_IMASK_LCEN | \
DTSEC_IMASK_CRLEN | \
DTSEC_IMASK_XFUNEN | \
DTSEC_IMASK_IFERREN | \
DTSEC_IMASK_MAGEN | \
DTSEC_IMASK_TDPEEN | \
DTSEC_IMASK_RDPEEN))
#define IMASK_BREN 0x80000000
#define IMASK_RXCEN 0x40000000
#define IMASK_MSROEN 0x04000000
#define IMASK_GTSCEN 0x02000000
#define IMASK_BTEN 0x01000000
#define IMASK_TXCEN 0x00800000
#define IMASK_TXEEN 0x00400000
#define IMASK_LCEN 0x00040000
#define IMASK_CRLEN 0x00020000
#define IMASK_XFUNEN 0x00010000
#define IMASK_ABRTEN 0x00008000
#define IMASK_IFERREN 0x00004000
#define IMASK_MAGEN 0x00000800
#define IMASK_MMRDEN 0x00000400
#define IMASK_MMWREN 0x00000200
#define IMASK_GRSCEN 0x00000100
#define IMASK_TDPEEN 0x00000002
#define IMASK_RDPEEN 0x00000001
#define EVENTS_MASK ((uint32_t)(IMASK_BREN | \
IMASK_RXCEN | \
IMASK_MSROEN | \
IMASK_GTSCEN | \
IMASK_BTEN | \
IMASK_TXCEN | \
IMASK_TXEEN | \
IMASK_ABRTEN | \
IMASK_LCEN | \
IMASK_CRLEN | \
IMASK_XFUNEN | \
IMASK_IFERREN | \
IMASK_MAGEN | \
IMASK_MMRDEN | \
IMASK_MMWREN | \
IMASK_GRSCEN | \
IMASK_TDPEEN | \
IMASK_RDPEEN))
#define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \
case e_FM_MAC_EX_1G_BAB_RX: \
bitMask = IMASK_BREN; break; \
case e_FM_MAC_EX_1G_RX_CTL: \
bitMask = IMASK_RXCEN; break; \
case e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET: \
bitMask = IMASK_GTSCEN ; break; \
case e_FM_MAC_EX_1G_BAB_TX: \
bitMask = IMASK_BTEN ; break; \
case e_FM_MAC_EX_1G_TX_CTL: \
bitMask = IMASK_TXCEN ; break; \
case e_FM_MAC_EX_1G_TX_ERR: \
bitMask = IMASK_TXEEN ; break; \
case e_FM_MAC_EX_1G_LATE_COL: \
bitMask = IMASK_LCEN ; break; \
case e_FM_MAC_EX_1G_COL_RET_LMT: \
bitMask = IMASK_CRLEN ; break; \
case e_FM_MAC_EX_1G_TX_FIFO_UNDRN: \
bitMask = IMASK_XFUNEN ; break; \
case e_FM_MAC_EX_1G_MAG_PCKT: \
bitMask = IMASK_MAGEN ; break; \
case e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET: \
bitMask = IMASK_MMRDEN; break; \
case e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET: \
bitMask = IMASK_MMWREN ; break; \
case e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET: \
bitMask = IMASK_GRSCEN; break; \
case e_FM_MAC_EX_1G_TX_DATA_ERR: \
bitMask = IMASK_TDPEEN; break; \
case e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL: \
bitMask = IMASK_MSROEN ; break; \
#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MAC_EX_1G_BAB_RX: \
bitMask = DTSEC_IMASK_BREN; break; \
case e_FM_MAC_EX_1G_RX_CTL: \
bitMask = DTSEC_IMASK_RXCEN; break; \
case e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET: \
bitMask = DTSEC_IMASK_GTSCEN ; break; \
case e_FM_MAC_EX_1G_BAB_TX: \
bitMask = DTSEC_IMASK_BTEN ; break; \
case e_FM_MAC_EX_1G_TX_CTL: \
bitMask = DTSEC_IMASK_TXCEN ; break; \
case e_FM_MAC_EX_1G_TX_ERR: \
bitMask = DTSEC_IMASK_TXEEN ; break; \
case e_FM_MAC_EX_1G_LATE_COL: \
bitMask = DTSEC_IMASK_LCEN ; break; \
case e_FM_MAC_EX_1G_COL_RET_LMT: \
bitMask = DTSEC_IMASK_CRLEN ; break; \
case e_FM_MAC_EX_1G_TX_FIFO_UNDRN: \
bitMask = DTSEC_IMASK_XFUNEN ; break; \
case e_FM_MAC_EX_1G_MAG_PCKT: \
bitMask = DTSEC_IMASK_MAGEN ; break; \
case e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET: \
bitMask = DTSEC_IMASK_MMRDEN; break; \
case e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET: \
bitMask = DTSEC_IMASK_MMWREN ; break; \
case e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET: \
bitMask = DTSEC_IMASK_GRSCEN; break; \
case e_FM_MAC_EX_1G_TX_DATA_ERR: \
bitMask = DTSEC_IMASK_TDPEEN; break; \
case e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL: \
bitMask = DTSEC_IMASK_MSROEN ; break; \
default: bitMask = 0;break;}
@ -145,192 +122,18 @@ typedef uint32_t t_ErrorDisable;
#define HASH_TABLE_SIZE 256 /* Hash table size (= 32 bits * 8 regs) */
#define DTSEC_TO_MII_OFFSET 0x1120 /* number of pattern match registers (entries) */
#define DEFAULT_errorDisabled 0
#define DEFAULT_promiscuousEnable FALSE
#define DEFAULT_pauseExtended 0x0
#define DEFAULT_pauseTime 0xf000
#define DEFAULT_halfDuplex FALSE
#define DEFAULT_halfDulexFlowControlEn FALSE
#define DEFAULT_txTimeStampEn FALSE
#define DEFAULT_rxTimeStampEn FALSE
#define DEFAULT_packetAlignment 0
#define DEFAULT_controlFrameAccept FALSE
#define DEFAULT_groupHashExtend FALSE
#define DEFAULT_broadcReject FALSE
#define DEFAULT_rxShortFrame TRUE
#define DEFAULT_exactMatch FALSE
#define DEFAULT_debugMode FALSE
#define DEFAULT_loopback FALSE
#define DEFAULT_actOnRxPauseFrame TRUE
#define DEFAULT_actOnTxPauseFrame TRUE
#define DEFAULT_PreAmLength 0x7
#define DEFAULT_PreAmRxEn FALSE
#define DEFAULT_PreAmTxEn FALSE
#define DEFAULT_lengthCheckEnable FALSE
#define DEFAULT_padAndCrcEnable TRUE
#define DEFAULT_crcEnable FALSE
#define DEFAULT_nonBackToBackIpg1 0x40
#define DEFAULT_nonBackToBackIpg2 0x60
#define DEFAULT_minIfgEnforcement 0x50
#define DEFAULT_backToBackIpg 0x60
#define DEFAULT_altBackoffVal 0x0A
#define DEFAULT_altBackoffEnable FALSE
#define DEFAULT_backPressureNoBackoff FALSE
#define DEFAULT_noBackoff FALSE
#define DEFAULT_excessDefer TRUE
#define DEFAULT_maxRetransmission 0x0F
#define DEFAULT_collisionWindow 0x37
#define DEFAULT_maxFrameLength 0x600
#define DEFAULT_collisionWindow 0x37
#define DEFAULT_fifoTxThr 0x10
#define DEFAULT_fifoTxWatermarkH 0x7e
#define DEFAULT_fifoRxWatermarkL 0x08
#define DEFAULT_tbiPhyAddr 5
#define DEFAULT_exceptions ((uint32_t)(IMASK_BREN | \
IMASK_RXCEN | \
IMASK_BTEN | \
IMASK_TXCEN | \
IMASK_TXEEN | \
IMASK_ABRTEN | \
IMASK_LCEN | \
IMASK_CRLEN | \
IMASK_XFUNEN | \
IMASK_IFERREN | \
IMASK_MAGEN | \
IMASK_TDPEEN | \
IMASK_RDPEEN))
#define HASH_TABLE_SIZE 256 /* Hash table size (32 bits * 8 regs) */
#define EXTENDED_HASH_TABLE_SIZE 512 /* Extended Hash table size (32 bits * 16 regs) */
#define DTSEC_TO_MII_OFFSET 0x1000 /* number of pattern match registers (entries) */
#define MAX_PHYS 32 /* maximum number of phys */
#define DTSEC_ID1_ID 0xffff0000
#define DTSEC_ID1_REV_MJ 0x0000FF00
#define DTSEC_ID1_REV_MN 0x000000ff
#define ID2_INT_REDUCED_OFF 0x00010000
#define ID2_INT_NORMAL_OFF 0x00020000
#define ECNTRL_CLRCNT 0x00004000
#define ECNTRL_AUTOZ 0x00002000
#define ECNTRL_STEN 0x00001000
#define ECNTRL_CFG_RO 0x80000000
#define ECNTRL_GMIIM 0x00000040
#define ECNTRL_TBIM 0x00000020
#define ECNTRL_SGMIIM 0x00000002
#define ECNTRL_RPM 0x00000010
#define ECNTRL_R100M 0x00000008
#define ECNTRL_RMM 0x00000004
#define ECNTRL_QSGMIIM 0x00000001
#define TCTRL_THDF 0x00000800
#define TCTRL_TTSE 0x00000040
#define TCTRL_GTS 0x00000020
#define TCTRL_TFC_PAUSE 0x00000010
/* PTV offsets */
#define PTV_PTE_OFST 16
#define RCTRL_CFA 0x00008000
#define RCTRL_GHTX 0x00000400
#define RCTRL_RTSE 0x00000040
#define RCTRL_GRS 0x00000020
#define RCTRL_BC_REJ 0x00000010
#define RCTRL_MPROM 0x00000008
#define RCTRL_RSF 0x00000004
#define RCTRL_EMEN 0x00000002
#define RCTRL_UPROM 0x00000001
#define RCTRL_PROM (RCTRL_UPROM | RCTRL_MPROM)
#define TMR_CTL_ESFDP 0x00000800
#define TMR_CTL_ESFDE 0x00000400
#define TSEC_ID1_DEBUG 0x00e00c00
#define DEBUG_ENABLE 0x80000000
#define DPERROR_Tx_ERROR_ON_SEC 0x00400000
#define DPERROR_Tx_ERROR_ON_WRITE 0x10000000
#define DPERROR_Rx_ERROR_ON_SEC 0x00000040
#define DPERROR_Rx_ERROR_ON_WRITE 0x00001000
#define DPERROR_STT 0x80000000
#define DPERROR_STR 0x00008000
#define MACCFG1_SOFT_RESET 0x80000000
#define MACCFG1_LOOPBACK 0x00000100
#define MACCFG1_RX_FLOW 0x00000020
#define MACCFG1_TX_FLOW 0x00000010
#define MACCFG1_TX_EN 0x00000001
#define MACCFG1_RX_EN 0x00000004
#define MACCFG1_RESET_RxMC 0x00080000
#define MACCFG1_RESET_TxMC 0x00040000
#define MACCFG1_RESET_RxFUN 0x00020000
#define MACCFG1_RESET_TxFUN 0x00010000
#define MACCFG2_NIBBLE_MODE 0x00000100
#define MACCFG2_BYTE_MODE 0x00000200
#define MACCFG2_PRE_AM_Rx_EN 0x00000080
#define MACCFG2_PRE_AM_Tx_EN 0x00000040
#define MACCFG2_LENGTH_CHECK 0x00000010
#define MACCFG2_MAGIC_PACKET_EN 0x00000008
#define MACCFG2_PAD_CRC_EN 0x00000004
#define MACCFG2_CRC_EN 0x00000002
#define MACCFG2_FULL_DUPLEX 0x00000001
#define PREAMBLE_LENGTH_SHIFT 12
#define IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT 24
#define IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT 16
#define IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT 8
#define IPGIFG_NON_BACK_TO_BACK_IPG_1 0x7F000000
#define IPGIFG_NON_BACK_TO_BACK_IPG_2 0x007F0000
#define IPGIFG_MIN_IFG_ENFORCEMENT 0x0000FF00
#define IPGIFG_BACK_TO_BACK_IPG 0x0000007F
#define HAFDUP_ALT_BEB 0x00080000
#define HAFDUP_BP_NO_BACKOFF 0x00040000
#define HAFDUP_NO_BACKOFF 0x00020000
#define HAFDUP_EXCESS_DEFER 0x00010000
#define HAFDUP_COLLISION_WINDOW 0x000003ff
#define HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT 20
#define HAFDUP_RETRANSMISSION_MAX_SHIFT 12
#define HAFDUP_RETRANSMISSION_MAX 0x0000f000
#define NUM_OF_HASH_REGS 8 /* Number of hash table registers */
#define DEBUG_GET_FIFO_READ_INDEX 0x007f0000
#define DEBUG_GET_FIFO_WRITE_INDEX 0x0000007f
/* Pause Time Value Register */
#define PTV_PTE_SHIFT 16
#define MASK22BIT 0x003FFFFF
#define MASK16BIT 0x0000FFFF
#define MASK12BIT 0x00000FFF
#define MASK8BIT 0x000000FF
#define VAL32BIT 0x100000000LL
#define VAL22BIT 0x00400000
#define VAL16BIT 0x00010000
#define VAL12BIT 0x00001000
/* PHY Control Register */
#define PHY_CR_LOOPBACK 0x4000
#define PHY_CR_SPEED0 0x2000
#define PHY_CR_ANE 0x1000
#define PHY_CR_FULLDUPLEX 0x0100
#define PHY_CR_SPEED1 0x0040
#define PHY_TBICON_SRESET 0x8000
#define PHY_TBICON_SPEED2 0x0020
/* CAR1/2 bits */
#define CAR1_TR64 0x80000000
#define CAR1_TR127 0x40000000
@ -363,19 +166,6 @@ typedef uint32_t t_ErrorDisable;
#define CAR2_TXPF 0x00000200
#define CAR2_TDRP 0x00000001
#define CAM1_ERRORS_ONLY (CAR1_RXPF | \
CAR1_RALN | \
CAR1_RFLR | \
CAR1_RCDE | \
CAR1_RCSE | \
CAR1_RUND | \
CAR1_ROVR | \
CAR1_RFRG | \
CAR1_RJBR | \
CAR1_RDRP)
#define CAM2_ERRORS_ONLY (CAR2_TFCS | CAR2_TXPF | CAR2_TDRP)
typedef struct t_InternalStatistics
{
uint64_t tr64;
@ -408,202 +198,11 @@ typedef struct t_InternalStatistics
uint64_t tfcs;
} t_InternalStatistics;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct
{
uint32_t exact_match1; /* octets 1-4 */
uint32_t exact_match2; /* octets 5-6 */
} _PackedType macRegs;
typedef _Packed struct
{
volatile uint32_t tsec_id1; /* 0x000 ETSEC_ID register */
volatile uint32_t tsec_id2; /* 0x004 ETSEC_ID2 register */
volatile uint32_t ievent; /* 0x008 Interrupt event register */
volatile uint32_t imask; /* 0x00C Interrupt mask register */
volatile uint32_t edis; /* 0x010 Error disabled register */
volatile uint32_t ecntrl; /* 0x014 E control register */
volatile uint32_t ptv; /* 0x018 Pause time value register */
volatile uint32_t tbipa; /* 0x01C TBI PHY address register */
volatile uint32_t tmr_ctrl; /* 0x020 Time-stamp Control register */
volatile uint32_t tmr_pevent; /* 0x024 Time-stamp event register */
volatile uint32_t tmr_pemask; /* 0x028 Timer event mask register */
volatile uint32_t DTSEC_RESERVED2; /* 0x02C */
volatile uint32_t iobistctl; /* 0x030 IO BIST Control register */
volatile uint32_t DTSEC_RESERVED3[3]; /* 0x034 */
volatile uint32_t tctrl; /* 0x040 Transmit control register */
volatile uint32_t DTSEC_RESERVED4[3]; /* 0x044-0x04C */
volatile uint32_t rctrl; /* 0x050 Receive control register */
volatile uint32_t DTSEC_RESERVED5[11]; /* 0x054- 0x07C */
volatile uint32_t igaddr[8]; /* 0x080-0x09C Individual/group address registers 0-7 */
volatile uint32_t gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */
volatile uint32_t ETSEC_RESERVED6[16]; /* 0x0C0-0x0FC */
volatile uint32_t maccfg1; /* 0x100 MAC configuration #1 */
volatile uint32_t maccfg2; /* 0x104 MAC configuration #2 */
volatile uint32_t ipgifg; /* 0x108 IPG/IFG */
volatile uint32_t hafdup; /* 0x10C Half-duplex */
volatile uint32_t maxfrm; /* 0x110 Maximum frame */
volatile uint32_t DTSEC_RESERVED7[3]; /* 0x114-0x11C register */
t_MiiAccessMemMap miiMemMap;
volatile uint32_t ifctrl; /* 0x138 MII Mgmt:interface control */
volatile uint32_t ifstat; /* 0x13C Interface status */
volatile uint32_t macstnaddr1; /* 0x140 Station Address,part 1 */
volatile uint32_t macstnaddr2; /* 0x144 Station Address,part 2 */
volatile macRegs macaddr[DTSEC_NUM_OF_PADDRS]; /* 0x148-0x1BC mac exact match addresses 1-15, parts 1-2 */
volatile uint32_t DTSEC_RESERVED8[16]; /* 0x1C0-0x1FC register */
/* RMON MIB REGISTERS */
/* TRANSMIT and RECEIVE COUNTERS */
volatile uint32_t tr64; /* 0x200 transmit and receive 64 byte frame counter */
volatile uint32_t tr127; /* 0x204 transmit and receive 65 to 127 byte frame counter */
volatile uint32_t tr255; /* 0x208 transmit and receive 128 to 255 byte frame counter */
volatile uint32_t tr511; /* 0x20C transmit and receive 256 to 511 byte frame counter */
volatile uint32_t tr1k; /* 0x210 transmit and receive 512 to 1023 byte frame counter */
volatile uint32_t trmax; /* 0x214 transmit and receive 1024 to 1518 byte frame counter */
volatile uint32_t trmgv; /* 0x218 transmit and receive 1519 to 1522 byte good VLAN frame count */
/* RECEIVE COUNTERS */
volatile uint32_t rbyt; /* 0x21C receive byte counter */
volatile uint32_t rpkt; /* 0x220 receive packet counter */
volatile uint32_t rfcs; /* 0x224 receive FCS error counter */
volatile uint32_t rmca; /* 0x228 RMCA receive multicast packet counter */
volatile uint32_t rbca; /* 0x22C receive broadcast packet counter */
volatile uint32_t rxcf; /* 0x230 receive control frame packet counter */
volatile uint32_t rxpf; /* 0x234 receive PAUSE frame packet counter */
volatile uint32_t rxuo; /* 0x238 receive unknown OP code counter */
volatile uint32_t raln; /* 0x23C receive alignment error counter */
volatile uint32_t rflr; /* 0x240 receive frame length error counter */
volatile uint32_t rcde; /* 0x244 receive code error counter */
volatile uint32_t rcse; /* 0x248 receive carrier sense error counter */
volatile uint32_t rund; /* 0x24C receive undersize packet counter */
volatile uint32_t rovr; /* 0x250 receive oversize packet counter */
volatile uint32_t rfrg; /* 0x254 receive fragments counter */
volatile uint32_t rjbr; /* 0x258 receive jabber counter */
volatile uint32_t rdrp; /* 0x25C receive drop */
/* TRANSMIT COUNTERS */
volatile uint32_t tbyt; /* 0x260 transmit byte counter */
volatile uint32_t tpkt; /* 0x264 transmit packet counter */
volatile uint32_t tmca; /* 0x268 transmit multicast packet counter */
volatile uint32_t tbca; /* 0x26C transmit broadcast packet counter */
volatile uint32_t txpf; /* 0x270 transmit PAUSE control frame counter */
volatile uint32_t tdfr; /* 0x274 transmit deferral packet counter */
volatile uint32_t tedf; /* 0x278 transmit excessive deferral packet counter */
volatile uint32_t tscl; /* 0x27C transmit single collision packet counter */
volatile uint32_t tmcl; /* 0x280 transmit multiple collision packet counter */
volatile uint32_t tlcl; /* 0x284 transmit late collision packet counter */
volatile uint32_t txcl; /* 0x288 transmit excessive collision packet counter */
volatile uint32_t tncl; /* 0x28C transmit total collision counter */
volatile uint32_t DTSEC_RESERVED9; /* 0x290 */
volatile uint32_t tdrp; /* 0x294 transmit drop frame counter */
volatile uint32_t tjbr; /* 0x298 transmit jabber frame counter */
volatile uint32_t tfcs; /* 0x29C transmit FCS error counter */
volatile uint32_t txcf; /* 0x2A0 transmit control frame counter */
volatile uint32_t tovr; /* 0x2A4 transmit oversize frame counter */
volatile uint32_t tund; /* 0x2A8 transmit undersize frame counter */
volatile uint32_t tfrg; /* 0x2AC transmit fragments frame counter */
/* GENERAL REGISTERS */
volatile uint32_t car1; /* 0x2B0 carry register one register* */
volatile uint32_t car2; /* 0x2B4 carry register two register* */
volatile uint32_t cam1; /* 0x2B8 carry register one mask register */
volatile uint32_t cam2; /* 0x2BC carry register two mask register */
volatile uint32_t DTSEC_RESERVED10[16]; /* 0x2C0-0x2FC */
/* Debug and Factory Test Registers */
volatile uint32_t debug; /* 0x300 DEBUG - Debug Register */
volatile uint32_t dperror; /* 0x304 DPERROR - Parity Error Register */
volatile uint32_t hwassert; /* 0x308 HWASSERT */
volatile uint32_t RESERVED11; /* 0x30C Reserved */
volatile uint32_t rx_fifo_ptr; /* 0x310 RXFIFOPTR - Rx FIFO R/W Pointer Register */
volatile uint32_t rx_fifo_dath; /* 0x314 RXFIFODATH - Rx FIFO Data Register */
volatile uint32_t rx_fifo_datl; /* 0x318 RXFIFODATL - Rx FIFO Data Register */
volatile uint32_t rx_fifo_stat; /* 0x31C RXFIFOSTAT - Rx FIFO Status Register */
volatile uint32_t tx_fifo_ptr; /* 0x320 TXFIFOPTR - Tx FIFO R/W Pointer Register */
volatile uint32_t tx_fifo_dath; /* 0x324 TXFIFODATH - Rx FIFO Data Register */
volatile uint32_t tx_fifo_datl; /* 0x328 TXFIFODATL - Rx FIFO Data Register */
volatile uint32_t tx_fifo_stat; /* 0x32C TXFIFOSTAT - Tx FIFO Status Register */
volatile uint32_t pkt_rcv_cnt; /* 0x330 PKTRCVCNT - Number of packets accepted and written to Rx FIFO */
volatile uint32_t RESERVED12[3]; /* 0x334-0x33C Reserved */
volatile uint32_t tx_threshold; /* 0x340 Transmit threshold; Number of entries (4 bytes units) before starting to transmit to the MAC */
volatile uint32_t tx_watermark_high;/* 0x344 Transmit watermark high; Number of entries (4 byte units) before de-asserting Ready to packet Interface */
volatile uint32_t rx_watermark_low; /* 0x348 Receive watermark low; Number of entries (4 byte units) before unloading to packet Interface */
} _PackedType t_DtsecMemMap;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
typedef struct {
uint32_t errorDisabled;
bool halfDuplex;
uint16_t pauseTime;
uint16_t pauseExtended;
uint8_t tbiPhyAddr; /**< TBI Physical address (1-31) [DEFAULT_tbiPhyAddr] */
bool autoZeroCounters;
bool promiscuousEnable;
bool halfDulexFlowControlEn;
bool txTimeStampEn;
bool rxTimeStampEn;
uint8_t packetAlignmentPadding;
bool controlFrameAccept;
bool groupHashExtend;
bool broadcReject;
bool rxShortFrame;
bool exactMatch;
bool debugMode;
bool loopback;
bool actOnRxPauseFrame;
bool actOnTxPauseFrame;
uint8_t nonBackToBackIpg1;
uint8_t nonBackToBackIpg2;
uint8_t minIfgEnforcement;
uint8_t backToBackIpg;
uint8_t preambleLength;
bool preambleRxEn;
bool preambleTxEn;
bool lengthCheckEnable;
bool magicPacketEnable;
bool padAndCrcEnable;
bool crcEnable;
bool alternateBackoffEnable;
uint8_t alternateBackoffVal;
bool backPressureNoBackoff;
bool noBackoff;
bool excessDefer;
uint8_t maxRetransmission;
uint16_t collisionWindow;
uint16_t maxFrameLength;
uint8_t fifoTxThr;
uint8_t fifoTxWatermarkH;
uint8_t fifoRxWatermarkL;
} t_DtsecDriverParam;
typedef struct {
t_FmMacControllerDriver fmMacControllerDriver;
t_Handle h_App; /**< Handle to the upper layer application */
t_DtsecMemMap *p_MemMap; /**< pointer to dTSEC memory mapped registers. */
t_MiiAccessMemMap *p_MiiMemMap; /**< pointer to dTSEC MII memory mapped registers. */
struct dtsec_regs *p_MemMap; /**< pointer to dTSEC memory mapped registers. */
struct dtsec_mii_reg *p_MiiMemMap; /**< pointer to dTSEC MII memory mapped registers. */
uint64_t addr; /**< MAC address of device; */
e_EnetMode enetMode; /**< Ethernet physical interface */
t_FmMacExceptionCallback *f_Exception;
@ -612,23 +211,18 @@ typedef struct {
bool indAddrRegUsed[DTSEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
uint64_t paddr[DTSEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
bool debugMode;
bool halfDuplex;
t_InternalStatistics internalStatistics;
t_EthHash *p_MulticastAddrHash; /* pointer to driver's global address hash table */
t_EthHash *p_UnicastAddrHash; /* pointer to driver's individual address hash table */
uint8_t macId;
uint8_t tbi_phy_addr;
uint32_t exceptions;
bool ptpTsuEnabled;
bool enTsuErrExeption;
e_FmMacStatisticsLevel statisticsLevel;
t_DtsecDriverParam *p_DtsecDriverParam;
struct dtsec_cfg *p_DtsecDriverParam;
} t_Dtsec;
t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#endif /* __DTSEC_H */

67
sys/contrib/ncsw/Peripherals/FM/MAC/dtsec_mii_acc.c
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File dtsec_mii_acc.c
@ -40,6 +41,7 @@
#include "std_ext.h"
#include "fm_mac.h"
#include "dtsec.h"
#include "fsl_fman_dtsec_mii_acc.h"
/*****************************************************************************/
@ -48,33 +50,20 @@ t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec,
uint8_t reg,
uint16_t data)
{
t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
t_MiiAccessMemMap *p_MiiAccess;
uint32_t tmpReg;
t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
struct dtsec_mii_reg *miiregs;
uint16_t dtsec_freq;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Dtsec->p_MiiMemMap;
dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1);
miiregs = p_Dtsec->p_MiiMemMap;
/* Stop the MII management read cycle */
WRITE_UINT32(p_MiiAccess->miimcom, 0);
/* Dummy read to make sure MIIMCOM is written */
tmpReg = GET_UINT32(p_MiiAccess->miimcom);
err = (t_Error)fman_dtsec_mii_write_reg(miiregs, phyAddr, reg, data, dtsec_freq);
/* Setting up MII Management Address Register */
tmpReg = (uint32_t)((phyAddr << MIIMADD_PHY_ADDR_SHIFT) | reg);
WRITE_UINT32(p_MiiAccess->miimadd, tmpReg);
/* Setting up MII Management Control Register with data */
WRITE_UINT32(p_MiiAccess->miimcon, (uint32_t)data);
/* Dummy read to make sure MIIMCON is written */
tmpReg = GET_UINT32(p_MiiAccess->miimcon);
/* Wait till MII management write is complete */
while ((GET_UINT32(p_MiiAccess->miimind)) & MIIMIND_BUSY) ;
return E_OK;
return err;
}
/*****************************************************************************/
@ -83,38 +72,26 @@ t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec,
uint8_t reg,
uint16_t *p_Data)
{
t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
t_MiiAccessMemMap *p_MiiAccess;
uint32_t tmpReg;
t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
struct dtsec_mii_reg *miiregs;
uint16_t dtsec_freq;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Dtsec->p_MiiMemMap;
dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1);
miiregs = p_Dtsec->p_MiiMemMap;
/* Setting up the MII Management Address Register */
tmpReg = (uint32_t)((phyAddr << MIIMADD_PHY_ADDR_SHIFT) | reg);
WRITE_UINT32(p_MiiAccess->miimadd, tmpReg);
/* Perform an MII management read cycle */
WRITE_UINT32(p_MiiAccess->miimcom, MIIMCOM_READ_CYCLE);
/* Dummy read to make sure MIIMCOM is written */
tmpReg = GET_UINT32(p_MiiAccess->miimcom);
/* Wait till MII management read is complete */
while ((GET_UINT32(p_MiiAccess->miimind)) & MIIMIND_BUSY) ;
/* Read MII management status */
*p_Data = (uint16_t)GET_UINT32(p_MiiAccess->miimstat);
WRITE_UINT32(p_MiiAccess->miimcom, 0);
/* Dummy read to make sure MIIMCOM is written */
tmpReg = GET_UINT32(p_MiiAccess->miimcom);
err = fman_dtsec_mii_read_reg(miiregs, phyAddr, reg, p_Data, dtsec_freq);
if (*p_Data == 0xffff)
RETURN_ERROR(MINOR, E_NO_DEVICE,
("Read wrong data (0xffff): phyAddr 0x%x, reg 0x%x",
phyAddr, reg));
if (err)
RETURN_ERROR(MINOR, (t_Error)err, NO_MSG);
return E_OK;
}

44
sys/contrib/ncsw/Peripherals/FM/MAC/dtsec_mii_acc.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -36,43 +36,7 @@
#include "std_ext.h"
/* MII Management Configuration Register */
#define MIIMCFG_RESET_MGMT 0x80000000
#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
/* MII Management Command Register */
#define MIIMCOM_READ_CYCLE 0x00000001
#define MIIMCOM_SCAN_CYCLE 0x00000002
/* MII Management Address Register */
#define MIIMADD_PHY_ADDR_SHIFT 8
/* MII Management Indicator Register */
#define MIIMIND_BUSY 0x00000001
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/*----------------------------------------------------*/
/* MII Configuration Control Memory Map Registers */
/*----------------------------------------------------*/
typedef _Packed struct t_MiiAccessMemMap
{
volatile uint32_t miimcfg; /* MII Mgmt:configuration */
volatile uint32_t miimcom; /* MII Mgmt:command */
volatile uint32_t miimadd; /* MII Mgmt:address */
volatile uint32_t miimcon; /* MII Mgmt:control 3 */
volatile uint32_t miimstat; /* MII Mgmt:status */
volatile uint32_t miimind; /* MII Mgmt:indicators */
} _PackedType t_MiiAccessMemMap ;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#endif /* __DTSEC_MII_ACC_H */

188
sys/contrib/ncsw/Peripherals/FM/MAC/fm_mac.c
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_mac.c
@ -45,18 +46,34 @@
#include "fm_mac.h"
/* ........................................................................... */
/* ......................................................................... */
t_Handle FM_MAC_Config (t_FmMacParams *p_FmMacParam)
{
t_FmMacControllerDriver *p_FmMacControllerDriver;
uint16_t fmClkFreq;
SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_INVALID_HANDLE, NULL);
if(ENET_SPEED_FROM_MODE(p_FmMacParam->enetMode) < e_ENET_SPEED_10000)
fmClkFreq = FmGetClockFreq(p_FmMacParam->h_Fm);
if (fmClkFreq == 0)
{
REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Can't get clock for MAC!"));
return NULL;
}
#if (DPAA_VERSION == 10)
if (ENET_SPEED_FROM_MODE(p_FmMacParam->enetMode) < e_ENET_SPEED_10000)
p_FmMacControllerDriver = (t_FmMacControllerDriver *)DTSEC_Config(p_FmMacParam);
else
p_FmMacControllerDriver = (t_FmMacControllerDriver *)TGEC_Config(p_FmMacParam);
#if FM_MAX_NUM_OF_10G_MACS > 0
p_FmMacControllerDriver = (t_FmMacControllerDriver *)TGEC_Config(p_FmMacParam);
#else
p_FmMacControllerDriver = NULL;
#endif /* FM_MAX_NUM_OF_10G_MACS > 0 */
#else
p_FmMacControllerDriver = (t_FmMacControllerDriver *)MEMAC_Config(p_FmMacParam);
#endif /* (DPAA_VERSION == 10) */
if (!p_FmMacControllerDriver)
return NULL;
@ -66,10 +83,12 @@ t_Handle FM_MAC_Config (t_FmMacParams *p_FmMacParam)
p_FmMacControllerDriver->macId = p_FmMacParam->macId;
p_FmMacControllerDriver->resetOnInit = DEFAULT_resetOnInit;
p_FmMacControllerDriver->clkFreq = fmClkFreq;
return (t_Handle)p_FmMacControllerDriver;
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_Init (t_Handle h_FmMac)
{
@ -78,20 +97,19 @@ t_Error FM_MAC_Init (t_Handle h_FmMac)
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->resetOnInit &&
!p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit &&
(FmResetMac(p_FmMacControllerDriver->h_Fm,
((ENET_INTERFACE_FROM_MODE(p_FmMacControllerDriver->enetMode) == e_ENET_IF_XGMII) ? e_FM_MAC_10G : e_FM_MAC_1G),
p_FmMacControllerDriver->macId) != E_OK))
((ENET_INTERFACE_FROM_MODE(p_FmMacControllerDriver->enetMode) == e_ENET_IF_XGMII) ?
e_FM_MAC_10G : e_FM_MAC_1G),
p_FmMacControllerDriver->macId) != E_OK))
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't reset MAC!"));
if ((p_FmMacControllerDriver->clkFreq = FmGetClockFreq(p_FmMacControllerDriver->h_Fm)) == 0)
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't get clock for MAC!"));
if (p_FmMacControllerDriver->f_FM_MAC_Init)
return p_FmMacControllerDriver->f_FM_MAC_Init(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_Free (t_Handle h_FmMac)
{
@ -105,7 +123,7 @@ t_Error FM_MAC_Free (t_Handle h_FmMac)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ConfigResetOnInit (t_Handle h_FmMac, bool enable)
{
@ -113,12 +131,15 @@ t_Error FM_MAC_ConfigResetOnInit (t_Handle h_FmMac, bool enable)
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit)
return p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit(h_FmMac, enable);
p_FmMacControllerDriver->resetOnInit = enable;
return E_OK;
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ConfigLoopback (t_Handle h_FmMac, bool newVal)
{
@ -132,7 +153,7 @@ t_Error FM_MAC_ConfigLoopback (t_Handle h_FmMac, bool newVal)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ConfigMaxFrameLength (t_Handle h_FmMac, uint16_t newVal)
{
@ -145,7 +166,7 @@ t_Error FM_MAC_ConfigMaxFrameLength (t_Handle h_FmMac, uint16_t newVal)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ConfigWan (t_Handle h_FmMac, bool flag)
{
@ -159,7 +180,7 @@ t_Error FM_MAC_ConfigWan (t_Handle h_FmMac, bool flag)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ConfigPadAndCrc (t_Handle h_FmMac, bool newVal)
{
@ -173,7 +194,7 @@ t_Error FM_MAC_ConfigPadAndCrc (t_Handle h_FmMac, bool newVal)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ConfigHalfDuplex (t_Handle h_FmMac, bool newVal)
{
@ -187,7 +208,21 @@ t_Error FM_MAC_ConfigHalfDuplex (t_Handle h_FmMac, bool newVal)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ConfigTbiPhyAddr (t_Handle h_FmMac, uint8_t newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr)
return p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr(h_FmMac,newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ConfigLengthCheck (t_Handle h_FmMac, bool newVal)
{
@ -201,7 +236,7 @@ t_Error FM_MAC_ConfigLengthCheck (t_Handle h_FmMac, bool newVal)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ConfigException (t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
{
@ -216,7 +251,7 @@ t_Error FM_MAC_ConfigException (t_Handle h_FmMac, e_FmMacExceptions ex, bool ena
}
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac)
{
@ -236,7 +271,7 @@ t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac)
/* Run Time Control */
/*****************************************************************************/
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_Enable (t_Handle h_FmMac, e_CommMode mode)
{
@ -250,7 +285,7 @@ t_Error FM_MAC_Enable (t_Handle h_FmMac, e_CommMode mode)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_Disable (t_Handle h_FmMac, e_CommMode mode)
{
@ -264,7 +299,19 @@ t_Error FM_MAC_Disable (t_Handle h_FmMac, e_CommMode mode)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_Resume (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Resume)
return p_FmMacControllerDriver->f_FM_MAC_Resume(h_FmMac);
return E_OK;
}
/* ......................................................................... */
t_Error FM_MAC_Enable1588TimeStamp (t_Handle h_FmMac)
{
@ -278,7 +325,7 @@ t_Error FM_MAC_Enable1588TimeStamp (t_Handle h_FmMac)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_Disable1588TimeStamp (t_Handle h_FmMac)
{
@ -292,21 +339,43 @@ t_Error FM_MAC_Disable1588TimeStamp (t_Handle h_FmMac)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_SetTxAutoPauseFrames (t_Handle h_FmMac, uint16_t pauseTime)
t_Error FM_MAC_SetTxAutoPauseFrames(t_Handle h_FmMac,
uint16_t pauseTime)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames)
return p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames(h_FmMac, pauseTime);
return p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames(h_FmMac,
pauseTime);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_SetTxPauseFrames(t_Handle h_FmMac,
uint8_t priority,
uint16_t pauseTime,
uint16_t threshTime)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames)
return p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames(h_FmMac,
priority,
pauseTime,
threshTime);
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_SetRxIgnorePauseFrames (t_Handle h_FmMac, bool en)
{
@ -320,7 +389,21 @@ t_Error FM_MAC_SetRxIgnorePauseFrames (t_Handle h_FmMac, bool en)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_SetWakeOnLan (t_Handle h_FmMac, bool en)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan)
return p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan(h_FmMac, en);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ResetCounters (t_Handle h_FmMac)
{
@ -334,7 +417,7 @@ t_Error FM_MAC_ResetCounters (t_Handle h_FmMac)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
{
@ -348,7 +431,7 @@ t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_SetStatistics (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel)
{
@ -358,10 +441,11 @@ t_Error FM_MAC_SetStatistics (t_Handle h_FmMac, e_FmMacStatisticsLevel statistic
if (p_FmMacControllerDriver->f_FM_MAC_SetStatistics)
return p_FmMacControllerDriver->f_FM_MAC_SetStatistics(h_FmMac, statisticsLevel);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_GetStatistics (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics)
{
@ -375,7 +459,7 @@ t_Error FM_MAC_GetStatistics (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_ModifyMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
@ -389,7 +473,7 @@ t_Error FM_MAC_ModifyMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_AddHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
@ -403,7 +487,7 @@ t_Error FM_MAC_AddHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_RemoveHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
@ -417,7 +501,7 @@ t_Error FM_MAC_RemoveHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_AddExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
@ -431,7 +515,7 @@ t_Error FM_MAC_AddExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_RemovelExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
@ -445,7 +529,7 @@ t_Error FM_MAC_RemovelExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAdd
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_GetVesrion (t_Handle h_FmMac, uint32_t *macVresion)
{
@ -460,7 +544,7 @@ t_Error FM_MAC_GetVesrion (t_Handle h_FmMac, uint32_t *macVresion)
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_GetId (t_Handle h_FmMac, uint32_t *macId)
{
@ -474,7 +558,7 @@ t_Error FM_MAC_GetId (t_Handle h_FmMac, uint32_t *macId)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_SetPromiscuous (t_Handle h_FmMac, bool newVal)
{
@ -488,7 +572,7 @@ t_Error FM_MAC_SetPromiscuous (t_Handle h_FmMac, bool newVal)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex)
{
@ -502,7 +586,21 @@ t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_RestartAutoneg(t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg)
return p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_MII_WritePhyReg (t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data)
{
@ -516,7 +614,7 @@ t_Error FM_MAC_MII_WritePhyReg (t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg,
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
t_Error FM_MAC_MII_ReadPhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data)
{
@ -530,7 +628,7 @@ t_Error FM_MAC_MII_ReadPhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, u
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
/* ......................................................................... */
uint16_t FM_MAC_GetMaxFrameLength(t_Handle h_FmMac)
{

78
sys/contrib/ncsw/Peripherals/FM/MAC/fm_mac.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_mac.h
@ -42,11 +43,18 @@
#include "error_ext.h"
#include "list_ext.h"
#include "fm_mac_ext.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_MAC
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
#define DEFAULT_halfDuplex FALSE
#define DEFAULT_padAndCrcEnable TRUE
#define DEFAULT_resetOnInit FALSE
@ -54,7 +62,7 @@ typedef struct {
uint64_t addr; /* Ethernet Address */
t_List node;
} t_EthHashEntry;
#define ETH_HASH_ENTRY_OBJ(ptr) LIST_OBJECT(ptr, t_EthHashEntry, node)
#define ETH_HASH_ENTRY_OBJ(ptr) NCSW_LIST_OBJECT(ptr, t_EthHashEntry, node)
typedef struct {
uint16_t size;
@ -72,7 +80,9 @@ typedef struct {
t_Error (*f_FM_MAC_ConfigPadAndCrc) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigHalfDuplex) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigLengthCheck) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigTbiPhyAddr) (t_Handle h_FmMac, uint8_t newVal);
t_Error (*f_FM_MAC_ConfigException) (t_Handle h_FmMac, e_FmMacExceptions, bool enable);
t_Error (*f_FM_MAC_ConfigResetOnInit) (t_Handle h_FmMac, bool enable);
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
t_Error (*f_FM_MAC_ConfigSkipFman11Workaround) (t_Handle h_FmMac);
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
@ -81,11 +91,17 @@ typedef struct {
t_Error (*f_FM_MAC_Enable) (t_Handle h_FmMac, e_CommMode mode);
t_Error (*f_FM_MAC_Disable) (t_Handle h_FmMac, e_CommMode mode);
t_Error (*f_FM_MAC_Resume) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Enable1588TimeStamp) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Disable1588TimeStamp) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Reset) (t_Handle h_FmMac, bool wait);
t_Error (*f_FM_MAC_SetTxAutoPauseFrames) (t_Handle h_FmMac, uint16_t pauseTime);
t_Error (*f_FM_MAC_SetTxAutoPauseFrames) (t_Handle h_FmMac,
uint16_t pauseTime);
t_Error (*f_FM_MAC_SetTxPauseFrames) (t_Handle h_FmMac,
uint8_t priority,
uint16_t pauseTime,
uint16_t threshTime);
t_Error (*f_FM_MAC_SetRxIgnorePauseFrames) (t_Handle h_FmMac, bool en);
t_Error (*f_FM_MAC_ResetCounters) (t_Handle h_FmMac);
@ -99,6 +115,9 @@ typedef struct {
t_Error (*f_FM_MAC_SetPromiscuous) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_AdjustLink) (t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex);
t_Error (*f_FM_MAC_RestartAutoneg) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_SetWakeOnLan) (t_Handle h_FmMac, bool en);
t_Error (*f_FM_MAC_GetId) (t_Handle h_FmMac, uint32_t *macId);
@ -113,16 +132,21 @@ typedef struct {
t_Error (*f_FM_MAC_DumpRegs) (t_Handle h_FmMac);
#endif /* (defined(DEBUG_ERRORS) && ... */
t_Handle h_Fm;
e_EnetMode enetMode;
uint8_t macId;
bool resetOnInit;
uint16_t clkFreq;
t_Handle h_Fm;
t_FmRevisionInfo fmRevInfo;
e_EnetMode enetMode;
uint8_t macId;
bool resetOnInit;
uint16_t clkFreq;
} t_FmMacControllerDriver;
#if (DPAA_VERSION == 10)
t_Handle DTSEC_Config(t_FmMacParams *p_FmMacParam);
t_Handle TGEC_Config(t_FmMacParams *p_FmMacParams);
#else
t_Handle MEMAC_Config(t_FmMacParams *p_FmMacParam);
#endif /* (DPAA_VERSION == 10) */
uint16_t FM_MAC_GetMaxFrameLength(t_Handle FmMac);
@ -131,10 +155,10 @@ uint16_t FM_MAC_GetMaxFrameLength(t_Handle FmMac);
static __inline__ t_EthHashEntry *DequeueAddrFromHashEntry(t_List *p_AddrLst)
{
t_EthHashEntry *p_HashEntry = NULL;
if (!LIST_IsEmpty(p_AddrLst))
if (!NCSW_LIST_IsEmpty(p_AddrLst))
{
p_HashEntry = ETH_HASH_ENTRY_OBJ(p_AddrLst->p_Next);
LIST_DelAndInit(&p_HashEntry->node);
NCSW_LIST_DelAndInit(&p_HashEntry->node);
}
return p_HashEntry;
}
@ -146,21 +170,25 @@ static __inline__ void FreeHashTable(t_EthHash *p_Hash)
t_EthHashEntry *p_HashEntry;
int i = 0;
if (!p_Hash || !p_Hash->p_Lsts)
return;
for(i=0; i<p_Hash->size; i++)
if (p_Hash)
{
p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
while (p_HashEntry)
if (p_Hash->p_Lsts)
{
XX_Free(p_HashEntry);
p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
}
}
for (i=0; i<p_Hash->size; i++)
{
p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
while (p_HashEntry)
{
XX_Free(p_HashEntry);
p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
}
}
XX_Free(p_Hash->p_Lsts);
XX_Free(p_Hash);
XX_Free(p_Hash->p_Lsts);
}
XX_Free(p_Hash);
}
}
/* ........................................................................... */
@ -171,7 +199,7 @@ static __inline__ t_EthHash * AllocHashTable(uint16_t size)
t_EthHash *p_Hash;
/* Allocate address hash table */
p_Hash = (t_EthHash *)XX_Malloc(size*sizeof(t_EthHash *));
p_Hash = (t_EthHash *)XX_Malloc(sizeof(t_EthHash));
if (!p_Hash)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Address hash table"));
@ -187,7 +215,7 @@ static __inline__ t_EthHash * AllocHashTable(uint16_t size)
return NULL;
}
for(i=0 ; i<p_Hash->size; i++)
for (i=0 ; i<p_Hash->size; i++)
INIT_LIST(&p_Hash->p_Lsts[i]);
return p_Hash;

119
sys/contrib/ncsw/Peripherals/FM/MAC/fman_crc32.c Normal file
View File

@ -0,0 +1,119 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fman_crc32.h"
#include "common/general.h"
/* precomputed CRC values for address hashing */
static const uint32_t crc_tbl[256] = {
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
};
/* Get the mirrored value of a byte size number. (0x11010011 --> 0x11001011) */
static inline uint8_t get_mirror8(uint8_t n)
{
uint8_t mirror[16] = {
0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e,
0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
};
return (uint8_t)(((mirror[n & 0x0f] << 4) | (mirror[n >> 4])));
}
static inline uint32_t get_mirror32(uint32_t n)
{
return ((uint32_t)get_mirror8((uint8_t)(n))<<24) |
((uint32_t)get_mirror8((uint8_t)(n>>8))<<16) |
((uint32_t)get_mirror8((uint8_t)(n>>16))<<8) |
((uint32_t)get_mirror8((uint8_t)(n>>24)));
}
uint32_t get_mac_addr_crc(uint64_t _addr)
{
uint32_t i;
uint8_t data;
uint32_t crc;
/* CRC calculation */
crc = 0xffffffff;
for (i = 0; i < 6; i++) {
data = (uint8_t)(_addr >> ((5-i)*8));
crc = crc ^ data;
crc = crc_tbl[crc&0xff] ^ (crc>>8);
}
crc = get_mirror32(crc);
return crc;
}

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FMAN_CRC32_H
#define __FMAN_CRC32_H
#include "common/general.h"
uint32_t get_mac_addr_crc(uint64_t _addr);
#endif /* __FMAN_CRC32_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_dtsec.h"
void fman_dtsec_stop_rx(struct dtsec_regs *regs)
{
/* Assert the graceful stop bit */
iowrite32be(ioread32be(&regs->rctrl) | RCTRL_GRS, &regs->rctrl);
}
void fman_dtsec_stop_tx(struct dtsec_regs *regs)
{
/* Assert the graceful stop bit */
iowrite32be(ioread32be(&regs->tctrl) | DTSEC_TCTRL_GTS, &regs->tctrl);
}
void fman_dtsec_start_tx(struct dtsec_regs *regs)
{
/* clear the graceful stop bit */
iowrite32be(ioread32be(&regs->tctrl) & ~DTSEC_TCTRL_GTS, &regs->tctrl);
}
void fman_dtsec_start_rx(struct dtsec_regs *regs)
{
/* clear the graceful stop bit */
iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_GRS, &regs->rctrl);
}
void fman_dtsec_defconfig(struct dtsec_cfg *cfg)
{
cfg->halfdup_on = DEFAULT_HALFDUP_ON;
cfg->halfdup_retransmit = DEFAULT_HALFDUP_RETRANSMIT;
cfg->halfdup_coll_window = DEFAULT_HALFDUP_COLL_WINDOW;
cfg->halfdup_excess_defer = DEFAULT_HALFDUP_EXCESS_DEFER;
cfg->halfdup_no_backoff = DEFAULT_HALFDUP_NO_BACKOFF;
cfg->halfdup_bp_no_backoff = DEFAULT_HALFDUP_BP_NO_BACKOFF;
cfg->halfdup_alt_backoff_val = DEFAULT_HALFDUP_ALT_BACKOFF_VAL;
cfg->halfdup_alt_backoff_en = DEFAULT_HALFDUP_ALT_BACKOFF_EN;
cfg->rx_drop_bcast = DEFAULT_RX_DROP_BCAST;
cfg->rx_short_frm = DEFAULT_RX_SHORT_FRM;
cfg->rx_len_check = DEFAULT_RX_LEN_CHECK;
cfg->tx_pad_crc = DEFAULT_TX_PAD_CRC;
cfg->tx_crc = DEFAULT_TX_CRC;
cfg->rx_ctrl_acc = DEFAULT_RX_CTRL_ACC;
cfg->tx_pause_time = DEFAULT_TX_PAUSE_TIME;
cfg->tbipa = DEFAULT_TBIPA; /* PHY address 0 is reserved (DPAA RM)*/
cfg->rx_prepend = DEFAULT_RX_PREPEND;
cfg->ptp_tsu_en = DEFAULT_PTP_TSU_EN;
cfg->ptp_exception_en = DEFAULT_PTP_EXCEPTION_EN;
cfg->preamble_len = DEFAULT_PREAMBLE_LEN;
cfg->rx_preamble = DEFAULT_RX_PREAMBLE;
cfg->tx_preamble = DEFAULT_TX_PREAMBLE;
cfg->loopback = DEFAULT_LOOPBACK;
cfg->rx_time_stamp_en = DEFAULT_RX_TIME_STAMP_EN;
cfg->tx_time_stamp_en = DEFAULT_TX_TIME_STAMP_EN;
cfg->rx_flow = DEFAULT_RX_FLOW;
cfg->tx_flow = DEFAULT_TX_FLOW;
cfg->rx_group_hash_exd = DEFAULT_RX_GROUP_HASH_EXD;
cfg->tx_pause_time_extd = DEFAULT_TX_PAUSE_TIME_EXTD;
cfg->rx_promisc = DEFAULT_RX_PROMISC;
cfg->non_back_to_back_ipg1 = DEFAULT_NON_BACK_TO_BACK_IPG1;
cfg->non_back_to_back_ipg2 = DEFAULT_NON_BACK_TO_BACK_IPG2;
cfg->min_ifg_enforcement = DEFAULT_MIN_IFG_ENFORCEMENT;
cfg->back_to_back_ipg = DEFAULT_BACK_TO_BACK_IPG;
cfg->maximum_frame = DEFAULT_MAXIMUM_FRAME;
cfg->tbi_phy_addr = DEFAULT_TBI_PHY_ADDR;
cfg->wake_on_lan = DEFAULT_WAKE_ON_LAN;
}
int fman_dtsec_init(struct dtsec_regs *regs, struct dtsec_cfg *cfg,
enum enet_interface iface_mode,
enum enet_speed iface_speed,
uint8_t *macaddr,
uint8_t fm_rev_maj,
uint8_t fm_rev_min,
uint32_t exception_mask)
{
bool is_rgmii = FALSE;
bool is_sgmii = FALSE;
bool is_qsgmii = FALSE;
int i;
uint32_t tmp;
UNUSED(fm_rev_maj);UNUSED(fm_rev_min);
/* let's start with a soft reset */
iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);
iowrite32be(0, &regs->maccfg1);
/*************dtsec_id2******************/
tmp = ioread32be(&regs->tsec_id2);
/* check RGMII support */
if (iface_mode == E_ENET_IF_RGMII ||
iface_mode == E_ENET_IF_RMII)
if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
return -EINVAL;
if (iface_mode == E_ENET_IF_SGMII ||
iface_mode == E_ENET_IF_MII)
if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
return -EINVAL;
/***************ECNTRL************************/
is_rgmii = (bool)((iface_mode == E_ENET_IF_RGMII) ? TRUE : FALSE);
is_sgmii = (bool)((iface_mode == E_ENET_IF_SGMII) ? TRUE : FALSE);
is_qsgmii = (bool)((iface_mode == E_ENET_IF_QSGMII) ? TRUE : FALSE);
tmp = 0;
if (is_rgmii || iface_mode == E_ENET_IF_GMII)
tmp |= DTSEC_ECNTRL_GMIIM;
if (is_sgmii)
tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
if (is_qsgmii)
tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
DTSEC_ECNTRL_QSGMIIM);
if (is_rgmii)
tmp |= DTSEC_ECNTRL_RPM;
if (iface_speed == E_ENET_SPEED_100)
tmp |= DTSEC_ECNTRL_R100M;
iowrite32be(tmp, &regs->ecntrl);
/***************ECNTRL************************/
/***************TCTRL************************/
tmp = 0;
if (cfg->halfdup_on)
tmp |= DTSEC_TCTRL_THDF;
if (cfg->tx_time_stamp_en)
tmp |= DTSEC_TCTRL_TTSE;
iowrite32be(tmp, &regs->tctrl);
/***************TCTRL************************/
/***************PTV************************/
tmp = 0;
#ifdef FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1
if ((fm_rev_maj == 1) && (fm_rev_min == 0))
cfg->tx_pause_time += 2;
#endif /* FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1 */
if (cfg->tx_pause_time)
tmp |= cfg->tx_pause_time;
if (cfg->tx_pause_time_extd)
tmp |= cfg->tx_pause_time_extd << PTV_PTE_OFST;
iowrite32be(tmp, &regs->ptv);
/***************RCTRL************************/
tmp = 0;
tmp |= ((uint32_t)(cfg->rx_prepend & 0x0000001f)) << 16;
if (cfg->rx_ctrl_acc)
tmp |= RCTRL_CFA;
if (cfg->rx_group_hash_exd)
tmp |= RCTRL_GHTX;
if (cfg->rx_time_stamp_en)
tmp |= RCTRL_RTSE;
if (cfg->rx_drop_bcast)
tmp |= RCTRL_BC_REJ;
if (cfg->rx_short_frm)
tmp |= RCTRL_RSF;
if (cfg->rx_promisc)
tmp |= RCTRL_PROM;
iowrite32be(tmp, &regs->rctrl);
/***************RCTRL************************/
/*
* Assign a Phy Address to the TBI (TBIPA).
* Done also in cases where TBI is not selected to avoid conflict with
* the external PHY's Physical address
*/
iowrite32be(cfg->tbipa, &regs->tbipa);
/***************TMR_CTL************************/
iowrite32be(0, &regs->tmr_ctrl);
if (cfg->ptp_tsu_en) {
tmp = 0;
tmp |= TMR_PEVENT_TSRE;
iowrite32be(tmp, &regs->tmr_pevent);
if (cfg->ptp_exception_en) {
tmp = 0;
tmp |= TMR_PEMASK_TSREEN;
iowrite32be(tmp, &regs->tmr_pemask);
}
}
/***************MACCFG1***********************/
tmp = 0;
if (cfg->loopback)
tmp |= MACCFG1_LOOPBACK;
if (cfg->rx_flow)
tmp |= MACCFG1_RX_FLOW;
if (cfg->tx_flow)
tmp |= MACCFG1_TX_FLOW;
iowrite32be(tmp, &regs->maccfg1);
/***************MACCFG1***********************/
/***************MACCFG2***********************/
tmp = 0;
if (iface_speed < E_ENET_SPEED_1000)
tmp |= MACCFG2_NIBBLE_MODE;
else if (iface_speed == E_ENET_SPEED_1000)
tmp |= MACCFG2_BYTE_MODE;
tmp |= ((uint32_t) cfg->preamble_len & 0x0000000f)
<< PREAMBLE_LENGTH_SHIFT;
if (cfg->rx_preamble)
tmp |= MACCFG2_PRE_AM_Rx_EN;
if (cfg->tx_preamble)
tmp |= MACCFG2_PRE_AM_Tx_EN;
if (cfg->rx_len_check)
tmp |= MACCFG2_LENGTH_CHECK;
if (cfg->tx_pad_crc)
tmp |= MACCFG2_PAD_CRC_EN;
if (cfg->tx_crc)
tmp |= MACCFG2_CRC_EN;
if (!cfg->halfdup_on)
tmp |= MACCFG2_FULL_DUPLEX;
iowrite32be(tmp, &regs->maccfg2);
/***************MACCFG2***********************/
/***************IPGIFG************************/
tmp = (((cfg->non_back_to_back_ipg1 <<
IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT)
& IPGIFG_NON_BACK_TO_BACK_IPG_1)
| ((cfg->non_back_to_back_ipg2 <<
IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT)
& IPGIFG_NON_BACK_TO_BACK_IPG_2)
| ((cfg->min_ifg_enforcement <<
IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT)
& IPGIFG_MIN_IFG_ENFORCEMENT)
| (cfg->back_to_back_ipg & IPGIFG_BACK_TO_BACK_IPG));
iowrite32be(tmp, &regs->ipgifg);
/***************IPGIFG************************/
/***************HAFDUP************************/
tmp = 0;
if (cfg->halfdup_alt_backoff_en)
tmp = (uint32_t)(HAFDUP_ALT_BEB |
((cfg->halfdup_alt_backoff_val & 0x0000000f)
<< HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT));
if (cfg->halfdup_bp_no_backoff)
tmp |= HAFDUP_BP_NO_BACKOFF;
if (cfg->halfdup_no_backoff)
tmp |= HAFDUP_NO_BACKOFF;
if (cfg->halfdup_excess_defer)
tmp |= HAFDUP_EXCESS_DEFER;
tmp |= ((cfg->halfdup_retransmit << HAFDUP_RETRANSMISSION_MAX_SHIFT)
& HAFDUP_RETRANSMISSION_MAX);
tmp |= (cfg->halfdup_coll_window & HAFDUP_COLLISION_WINDOW);
iowrite32be(tmp, &regs->hafdup);
/***************HAFDUP************************/
/***************MAXFRM************************/
/* Initialize MAXFRM */
iowrite32be(cfg->maximum_frame, &regs->maxfrm);
/***************MAXFRM************************/
/***************CAM1************************/
iowrite32be(0xffffffff, &regs->cam1);
iowrite32be(0xffffffff, &regs->cam2);
/***************IMASK************************/
iowrite32be(exception_mask, &regs->imask);
/***************IMASK************************/
/***************IEVENT************************/
iowrite32be(0xffffffff, &regs->ievent);
/***************MACSTNADDR1/2*****************/
tmp = (uint32_t)((macaddr[5] << 24) |
(macaddr[4] << 16) |
(macaddr[3] << 8) |
macaddr[2]);
iowrite32be(tmp, &regs->macstnaddr1);
tmp = (uint32_t)((macaddr[1] << 24) |
(macaddr[0] << 16));
iowrite32be(tmp, &regs->macstnaddr2);
/***************MACSTNADDR1/2*****************/
/*****************HASH************************/
for (i = 0; i < NUM_OF_HASH_REGS ; i++) {
/* Initialize IADDRx */
iowrite32be(0, &regs->igaddr[i]);
/* Initialize GADDRx */
iowrite32be(0, &regs->gaddr[i]);
}
fman_dtsec_reset_stat(regs);
return 0;
}
uint16_t fman_dtsec_get_max_frame_len(struct dtsec_regs *regs)
{
return (uint16_t)ioread32be(&regs->maxfrm);
}
void fman_dtsec_set_max_frame_len(struct dtsec_regs *regs, uint16_t length)
{
iowrite32be(length, &regs->maxfrm);
}
void fman_dtsec_set_mac_address(struct dtsec_regs *regs, uint8_t *adr)
{
uint32_t tmp;
tmp = (uint32_t)((adr[5] << 24) |
(adr[4] << 16) |
(adr[3] << 8) |
adr[2]);
iowrite32be(tmp, &regs->macstnaddr1);
tmp = (uint32_t)((adr[1] << 24) |
(adr[0] << 16));
iowrite32be(tmp, &regs->macstnaddr2);
}
void fman_dtsec_get_mac_address(struct dtsec_regs *regs, uint8_t *macaddr)
{
uint32_t tmp1, tmp2;
tmp1 = ioread32be(&regs->macstnaddr1);
tmp2 = ioread32be(&regs->macstnaddr2);
macaddr[0] = (uint8_t)((tmp2 & 0x00ff0000) >> 16);
macaddr[1] = (uint8_t)((tmp2 & 0xff000000) >> 24);
macaddr[2] = (uint8_t)(tmp1 & 0x000000ff);
macaddr[3] = (uint8_t)((tmp1 & 0x0000ff00) >> 8);
macaddr[4] = (uint8_t)((tmp1 & 0x00ff0000) >> 16);
macaddr[5] = (uint8_t)((tmp1 & 0xff000000) >> 24);
}
void fman_dtsec_set_hash_table(struct dtsec_regs *regs, uint32_t crc, bool mcast, bool ghtx)
{
int32_t bucket;
if (ghtx)
bucket = (int32_t)((crc >> 23) & 0x1ff);
else {
bucket = (int32_t)((crc >> 24) & 0xff);
/* if !ghtx and mcast the bit must be set in gaddr instead of igaddr. */
if (mcast)
bucket += 0x100;
}
fman_dtsec_set_bucket(regs, bucket, TRUE);
}
void fman_dtsec_set_bucket(struct dtsec_regs *regs, int bucket, bool enable)
{
int reg_idx = (bucket >> 5) & 0xf;
int bit_idx = bucket & 0x1f;
uint32_t bit_mask = 0x80000000 >> bit_idx;
uint32_t *reg;
if (reg_idx > 7)
reg = &regs->gaddr[reg_idx-8];
else
reg = &regs->igaddr[reg_idx];
if (enable)
iowrite32be(ioread32be(reg) | bit_mask, reg);
else
iowrite32be(ioread32be(reg) & (~bit_mask), reg);
}
void fman_dtsec_reset_filter_table(struct dtsec_regs *regs, bool mcast, bool ucast)
{
int i;
bool ghtx;
ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? TRUE : FALSE);
if (ucast || (ghtx && mcast)) {
for (i = 0; i < NUM_OF_HASH_REGS; i++)
iowrite32be(0, &regs->igaddr[i]);
}
if (mcast) {
for (i = 0; i < NUM_OF_HASH_REGS; i++)
iowrite32be(0, &regs->gaddr[i]);
}
}
int fman_dtsec_set_tbi_phy_addr(struct dtsec_regs *regs,
uint8_t addr)
{
if (addr > 0 && addr < 32)
iowrite32be(addr, &regs->tbipa);
else
return -EINVAL;
return 0;
}
void fman_dtsec_set_wol(struct dtsec_regs *regs, bool en)
{
uint32_t tmp;
tmp = ioread32be(&regs->maccfg2);
if (en)
tmp |= MACCFG2_MAGIC_PACKET_EN;
else
tmp &= ~MACCFG2_MAGIC_PACKET_EN;
iowrite32be(tmp, &regs->maccfg2);
}
int fman_dtsec_adjust_link(struct dtsec_regs *regs,
enum enet_interface iface_mode,
enum enet_speed speed, bool full_dx)
{
uint32_t tmp;
UNUSED(iface_mode);
if ((speed == E_ENET_SPEED_1000) && !full_dx)
return -EINVAL;
tmp = ioread32be(&regs->maccfg2);
if (!full_dx)
tmp &= ~MACCFG2_FULL_DUPLEX;
else
tmp |= MACCFG2_FULL_DUPLEX;
tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
if (speed < E_ENET_SPEED_1000)
tmp |= MACCFG2_NIBBLE_MODE;
else if (speed == E_ENET_SPEED_1000)
tmp |= MACCFG2_BYTE_MODE;
iowrite32be(tmp, &regs->maccfg2);
tmp = ioread32be(&regs->ecntrl);
if (speed == E_ENET_SPEED_100)
tmp |= DTSEC_ECNTRL_R100M;
else
tmp &= ~DTSEC_ECNTRL_R100M;
iowrite32be(tmp, &regs->ecntrl);
return 0;
}
void fman_dtsec_set_uc_promisc(struct dtsec_regs *regs, bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->rctrl);
if (enable)
tmp |= RCTRL_UPROM;
else
tmp &= ~RCTRL_UPROM;
iowrite32be(tmp, &regs->rctrl);
}
void fman_dtsec_set_mc_promisc(struct dtsec_regs *regs, bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->rctrl);
if (enable)
tmp |= RCTRL_MPROM;
else
tmp &= ~RCTRL_MPROM;
iowrite32be(tmp, &regs->rctrl);
}
bool fman_dtsec_get_clear_carry_regs(struct dtsec_regs *regs,
uint32_t *car1, uint32_t *car2)
{
/* read carry registers */
*car1 = ioread32be(&regs->car1);
*car2 = ioread32be(&regs->car2);
/* clear carry registers */
if (*car1)
iowrite32be(*car1, &regs->car1);
if (*car2)
iowrite32be(*car2, &regs->car2);
return (bool)((*car1 | *car2) ? TRUE : FALSE);
}
void fman_dtsec_reset_stat(struct dtsec_regs *regs)
{
/* clear HW counters */
iowrite32be(ioread32be(&regs->ecntrl) |
DTSEC_ECNTRL_CLRCNT, &regs->ecntrl);
}
int fman_dtsec_set_stat_level(struct dtsec_regs *regs, enum dtsec_stat_level level)
{
switch (level) {
case E_MAC_STAT_NONE:
iowrite32be(0xffffffff, &regs->cam1);
iowrite32be(0xffffffff, &regs->cam2);
iowrite32be(ioread32be(&regs->ecntrl) & ~DTSEC_ECNTRL_STEN,
&regs->ecntrl);
iowrite32be(ioread32be(&regs->imask) & ~DTSEC_IMASK_MSROEN,
&regs->imask);
break;
case E_MAC_STAT_PARTIAL:
iowrite32be(CAM1_ERRORS_ONLY, &regs->cam1);
iowrite32be(CAM2_ERRORS_ONLY, &regs->cam2);
iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,
&regs->ecntrl);
iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,
&regs->imask);
break;
case E_MAC_STAT_MIB_GRP1:
iowrite32be((uint32_t)~CAM1_MIB_GRP_1, &regs->cam1);
iowrite32be((uint32_t)~CAM2_MIB_GRP_1, &regs->cam2);
iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,
&regs->ecntrl);
iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,
&regs->imask);
break;
case E_MAC_STAT_FULL:
iowrite32be(0, &regs->cam1);
iowrite32be(0, &regs->cam2);
iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,
&regs->ecntrl);
iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,
&regs->imask);
break;
default:
return -EINVAL;
}
return 0;
}
void fman_dtsec_set_ts(struct dtsec_regs *regs, bool en)
{
if (en) {
iowrite32be(ioread32be(&regs->rctrl) | RCTRL_RTSE,
&regs->rctrl);
iowrite32be(ioread32be(&regs->tctrl) | DTSEC_TCTRL_TTSE,
&regs->tctrl);
} else {
iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_RTSE,
&regs->rctrl);
iowrite32be(ioread32be(&regs->tctrl) & ~DTSEC_TCTRL_TTSE,
&regs->tctrl);
}
}
void fman_dtsec_enable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->maccfg1);
if (apply_rx)
tmp |= MACCFG1_RX_EN ;
if (apply_tx)
tmp |= MACCFG1_TX_EN ;
iowrite32be(tmp, &regs->maccfg1);
}
void fman_dtsec_clear_addr_in_paddr(struct dtsec_regs *regs, uint8_t paddr_num)
{
iowrite32be(0, &regs->macaddr[paddr_num].exact_match1);
iowrite32be(0, &regs->macaddr[paddr_num].exact_match2);
}
void fman_dtsec_add_addr_in_paddr(struct dtsec_regs *regs,
uint64_t addr,
uint8_t paddr_num)
{
uint32_t tmp;
tmp = (uint32_t)(addr);
/* swap */
tmp = (((tmp & 0x000000FF) << 24) |
((tmp & 0x0000FF00) << 8) |
((tmp & 0x00FF0000) >> 8) |
((tmp & 0xFF000000) >> 24));
iowrite32be(tmp, &regs->macaddr[paddr_num].exact_match1);
tmp = (uint32_t)(addr>>32);
/* swap */
tmp = (((tmp & 0x000000FF) << 24) |
((tmp & 0x0000FF00) << 8) |
((tmp & 0x00FF0000) >> 8) |
((tmp & 0xFF000000) >> 24));
iowrite32be(tmp, &regs->macaddr[paddr_num].exact_match2);
}
void fman_dtsec_disable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->maccfg1);
if (apply_rx)
tmp &= ~MACCFG1_RX_EN;
if (apply_tx)
tmp &= ~MACCFG1_TX_EN;
iowrite32be(tmp, &regs->maccfg1);
}
void fman_dtsec_set_tx_pause_frames(struct dtsec_regs *regs, uint16_t time)
{
uint32_t ptv = 0;
/* fixme: don't enable tx pause for half-duplex */
if (time) {
ptv = ioread32be(&regs->ptv);
ptv &= 0xffff0000;
ptv |= time & 0x0000ffff;
iowrite32be(ptv, &regs->ptv);
/* trigger the transmission of a flow-control pause frame */
iowrite32be(ioread32be(&regs->maccfg1) | MACCFG1_TX_FLOW,
&regs->maccfg1);
} else
iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
&regs->maccfg1);
}
void fman_dtsec_handle_rx_pause(struct dtsec_regs *regs, bool en)
{
uint32_t tmp;
/* todo: check if mac is set to full-duplex */
tmp = ioread32be(&regs->maccfg1);
if (en)
tmp |= MACCFG1_RX_FLOW;
else
tmp &= ~MACCFG1_RX_FLOW;
iowrite32be(tmp, &regs->maccfg1);
}
uint32_t fman_dtsec_get_rctrl(struct dtsec_regs *regs)
{
return ioread32be(&regs->rctrl);
}
uint32_t fman_dtsec_get_revision(struct dtsec_regs *regs)
{
return ioread32be(&regs->tsec_id);
}
uint32_t fman_dtsec_get_event(struct dtsec_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->ievent) & ev_mask;
}
void fman_dtsec_ack_event(struct dtsec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ev_mask, &regs->ievent);
}
uint32_t fman_dtsec_get_interrupt_mask(struct dtsec_regs *regs)
{
return ioread32be(&regs->imask);
}
uint32_t fman_dtsec_check_and_clear_tmr_event(struct dtsec_regs *regs)
{
uint32_t event;
event = ioread32be(&regs->tmr_pevent);
event &= ioread32be(&regs->tmr_pemask);
if (event)
iowrite32be(event, &regs->tmr_pevent);
return event;
}
void fman_dtsec_enable_tmr_interrupt(struct dtsec_regs *regs)
{
iowrite32be(ioread32be(&regs->tmr_pemask) | TMR_PEMASK_TSREEN,
&regs->tmr_pemask);
}
void fman_dtsec_disable_tmr_interrupt(struct dtsec_regs *regs)
{
iowrite32be(ioread32be(&regs->tmr_pemask) & ~TMR_PEMASK_TSREEN,
&regs->tmr_pemask);
}
void fman_dtsec_enable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ioread32be(&regs->imask) | ev_mask, &regs->imask);
}
void fman_dtsec_disable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ioread32be(&regs->imask) & ~ev_mask, &regs->imask);
}
uint32_t fman_dtsec_get_stat_counter(struct dtsec_regs *regs,
enum dtsec_stat_counters reg_name)
{
uint32_t ret_val;
switch (reg_name) {
case E_DTSEC_STAT_TR64:
ret_val = ioread32be(&regs->tr64);
break;
case E_DTSEC_STAT_TR127:
ret_val = ioread32be(&regs->tr127);
break;
case E_DTSEC_STAT_TR255:
ret_val = ioread32be(&regs->tr255);
break;
case E_DTSEC_STAT_TR511:
ret_val = ioread32be(&regs->tr511);
break;
case E_DTSEC_STAT_TR1K:
ret_val = ioread32be(&regs->tr1k);
break;
case E_DTSEC_STAT_TRMAX:
ret_val = ioread32be(&regs->trmax);
break;
case E_DTSEC_STAT_TRMGV:
ret_val = ioread32be(&regs->trmgv);
break;
case E_DTSEC_STAT_RBYT:
ret_val = ioread32be(&regs->rbyt);
break;
case E_DTSEC_STAT_RPKT:
ret_val = ioread32be(&regs->rpkt);
break;
case E_DTSEC_STAT_RMCA:
ret_val = ioread32be(&regs->rmca);
break;
case E_DTSEC_STAT_RBCA:
ret_val = ioread32be(&regs->rbca);
break;
case E_DTSEC_STAT_RXPF:
ret_val = ioread32be(&regs->rxpf);
break;
case E_DTSEC_STAT_RALN:
ret_val = ioread32be(&regs->raln);
break;
case E_DTSEC_STAT_RFLR:
ret_val = ioread32be(&regs->rflr);
break;
case E_DTSEC_STAT_RCDE:
ret_val = ioread32be(&regs->rcde);
break;
case E_DTSEC_STAT_RCSE:
ret_val = ioread32be(&regs->rcse);
break;
case E_DTSEC_STAT_RUND:
ret_val = ioread32be(&regs->rund);
break;
case E_DTSEC_STAT_ROVR:
ret_val = ioread32be(&regs->rovr);
break;
case E_DTSEC_STAT_RFRG:
ret_val = ioread32be(&regs->rfrg);
break;
case E_DTSEC_STAT_RJBR:
ret_val = ioread32be(&regs->rjbr);
break;
case E_DTSEC_STAT_RDRP:
ret_val = ioread32be(&regs->rdrp);
break;
case E_DTSEC_STAT_TFCS:
ret_val = ioread32be(&regs->tfcs);
break;
case E_DTSEC_STAT_TBYT:
ret_val = ioread32be(&regs->tbyt);
break;
case E_DTSEC_STAT_TPKT:
ret_val = ioread32be(&regs->tpkt);
break;
case E_DTSEC_STAT_TMCA:
ret_val = ioread32be(&regs->tmca);
break;
case E_DTSEC_STAT_TBCA:
ret_val = ioread32be(&regs->tbca);
break;
case E_DTSEC_STAT_TXPF:
ret_val = ioread32be(&regs->txpf);
break;
case E_DTSEC_STAT_TNCL:
ret_val = ioread32be(&regs->tncl);
break;
case E_DTSEC_STAT_TDRP:
ret_val = ioread32be(&regs->tdrp);
break;
default:
ret_val = 0;
}
return ret_val;
}

163
sys/contrib/ncsw/Peripherals/FM/MAC/fman_dtsec_mii_acc.c Normal file
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/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "common/general.h"
#include "fsl_fman_dtsec_mii_acc.h"
/**
* dtsec_mii_get_div() - calculates the value of the dtsec mii divider
* @dtsec_freq: dtsec clock frequency (in Mhz)
*
* This function calculates the dtsec mii clock divider that determines
* the MII MDC clock. MII MDC clock will be set to work in the range
* of 1.5 to 2.5Mhz
* The output of this function is the value of MIIMCFG[MgmtClk] which
* implicitly determines the divider value.
* Note: the dTSEC system clock is equal to 1/2 of the FMan clock.
*
* The table below which reflects dtsec_mii_get_div() functionality
* shows the relations among dtsec_freq, MgmtClk, actual divider
* and the MII frequency:
*
* dtsec freq MgmtClk div MII freq Mhz
* [0.....80] 1 (1/4)(1/8) [0 to 2.5]
* [81...120] 2 (1/6)(1/8) [1.6 to 2.5]
* [121..160] 3 (1/8)(1/8) [1.8 to 2.5]
* [161..200] 4 (1/10)(1/8) [2.0 to 2.5]
* [201..280] 5 (1/14)(1/8) [1.8 to 2.5]
* [281..400] 6 (1/20)(1/8) [1.1 to 2.5]
* [401..560] 7 (1/28)(1/8) [1.8 to 2.5]
* [560..frq] 7 (1/28)(1/8) [frq/224]
*
* Returns: the MIIMCFG[MgmtClk] appropriate value
*/
static uint8_t dtsec_mii_get_div(uint16_t dtsec_freq)
{
uint16_t mgmt_clk;
if (dtsec_freq < 80) mgmt_clk = 1;
else if (dtsec_freq < 120) mgmt_clk = 2;
else if (dtsec_freq < 160) mgmt_clk = 3;
else if (dtsec_freq < 200) mgmt_clk = 4;
else if (dtsec_freq < 280) mgmt_clk = 5;
else if (dtsec_freq < 400) mgmt_clk = 6;
else mgmt_clk = 7;
return (uint8_t)mgmt_clk;
}
void fman_dtsec_mii_reset(struct dtsec_mii_reg *regs)
{
/* Reset the management interface */
iowrite32be(ioread32be(&regs->miimcfg) | MIIMCFG_RESET_MGMT,
&regs->miimcfg);
iowrite32be(ioread32be(&regs->miimcfg) & ~MIIMCFG_RESET_MGMT,
&regs->miimcfg);
}
int fman_dtsec_mii_write_reg(struct dtsec_mii_reg *regs, uint8_t addr,
uint8_t reg, uint16_t data, uint16_t dtsec_freq)
{
uint32_t tmp;
/* Setup the MII Mgmt clock speed */
iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), &regs->miimcfg);
wmb();
/* Stop the MII management read cycle */
iowrite32be(0, &regs->miimcom);
/* Dummy read to make sure MIIMCOM is written */
tmp = ioread32be(&regs->miimcom);
wmb();
/* Setting up MII Management Address Register */
tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
iowrite32be(tmp, &regs->miimadd);
wmb();
/* Setting up MII Management Control Register with data */
iowrite32be((uint32_t)data, &regs->miimcon);
/* Dummy read to make sure MIIMCON is written */
tmp = ioread32be(&regs->miimcon);
wmb();
/* Wait until MII management write is complete */
/* todo: a timeout could be useful here */
while ((ioread32be(&regs->miimind)) & MIIMIND_BUSY)
/* busy wait */;
return 0;
}
int fman_dtsec_mii_read_reg(struct dtsec_mii_reg *regs, uint8_t addr,
uint8_t reg, uint16_t *data, uint16_t dtsec_freq)
{
uint32_t tmp;
/* Setup the MII Mgmt clock speed */
iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), &regs->miimcfg);
wmb();
/* Setting up the MII Management Address Register */
tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
iowrite32be(tmp, &regs->miimadd);
wmb();
/* Perform an MII management read cycle */
iowrite32be(MIIMCOM_READ_CYCLE, &regs->miimcom);
/* Dummy read to make sure MIIMCOM is written */
tmp = ioread32be(&regs->miimcom);
wmb();
/* Wait until MII management read is complete */
/* todo: a timeout could be useful here */
while ((ioread32be(&regs->miimind)) & MIIMIND_BUSY)
/* busy wait */;
/* Read MII management status */
*data = (uint16_t)ioread32be(&regs->miimstat);
wmb();
iowrite32be(0, &regs->miimcom);
/* Dummy read to make sure MIIMCOM is written */
tmp = ioread32be(&regs->miimcom);
if (*data == 0xffff)
return -ENXIO;
return 0;
}

511
sys/contrib/ncsw/Peripherals/FM/MAC/fman_memac.c Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_memac.h"
uint32_t fman_memac_get_event(struct memac_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->ievent) & ev_mask;
}
uint32_t fman_memac_get_interrupt_mask(struct memac_regs *regs)
{
return ioread32be(&regs->imask);
}
void fman_memac_ack_event(struct memac_regs *regs, uint32_t ev_mask)
{
iowrite32be(ev_mask, &regs->ievent);
}
void fman_memac_set_promiscuous(struct memac_regs *regs, bool val)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (val)
tmp |= CMD_CFG_PROMIS_EN;
else
tmp &= ~CMD_CFG_PROMIS_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_memac_clear_addr_in_paddr(struct memac_regs *regs,
uint8_t paddr_num)
{
if (paddr_num == 0) {
iowrite32be(0, &regs->mac_addr0.mac_addr_l);
iowrite32be(0, &regs->mac_addr0.mac_addr_u);
} else {
iowrite32be(0x0, &regs->mac_addr[paddr_num - 1].mac_addr_l);
iowrite32be(0x0, &regs->mac_addr[paddr_num - 1].mac_addr_u);
}
}
void fman_memac_add_addr_in_paddr(struct memac_regs *regs,
uint8_t *adr,
uint8_t paddr_num)
{
uint32_t tmp0, tmp1;
tmp0 = (uint32_t)(adr[0] |
adr[1] << 8 |
adr[2] << 16 |
adr[3] << 24);
tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
if (paddr_num == 0) {
iowrite32be(tmp0, &regs->mac_addr0.mac_addr_l);
iowrite32be(tmp1, &regs->mac_addr0.mac_addr_u);
} else {
iowrite32be(tmp0, &regs->mac_addr[paddr_num-1].mac_addr_l);
iowrite32be(tmp1, &regs->mac_addr[paddr_num-1].mac_addr_u);
}
}
void fman_memac_enable(struct memac_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (apply_rx)
tmp |= CMD_CFG_RX_EN;
if (apply_tx)
tmp |= CMD_CFG_TX_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_memac_disable(struct memac_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (apply_rx)
tmp &= ~CMD_CFG_RX_EN;
if (apply_tx)
tmp &= ~CMD_CFG_TX_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_memac_reset_stat(struct memac_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->statn_config);
tmp |= STATS_CFG_CLR;
iowrite32be(tmp, &regs->statn_config);
while (ioread32be(&regs->statn_config) & STATS_CFG_CLR);
}
void fman_memac_reset(struct memac_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
tmp |= CMD_CFG_SW_RESET;
iowrite32be(tmp, &regs->command_config);
while (ioread32be(&regs->command_config) & CMD_CFG_SW_RESET);
}
int fman_memac_init(struct memac_regs *regs,
struct memac_cfg *cfg,
enum enet_interface enet_interface,
enum enet_speed enet_speed,
bool slow_10g_if,
uint32_t exceptions)
{
uint32_t tmp;
/* Config */
tmp = 0;
if (cfg->wan_mode_enable)
tmp |= CMD_CFG_WAN_MODE;
if (cfg->promiscuous_mode_enable)
tmp |= CMD_CFG_PROMIS_EN;
if (cfg->pause_forward_enable)
tmp |= CMD_CFG_PAUSE_FWD;
if (cfg->pause_ignore)
tmp |= CMD_CFG_PAUSE_IGNORE;
if (cfg->tx_addr_ins_enable)
tmp |= CMD_CFG_TX_ADDR_INS;
if (cfg->loopback_enable)
tmp |= CMD_CFG_LOOPBACK_EN;
if (cfg->cmd_frame_enable)
tmp |= CMD_CFG_CNT_FRM_EN;
if (cfg->send_idle_enable)
tmp |= CMD_CFG_SEND_IDLE;
if (cfg->no_length_check_enable)
tmp |= CMD_CFG_NO_LEN_CHK;
if (cfg->rx_sfd_any)
tmp |= CMD_CFG_SFD_ANY;
if (cfg->pad_enable)
tmp |= CMD_CFG_TX_PAD_EN;
if (cfg->wake_on_lan)
tmp |= CMD_CFG_MG;
tmp |= CMD_CFG_CRC_FWD;
iowrite32be(tmp, &regs->command_config);
/* Max Frame Length */
iowrite32be((uint32_t)cfg->max_frame_length, &regs->maxfrm);
/* Pause Time */
iowrite32be((uint32_t)cfg->pause_quanta, &regs->pause_quanta[0]);
iowrite32be((uint32_t)0, &regs->pause_thresh[0]);
/* IF_MODE */
tmp = 0;
switch (enet_interface) {
case E_ENET_IF_XGMII:
case E_ENET_IF_XFI:
tmp |= IF_MODE_XGMII;
break;
default:
tmp |= IF_MODE_GMII;
if (enet_interface == E_ENET_IF_RGMII && !cfg->loopback_enable)
tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
}
iowrite32be(tmp, &regs->if_mode);
/* TX_FIFO_SECTIONS */
tmp = 0;
if (enet_interface == E_ENET_IF_XGMII ||
enet_interface == E_ENET_IF_XFI) {
if(slow_10g_if) {
tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
} else {
tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
}
} else {
tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
}
iowrite32be(tmp, &regs->tx_fifo_sections);
/* clear all pending events and set-up interrupts */
fman_memac_ack_event(regs, 0xffffffff);
fman_memac_set_exception(regs, exceptions, TRUE);
return 0;
}
void fman_memac_set_exception(struct memac_regs *regs, uint32_t val, bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->imask);
if (enable)
tmp |= val;
else
tmp &= ~val;
iowrite32be(tmp, &regs->imask);
}
void fman_memac_reset_filter_table(struct memac_regs *regs)
{
uint32_t i;
for (i = 0; i < 64; i++)
iowrite32be(i & ~HASH_CTRL_MCAST_EN, &regs->hashtable_ctrl);
}
void fman_memac_set_hash_table_entry(struct memac_regs *regs, uint32_t crc)
{
iowrite32be(crc | HASH_CTRL_MCAST_EN, &regs->hashtable_ctrl);
}
void fman_memac_set_hash_table(struct memac_regs *regs, uint32_t val)
{
iowrite32be(val, &regs->hashtable_ctrl);
}
uint16_t fman_memac_get_max_frame_len(struct memac_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->maxfrm);
return(uint16_t)tmp;
}
void fman_memac_set_tx_pause_frames(struct memac_regs *regs,
uint8_t priority,
uint16_t pause_time,
uint16_t thresh_time)
{
uint32_t tmp;
tmp = ioread32be(&regs->tx_fifo_sections);
if (priority == 0xff) {
GET_TX_EMPTY_DEFAULT_VALUE(tmp);
iowrite32be(tmp, &regs->tx_fifo_sections);
tmp = ioread32be(&regs->command_config);
tmp &= ~CMD_CFG_PFC_MODE;
priority = 0;
} else {
GET_TX_EMPTY_PFC_VALUE(tmp);
iowrite32be(tmp, &regs->tx_fifo_sections);
tmp = ioread32be(&regs->command_config);
tmp |= CMD_CFG_PFC_MODE;
}
iowrite32be(tmp, &regs->command_config);
tmp = ioread32be(&regs->pause_quanta[priority / 2]);
if (priority % 2)
tmp &= 0x0000FFFF;
else
tmp &= 0xFFFF0000;
tmp |= ((uint32_t)pause_time << (16 * (priority % 2)));
iowrite32be(tmp, &regs->pause_quanta[priority / 2]);
tmp = ioread32be(&regs->pause_thresh[priority / 2]);
if (priority % 2)
tmp &= 0x0000FFFF;
else
tmp &= 0xFFFF0000;
tmp |= ((uint32_t)thresh_time<<(16 * (priority % 2)));
iowrite32be(tmp, &regs->pause_thresh[priority / 2]);
}
void fman_memac_set_rx_ignore_pause_frames(struct memac_regs *regs,bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (enable)
tmp |= CMD_CFG_PAUSE_IGNORE;
else
tmp &= ~CMD_CFG_PAUSE_IGNORE;
iowrite32be(tmp, &regs->command_config);
}
void fman_memac_set_wol(struct memac_regs *regs, bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (enable)
tmp |= CMD_CFG_MG;
else
tmp &= ~CMD_CFG_MG;
iowrite32be(tmp, &regs->command_config);
}
#define GET_MEMAC_CNTR_64(bn) \
(ioread32be(&regs->bn ## _l) | \
((uint64_t)ioread32be(&regs->bn ## _u) << 32))
uint64_t fman_memac_get_counter(struct memac_regs *regs,
enum memac_counters reg_name)
{
uint64_t ret_val;
switch (reg_name) {
case E_MEMAC_COUNTER_R64:
ret_val = GET_MEMAC_CNTR_64(r64);
break;
case E_MEMAC_COUNTER_R127:
ret_val = GET_MEMAC_CNTR_64(r127);
break;
case E_MEMAC_COUNTER_R255:
ret_val = GET_MEMAC_CNTR_64(r255);
break;
case E_MEMAC_COUNTER_R511:
ret_val = GET_MEMAC_CNTR_64(r511);
break;
case E_MEMAC_COUNTER_R1023:
ret_val = GET_MEMAC_CNTR_64(r1023);
break;
case E_MEMAC_COUNTER_R1518:
ret_val = GET_MEMAC_CNTR_64(r1518);
break;
case E_MEMAC_COUNTER_R1519X:
ret_val = GET_MEMAC_CNTR_64(r1519x);
break;
case E_MEMAC_COUNTER_RFRG:
ret_val = GET_MEMAC_CNTR_64(rfrg);
break;
case E_MEMAC_COUNTER_RJBR:
ret_val = GET_MEMAC_CNTR_64(rjbr);
break;
case E_MEMAC_COUNTER_RDRP:
ret_val = GET_MEMAC_CNTR_64(rdrp);
break;
case E_MEMAC_COUNTER_RALN:
ret_val = GET_MEMAC_CNTR_64(raln);
break;
case E_MEMAC_COUNTER_TUND:
ret_val = GET_MEMAC_CNTR_64(tund);
break;
case E_MEMAC_COUNTER_ROVR:
ret_val = GET_MEMAC_CNTR_64(rovr);
break;
case E_MEMAC_COUNTER_RXPF:
ret_val = GET_MEMAC_CNTR_64(rxpf);
break;
case E_MEMAC_COUNTER_TXPF:
ret_val = GET_MEMAC_CNTR_64(txpf);
break;
case E_MEMAC_COUNTER_ROCT:
ret_val = GET_MEMAC_CNTR_64(roct);
break;
case E_MEMAC_COUNTER_RMCA:
ret_val = GET_MEMAC_CNTR_64(rmca);
break;
case E_MEMAC_COUNTER_RBCA:
ret_val = GET_MEMAC_CNTR_64(rbca);
break;
case E_MEMAC_COUNTER_RPKT:
ret_val = GET_MEMAC_CNTR_64(rpkt);
break;
case E_MEMAC_COUNTER_RUCA:
ret_val = GET_MEMAC_CNTR_64(ruca);
break;
case E_MEMAC_COUNTER_RERR:
ret_val = GET_MEMAC_CNTR_64(rerr);
break;
case E_MEMAC_COUNTER_TOCT:
ret_val = GET_MEMAC_CNTR_64(toct);
break;
case E_MEMAC_COUNTER_TMCA:
ret_val = GET_MEMAC_CNTR_64(tmca);
break;
case E_MEMAC_COUNTER_TBCA:
ret_val = GET_MEMAC_CNTR_64(tbca);
break;
case E_MEMAC_COUNTER_TUCA:
ret_val = GET_MEMAC_CNTR_64(tuca);
break;
case E_MEMAC_COUNTER_TERR:
ret_val = GET_MEMAC_CNTR_64(terr);
break;
default:
ret_val = 0;
}
return ret_val;
}
void fman_memac_adjust_link(struct memac_regs *regs,
enum enet_interface iface_mode,
enum enet_speed speed, bool full_dx)
{
uint32_t tmp;
tmp = ioread32be(&regs->if_mode);
if (full_dx)
tmp &= ~IF_MODE_HD;
else
tmp |= IF_MODE_HD;
if (iface_mode == E_ENET_IF_RGMII) {
/* Configure RGMII in manual mode */
tmp &= ~IF_MODE_RGMII_AUTO;
tmp &= ~IF_MODE_RGMII_SP_MASK;
if (full_dx)
tmp |= IF_MODE_RGMII_FD;
else
tmp &= ~IF_MODE_RGMII_FD;
switch (speed) {
case E_ENET_SPEED_1000:
tmp |= IF_MODE_RGMII_1000;
break;
case E_ENET_SPEED_100:
tmp |= IF_MODE_RGMII_100;
break;
case E_ENET_SPEED_10:
tmp |= IF_MODE_RGMII_10;
break;
default:
break;
}
}
iowrite32be(tmp, &regs->if_mode);
}
void fman_memac_defconfig(struct memac_cfg *cfg)
{
cfg->reset_on_init = FALSE;
cfg->wan_mode_enable = FALSE;
cfg->promiscuous_mode_enable = FALSE;
cfg->pause_forward_enable = FALSE;
cfg->pause_ignore = FALSE;
cfg->tx_addr_ins_enable = FALSE;
cfg->loopback_enable = FALSE;
cfg->cmd_frame_enable = FALSE;
cfg->rx_error_discard = FALSE;
cfg->send_idle_enable = FALSE;
cfg->no_length_check_enable = TRUE;
cfg->lgth_check_nostdr = FALSE;
cfg->time_stamp_enable = FALSE;
cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
cfg->max_frame_length = DEFAULT_FRAME_LENGTH;
cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;
cfg->pad_enable = TRUE;
cfg->phy_tx_ena_on = FALSE;
cfg->rx_sfd_any = FALSE;
cfg->rx_pbl_fwd = FALSE;
cfg->tx_pbl_fwd = FALSE;
cfg->debug_mode = FALSE;
cfg->wake_on_lan = FALSE;
}

213
sys/contrib/ncsw/Peripherals/FM/MAC/fman_memac_mii_acc.c Executable file
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/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_memac_mii_acc.h"
static void write_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t data)
{
uint32_t tmp_reg;
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
/* Leave only MDIO_CLK_DIV bits set on */
tmp_reg &= MDIO_CFG_CLK_DIV_MASK;
/* Set maximum MDIO_HOLD value to allow phy to see
change of data signal */
tmp_reg |= MDIO_CFG_HOLD_MASK;
/* Add 10G interface mode */
tmp_reg |= MDIO_CFG_ENC45;
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Specify phy and register to be accessed */
iowrite32be(phy_addr, &mii_regs->mdio_ctrl);
iowrite32be(reg, &mii_regs->mdio_addr);
wmb();
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Write data */
iowrite32be(data, &mii_regs->mdio_data);
wmb();
/* Wait for write transaction end */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
}
static uint32_t read_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t *data)
{
uint32_t tmp_reg;
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
/* Leave only MDIO_CLK_DIV bits set on */
tmp_reg &= MDIO_CFG_CLK_DIV_MASK;
/* Set maximum MDIO_HOLD value to allow phy to see
change of data signal */
tmp_reg |= MDIO_CFG_HOLD_MASK;
/* Add 10G interface mode */
tmp_reg |= MDIO_CFG_ENC45;
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Specify phy and register to be accessed */
iowrite32be(phy_addr, &mii_regs->mdio_ctrl);
iowrite32be(reg, &mii_regs->mdio_addr);
wmb();
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Read cycle */
tmp_reg = phy_addr;
tmp_reg |= MDIO_CTL_READ;
iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
wmb();
/* Wait for data to be available */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
*data = (uint16_t)ioread32be(&mii_regs->mdio_data);
/* Check if there was an error */
return ioread32be(&mii_regs->mdio_cfg);
}
static void write_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t data)
{
uint32_t tmp_reg;
/* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Write transaction */
tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
tmp_reg |= reg;
iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
iowrite32be(data, &mii_regs->mdio_data);
wmb();
/* Wait for write transaction to end */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
}
static uint32_t read_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t *data)
{
uint32_t tmp_reg;
/* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Read transaction */
tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
tmp_reg |= reg;
tmp_reg |= MDIO_CTL_READ;
iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Wait for data to be available */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
*data = (uint16_t)ioread32be(&mii_regs->mdio_data);
/* Check error */
return ioread32be(&mii_regs->mdio_cfg);
}
/*****************************************************************************/
int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t data,
enum enet_speed enet_speed)
{
/* Figure out interface type - 10G vs 1G.
In 10G interface both phy_addr and devAddr present. */
if (enet_speed == E_ENET_SPEED_10000)
write_phy_reg_10g(mii_regs, phy_addr, reg, data);
else
write_phy_reg_1g(mii_regs, phy_addr, reg, data);
return 0;
}
/*****************************************************************************/
int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t *data,
enum enet_speed enet_speed)
{
uint32_t ans;
/* Figure out interface type - 10G vs 1G.
In 10G interface both phy_addr and devAddr present. */
if (enet_speed == E_ENET_SPEED_10000)
ans = read_phy_reg_10g(mii_regs, phy_addr, reg, data);
else
ans = read_phy_reg_1g(mii_regs, phy_addr, reg, data);
if (ans & MDIO_CFG_READ_ERR)
return -EINVAL;
return 0;
}
/* ......................................................................... */

367
sys/contrib/ncsw/Peripherals/FM/MAC/fman_tgec.c Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_tgec.h"
void fman_tgec_set_mac_address(struct tgec_regs *regs, uint8_t *adr)
{
uint32_t tmp0, tmp1;
tmp0 = (uint32_t)(adr[0] |
adr[1] << 8 |
adr[2] << 16 |
adr[3] << 24);
tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
iowrite32be(tmp0, &regs->mac_addr_0);
iowrite32be(tmp1, &regs->mac_addr_1);
}
void fman_tgec_reset_stat(struct tgec_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
tmp |= CMD_CFG_STAT_CLR;
iowrite32be(tmp, &regs->command_config);
while (ioread32be(&regs->command_config) & CMD_CFG_STAT_CLR) ;
}
#define GET_TGEC_CNTR_64(bn) \
(((uint64_t)ioread32be(&regs->bn ## _u) << 32) | \
ioread32be(&regs->bn ## _l))
uint64_t fman_tgec_get_counter(struct tgec_regs *regs, enum tgec_counters reg_name)
{
uint64_t ret_val;
switch (reg_name) {
case E_TGEC_COUNTER_R64:
ret_val = GET_TGEC_CNTR_64(r64);
break;
case E_TGEC_COUNTER_R127:
ret_val = GET_TGEC_CNTR_64(r127);
break;
case E_TGEC_COUNTER_R255:
ret_val = GET_TGEC_CNTR_64(r255);
break;
case E_TGEC_COUNTER_R511:
ret_val = GET_TGEC_CNTR_64(r511);
break;
case E_TGEC_COUNTER_R1023:
ret_val = GET_TGEC_CNTR_64(r1023);
break;
case E_TGEC_COUNTER_R1518:
ret_val = GET_TGEC_CNTR_64(r1518);
break;
case E_TGEC_COUNTER_R1519X:
ret_val = GET_TGEC_CNTR_64(r1519x);
break;
case E_TGEC_COUNTER_TRFRG:
ret_val = GET_TGEC_CNTR_64(trfrg);
break;
case E_TGEC_COUNTER_TRJBR:
ret_val = GET_TGEC_CNTR_64(trjbr);
break;
case E_TGEC_COUNTER_RDRP:
ret_val = GET_TGEC_CNTR_64(rdrp);
break;
case E_TGEC_COUNTER_RALN:
ret_val = GET_TGEC_CNTR_64(raln);
break;
case E_TGEC_COUNTER_TRUND:
ret_val = GET_TGEC_CNTR_64(trund);
break;
case E_TGEC_COUNTER_TROVR:
ret_val = GET_TGEC_CNTR_64(trovr);
break;
case E_TGEC_COUNTER_RXPF:
ret_val = GET_TGEC_CNTR_64(rxpf);
break;
case E_TGEC_COUNTER_TXPF:
ret_val = GET_TGEC_CNTR_64(txpf);
break;
case E_TGEC_COUNTER_ROCT:
ret_val = GET_TGEC_CNTR_64(roct);
break;
case E_TGEC_COUNTER_RMCA:
ret_val = GET_TGEC_CNTR_64(rmca);
break;
case E_TGEC_COUNTER_RBCA:
ret_val = GET_TGEC_CNTR_64(rbca);
break;
case E_TGEC_COUNTER_RPKT:
ret_val = GET_TGEC_CNTR_64(rpkt);
break;
case E_TGEC_COUNTER_RUCA:
ret_val = GET_TGEC_CNTR_64(ruca);
break;
case E_TGEC_COUNTER_RERR:
ret_val = GET_TGEC_CNTR_64(rerr);
break;
case E_TGEC_COUNTER_TOCT:
ret_val = GET_TGEC_CNTR_64(toct);
break;
case E_TGEC_COUNTER_TMCA:
ret_val = GET_TGEC_CNTR_64(tmca);
break;
case E_TGEC_COUNTER_TBCA:
ret_val = GET_TGEC_CNTR_64(tbca);
break;
case E_TGEC_COUNTER_TUCA:
ret_val = GET_TGEC_CNTR_64(tuca);
break;
case E_TGEC_COUNTER_TERR:
ret_val = GET_TGEC_CNTR_64(terr);
break;
default:
ret_val = 0;
}
return ret_val;
}
void fman_tgec_enable(struct tgec_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (apply_rx)
tmp |= CMD_CFG_RX_EN;
if (apply_tx)
tmp |= CMD_CFG_TX_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_tgec_disable(struct tgec_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp_reg_32;
tmp_reg_32 = ioread32be(&regs->command_config);
if (apply_rx)
tmp_reg_32 &= ~CMD_CFG_RX_EN;
if (apply_tx)
tmp_reg_32 &= ~CMD_CFG_TX_EN;
iowrite32be(tmp_reg_32, &regs->command_config);
}
void fman_tgec_set_promiscuous(struct tgec_regs *regs, bool val)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (val)
tmp |= CMD_CFG_PROMIS_EN;
else
tmp &= ~CMD_CFG_PROMIS_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_tgec_reset_filter_table(struct tgec_regs *regs)
{
uint32_t i;
for (i = 0; i < 512; i++)
iowrite32be(i & ~TGEC_HASH_MCAST_EN, &regs->hashtable_ctrl);
}
void fman_tgec_set_hash_table_entry(struct tgec_regs *regs, uint32_t crc)
{
uint32_t hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; /* Take 9 MSB bits */
iowrite32be(hash | TGEC_HASH_MCAST_EN, &regs->hashtable_ctrl);
}
void fman_tgec_set_hash_table(struct tgec_regs *regs, uint32_t value)
{
iowrite32be(value, &regs->hashtable_ctrl);
}
void fman_tgec_set_tx_pause_frames(struct tgec_regs *regs, uint16_t pause_time)
{
iowrite32be((uint32_t)pause_time, &regs->pause_quant);
}
void fman_tgec_set_rx_ignore_pause_frames(struct tgec_regs *regs, bool en)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (en)
tmp |= CMD_CFG_PAUSE_IGNORE;
else
tmp &= ~CMD_CFG_PAUSE_IGNORE;
iowrite32be(tmp, &regs->command_config);
}
void fman_tgec_enable_1588_time_stamp(struct tgec_regs *regs, bool en)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (en)
tmp |= CMD_CFG_EN_TIMESTAMP;
else
tmp &= ~CMD_CFG_EN_TIMESTAMP;
iowrite32be(tmp, &regs->command_config);
}
uint32_t fman_tgec_get_event(struct tgec_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->ievent) & ev_mask;
}
void fman_tgec_ack_event(struct tgec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ev_mask, &regs->ievent);
}
uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs *regs)
{
return ioread32be(&regs->imask);
}
void fman_tgec_add_addr_in_paddr(struct tgec_regs *regs, uint8_t *adr)
{
uint32_t tmp0, tmp1;
tmp0 = (uint32_t)(adr[0] |
adr[1] << 8 |
adr[2] << 16 |
adr[3] << 24);
tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
iowrite32be(tmp0, &regs->mac_addr_2);
iowrite32be(tmp1, &regs->mac_addr_3);
}
void fman_tgec_clear_addr_in_paddr(struct tgec_regs *regs)
{
iowrite32be(0, &regs->mac_addr_2);
iowrite32be(0, &regs->mac_addr_3);
}
uint32_t fman_tgec_get_revision(struct tgec_regs *regs)
{
return ioread32be(&regs->tgec_id);
}
void fman_tgec_enable_interrupt(struct tgec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ioread32be(&regs->imask) | ev_mask, &regs->imask);
}
void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ioread32be(&regs->imask) & ~ev_mask, &regs->imask);
}
uint16_t fman_tgec_get_max_frame_len(struct tgec_regs *regs)
{
return (uint16_t) ioread32be(&regs->maxfrm);
}
void fman_tgec_defconfig(struct tgec_cfg *cfg)
{
cfg->wan_mode_enable = DEFAULT_WAN_MODE_ENABLE;
cfg->promiscuous_mode_enable = DEFAULT_PROMISCUOUS_MODE_ENABLE;
cfg->pause_forward_enable = DEFAULT_PAUSE_FORWARD_ENABLE;
cfg->pause_ignore = DEFAULT_PAUSE_IGNORE;
cfg->tx_addr_ins_enable = DEFAULT_TX_ADDR_INS_ENABLE;
cfg->loopback_enable = DEFAULT_LOOPBACK_ENABLE;
cfg->cmd_frame_enable = DEFAULT_CMD_FRAME_ENABLE;
cfg->rx_error_discard = DEFAULT_RX_ERROR_DISCARD;
cfg->send_idle_enable = DEFAULT_SEND_IDLE_ENABLE;
cfg->no_length_check_enable = DEFAULT_NO_LENGTH_CHECK_ENABLE;
cfg->lgth_check_nostdr = DEFAULT_LGTH_CHECK_NOSTDR;
cfg->time_stamp_enable = DEFAULT_TIME_STAMP_ENABLE;
cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH;
cfg->pause_quant = DEFAULT_PAUSE_QUANT;
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
cfg->skip_fman11_workaround = FALSE;
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
}
int fman_tgec_init(struct tgec_regs *regs, struct tgec_cfg *cfg,
uint32_t exception_mask)
{
uint32_t tmp;
/* Config */
tmp = 0x40; /* CRC forward */
if (cfg->wan_mode_enable)
tmp |= CMD_CFG_WAN_MODE;
if (cfg->promiscuous_mode_enable)
tmp |= CMD_CFG_PROMIS_EN;
if (cfg->pause_forward_enable)
tmp |= CMD_CFG_PAUSE_FWD;
if (cfg->pause_ignore)
tmp |= CMD_CFG_PAUSE_IGNORE;
if (cfg->tx_addr_ins_enable)
tmp |= CMD_CFG_TX_ADDR_INS;
if (cfg->loopback_enable)
tmp |= CMD_CFG_LOOPBACK_EN;
if (cfg->cmd_frame_enable)
tmp |= CMD_CFG_CMD_FRM_EN;
if (cfg->rx_error_discard)
tmp |= CMD_CFG_RX_ER_DISC;
if (cfg->send_idle_enable)
tmp |= CMD_CFG_SEND_IDLE;
if (cfg->no_length_check_enable)
tmp |= CMD_CFG_NO_LEN_CHK;
if (cfg->time_stamp_enable)
tmp |= CMD_CFG_EN_TIMESTAMP;
iowrite32be(tmp, &regs->command_config);
/* Max Frame Length */
iowrite32be((uint32_t)cfg->max_frame_length, &regs->maxfrm);
/* Pause Time */
iowrite32be(cfg->pause_quant, &regs->pause_quant);
/* clear all pending events and set-up interrupts */
fman_tgec_ack_event(regs, 0xffffffff);
fman_tgec_enable_interrupt(regs, exception_mask);
return 0;
}
void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs *regs)
{
uint32_t tmp;
/* restore the default tx ipg Length */
tmp = (ioread32be(&regs->tx_ipg_len) & ~TGEC_TX_IPG_LENGTH_MASK) | 12;
iowrite32be(tmp, &regs->tx_ipg_len);
}

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File memac.h
@Description FM Multirate Ethernet MAC (mEMAC)
*//***************************************************************************/
#ifndef __MEMAC_H
#define __MEMAC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fsl_fman_memac_mii_acc.h"
#include "fm_mac.h"
#include "fsl_fman_memac.h"
#define MEMAC_default_exceptions \
((uint32_t)(MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI))
#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MAC_EX_10G_1TX_ECC_ER: \
bitMask = MEMAC_IMASK_TECC_ER; break; \
case e_FM_MAC_EX_10G_RX_ECC_ER: \
bitMask = MEMAC_IMASK_RECC_ER; break; \
case e_FM_MAC_EX_TS_FIFO_ECC_ERR: \
bitMask = MEMAC_IMASK_TSECC_ER; break; \
case e_FM_MAC_EX_MAGIC_PACKET_INDICATION: \
bitMask = MEMAC_IMASK_MGI; break; \
default: bitMask = 0;break;}
typedef struct
{
t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */
t_Handle h_App; /**< Handle to the upper layer application */
struct memac_regs *p_MemMap; /**< Pointer to MAC memory mapped registers */
struct memac_mii_access_mem_map *p_MiiMemMap; /**< Pointer to MII memory mapped registers */
uint64_t addr; /**< MAC address of device */
e_EnetMode enetMode; /**< Ethernet physical interface */
t_FmMacExceptionCallback *f_Exception;
int mdioIrq;
t_FmMacExceptionCallback *f_Event;
bool indAddrRegUsed[MEMAC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
uint64_t paddr[MEMAC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
t_EthHash *p_MulticastAddrHash; /**< Pointer to driver's global address hash table */
t_EthHash *p_UnicastAddrHash; /**< Pointer to driver's individual address hash table */
bool debugMode;
uint8_t macId;
uint32_t exceptions;
struct memac_cfg *p_MemacDriverParam;
} t_Memac;
/* Internal PHY access */
#define PHY_MDIO_ADDR 0
/* Internal PHY Registers - SGMII */
#define PHY_SGMII_CR_PHY_RESET 0x8000
#define PHY_SGMII_CR_RESET_AN 0x0200
#define PHY_SGMII_CR_DEF_VAL 0x1140
#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
#define PHY_SGMII_DEV_ABILITY_1000X 0x01A0
#define PHY_SGMII_IF_SPEED_GIGABIT 0x0008
#define PHY_SGMII_IF_MODE_AN 0x0002
#define PHY_SGMII_IF_MODE_SGMII 0x0001
#define PHY_SGMII_IF_MODE_1000X 0x0000
#define MEMAC_TO_MII_OFFSET 0x030 /* Offset from the MEM map to the MDIO mem map */
t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#endif /* __MEMAC_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "error_ext.h"
#include "std_ext.h"
#include "fm_mac.h"
#include "memac.h"
#include "xx_ext.h"
#include "fm_common.h"
#include "memac_mii_acc.h"
/*****************************************************************************/
t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac,
uint8_t phyAddr,
uint8_t reg,
uint16_t data)
{
t_Memac *p_Memac = (t_Memac *)h_Memac;
SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE);
return (t_Error)fman_memac_mii_write_phy_reg(p_Memac->p_MiiMemMap,
phyAddr,
reg,
data,
(enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode));
}
/*****************************************************************************/
t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac,
uint8_t phyAddr,
uint8_t reg,
uint16_t *p_Data)
{
t_Memac *p_Memac = (t_Memac *)h_Memac;
SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE);
return fman_memac_mii_read_phy_reg(p_Memac->p_MiiMemMap,
phyAddr,
reg,
p_Data,
(enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode));
}

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MEMAC_MII_ACC_H
#define __MEMAC_MII_ACC_H
#include "std_ext.h"
/* MII Management Registers */
#define MDIO_CFG_CLK_DIV_MASK 0x0080ff80
#define MDIO_CFG_CLK_DIV_SHIFT 7
#define MDIO_CFG_HOLD_MASK 0x0000001c
#define MDIO_CFG_ENC45 0x00000040
#define MDIO_CFG_READ_ERR 0x00000002
#define MDIO_CFG_BSY 0x00000001
#define MDIO_CTL_PHY_ADDR_SHIFT 5
#define MDIO_CTL_READ 0x00008000
#define MDIO_DATA_BSY 0x80000000
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
/*----------------------------------------------------*/
/* MII Configuration Control Memory Map Registers */
/*----------------------------------------------------*/
typedef struct t_MemacMiiAccessMemMap
{
volatile uint32_t mdio_cfg; /* 0x030 */
volatile uint32_t mdio_ctrl; /* 0x034 */
volatile uint32_t mdio_data; /* 0x038 */
volatile uint32_t mdio_addr; /* 0x03c */
} t_MemacMiiAccessMemMap ;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
#endif /* __MEMAC_MII_ACC_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File tgec.h
@ -41,190 +42,72 @@
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "enet_ext.h"
#include "tgec_mii_acc.h"
#include "fm_mac.h"
/* Interrupt Mask Register (IMASK) */
#define IMASK_MDIO_SCAN_EVENTMDIO 0x00010000 /* MDIO_SCAN_EVENTMDIO scan event interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_MDIO_CMD_CMPL 0x00008000 /* 16 MDIO_CMD_CMPL MDIO command completion interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_REM_FAULT 0x00004000 /* 17 REM_FAULT Remote fault interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_LOC_FAULT 0x00002000 /* 18 LOC_FAULT Local fault interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_1TX_ECC_ER 0x00001000 /* 19 TX_ECC_ER Transmit frame ECC error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_TX_FIFO_UNFL 0x00000800 /* 20 TX_FIFO_UNFL Transmit FIFO underflow interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_TX_FIFO_OVFL 0x00000400 /* 21 TX_FIFO_OVFL Transmit FIFO overflow interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_TX_ER 0x00000200 /* 22 TX_ER Transmit frame error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_FIFO_OVFL 0x00000100 /* 23 RX_FIFO_OVFL Receive FIFO overflow interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_ECC_ER 0x00000080 /* 24 RX_ECC_ER Receive frame ECC error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_JAB_FRM 0x00000040 /* 25 RX_JAB_FRM Receive jabber frame interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_OVRSZ_FRM 0x00000020 /* 26 RX_OVRSZ_FRM Receive oversized frame interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_RUNT_FRM 0x00000010 /* 27 RX_RUNT_FRM Receive runt frame interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_FRAG_FRM 0x00000008 /* 28 RX_FRAG_FRM Receive fragment frame interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_LEN_ER 0x00000004 /* 29 RX_LEN_ER Receive payload length error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_CRC_ER 0x00000002 /* 30 RX_CRC_ER Receive CRC error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_ALIGN_ER 0x00000001 /* 31 RX_ALIGN_ER Receive alignment error interrupt mask.
* 0 masked
* 1 enabled
*/
#define DEFAULT_exceptions \
((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \
TGEC_IMASK_REM_FAULT | \
TGEC_IMASK_LOC_FAULT | \
TGEC_IMASK_TX_ECC_ER | \
TGEC_IMASK_TX_FIFO_UNFL | \
TGEC_IMASK_TX_FIFO_OVFL | \
TGEC_IMASK_TX_ER | \
TGEC_IMASK_RX_FIFO_OVFL | \
TGEC_IMASK_RX_ECC_ER | \
TGEC_IMASK_RX_JAB_FRM | \
TGEC_IMASK_RX_OVRSZ_FRM | \
TGEC_IMASK_RX_RUNT_FRM | \
TGEC_IMASK_RX_FRAG_FRM | \
TGEC_IMASK_RX_CRC_ER | \
TGEC_IMASK_RX_ALIGN_ER))
#define EVENTS_MASK ((uint32_t)(IMASK_MDIO_SCAN_EVENTMDIO | \
IMASK_MDIO_CMD_CMPL | \
IMASK_REM_FAULT | \
IMASK_LOC_FAULT | \
IMASK_1TX_ECC_ER | \
IMASK_TX_FIFO_UNFL | \
IMASK_TX_FIFO_OVFL | \
IMASK_TX_ER | \
IMASK_RX_FIFO_OVFL | \
IMASK_RX_ECC_ER | \
IMASK_RX_JAB_FRM | \
IMASK_RX_OVRSZ_FRM | \
IMASK_RX_RUNT_FRM | \
IMASK_RX_FRAG_FRM | \
IMASK_RX_LEN_ER | \
IMASK_RX_CRC_ER | \
IMASK_RX_ALIGN_ER))
#define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \
case e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO: \
bitMask = IMASK_MDIO_SCAN_EVENTMDIO; break; \
case e_FM_MAC_EX_10G_MDIO_CMD_CMPL: \
bitMask = IMASK_MDIO_CMD_CMPL ; break; \
case e_FM_MAC_EX_10G_REM_FAULT: \
bitMask = IMASK_REM_FAULT ; break; \
case e_FM_MAC_EX_10G_LOC_FAULT: \
bitMask = IMASK_LOC_FAULT ; break; \
case e_FM_MAC_EX_10G_1TX_ECC_ER: \
bitMask = IMASK_1TX_ECC_ER ; break; \
case e_FM_MAC_EX_10G_TX_FIFO_UNFL: \
bitMask = IMASK_TX_FIFO_UNFL ; break; \
case e_FM_MAC_EX_10G_TX_FIFO_OVFL: \
bitMask = IMASK_TX_FIFO_OVFL ; break; \
case e_FM_MAC_EX_10G_TX_ER: \
bitMask = IMASK_TX_ER ; break; \
case e_FM_MAC_EX_10G_RX_FIFO_OVFL: \
bitMask = IMASK_RX_FIFO_OVFL ; break; \
case e_FM_MAC_EX_10G_RX_ECC_ER: \
bitMask = IMASK_RX_ECC_ER ; break; \
case e_FM_MAC_EX_10G_RX_JAB_FRM: \
bitMask = IMASK_RX_JAB_FRM ; break; \
case e_FM_MAC_EX_10G_RX_OVRSZ_FRM: \
bitMask = IMASK_RX_OVRSZ_FRM ; break; \
case e_FM_MAC_EX_10G_RX_RUNT_FRM: \
bitMask = IMASK_RX_RUNT_FRM ; break; \
case e_FM_MAC_EX_10G_RX_FRAG_FRM: \
bitMask = IMASK_RX_FRAG_FRM ; break; \
case e_FM_MAC_EX_10G_RX_LEN_ER: \
bitMask = IMASK_RX_LEN_ER ; break; \
case e_FM_MAC_EX_10G_RX_CRC_ER: \
bitMask = IMASK_RX_CRC_ER ; break; \
case e_FM_MAC_EX_10G_RX_ALIGN_ER: \
bitMask = IMASK_RX_ALIGN_ER ; break; \
#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO: \
bitMask = TGEC_IMASK_MDIO_SCAN_EVENT ; break; \
case e_FM_MAC_EX_10G_MDIO_CMD_CMPL: \
bitMask = TGEC_IMASK_MDIO_CMD_CMPL ; break; \
case e_FM_MAC_EX_10G_REM_FAULT: \
bitMask = TGEC_IMASK_REM_FAULT ; break; \
case e_FM_MAC_EX_10G_LOC_FAULT: \
bitMask = TGEC_IMASK_LOC_FAULT ; break; \
case e_FM_MAC_EX_10G_1TX_ECC_ER: \
bitMask = TGEC_IMASK_TX_ECC_ER ; break; \
case e_FM_MAC_EX_10G_TX_FIFO_UNFL: \
bitMask = TGEC_IMASK_TX_FIFO_UNFL ; break; \
case e_FM_MAC_EX_10G_TX_FIFO_OVFL: \
bitMask = TGEC_IMASK_TX_FIFO_OVFL ; break; \
case e_FM_MAC_EX_10G_TX_ER: \
bitMask = TGEC_IMASK_TX_ER ; break; \
case e_FM_MAC_EX_10G_RX_FIFO_OVFL: \
bitMask = TGEC_IMASK_RX_FIFO_OVFL ; break; \
case e_FM_MAC_EX_10G_RX_ECC_ER: \
bitMask = TGEC_IMASK_RX_ECC_ER ; break; \
case e_FM_MAC_EX_10G_RX_JAB_FRM: \
bitMask = TGEC_IMASK_RX_JAB_FRM ; break; \
case e_FM_MAC_EX_10G_RX_OVRSZ_FRM: \
bitMask = TGEC_IMASK_RX_OVRSZ_FRM ; break; \
case e_FM_MAC_EX_10G_RX_RUNT_FRM: \
bitMask = TGEC_IMASK_RX_RUNT_FRM ; break; \
case e_FM_MAC_EX_10G_RX_FRAG_FRM: \
bitMask = TGEC_IMASK_RX_FRAG_FRM ; break; \
case e_FM_MAC_EX_10G_RX_LEN_ER: \
bitMask = TGEC_IMASK_RX_LEN_ER ; break; \
case e_FM_MAC_EX_10G_RX_CRC_ER: \
bitMask = TGEC_IMASK_RX_CRC_ER ; break; \
case e_FM_MAC_EX_10G_RX_ALIGN_ER: \
bitMask = TGEC_IMASK_RX_ALIGN_ER ; break; \
default: bitMask = 0;break;}
/* Default Config Params */
#define DEFAULT_wanModeEnable FALSE
#define DEFAULT_promiscuousModeEnable FALSE
#define DEFAULT_pauseForwardEnable FALSE
#define DEFAULT_pauseIgnore FALSE
#define DEFAULT_txAddrInsEnable FALSE
#define DEFAULT_loopbackEnable FALSE
#define DEFAULT_cmdFrameEnable FALSE
#define DEFAULT_rxErrorDiscard FALSE
#define DEFAULT_phyTxenaOn FALSE
#define DEFAULT_sendIdleEnable FALSE
#define DEFAULT_noLengthCheckEnable TRUE
#define DEFAULT_lgthCheckNostdr FALSE
#define DEFAULT_timeStampEnable FALSE
#define DEFAULT_rxSfdAny FALSE
#define DEFAULT_rxPblFwd FALSE
#define DEFAULT_txPblFwd FALSE
#define DEFAULT_txIpgLength 12
#define DEFAULT_maxFrameLength 0x600
#define DEFAULT_debugMode FALSE
#define DEFAULT_pauseTime 0xf000
#define DEFAULT_imask 0xf000
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
#define DEFAULT_skipFman11Workaround FALSE
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
#define DEFAULT_exceptions ((uint32_t)(IMASK_MDIO_SCAN_EVENTMDIO | \
IMASK_REM_FAULT | \
IMASK_LOC_FAULT | \
IMASK_1TX_ECC_ER | \
IMASK_TX_FIFO_UNFL | \
IMASK_TX_FIFO_OVFL | \
IMASK_TX_ER | \
IMASK_RX_FIFO_OVFL | \
IMASK_RX_ECC_ER | \
IMASK_RX_JAB_FRM | \
IMASK_RX_OVRSZ_FRM | \
IMASK_RX_RUNT_FRM | \
IMASK_RX_FRAG_FRM | \
IMASK_RX_CRC_ER | \
IMASK_RX_ALIGN_ER))
#define MAX_PACKET_ALIGNMENT 31
#define MAX_INTER_PACKET_GAP 0x7f
#define MAX_INTER_PALTERNATE_BEB 0x0f
#define MAX_RETRANSMISSION 0x0f
#define MAX_COLLISION_WINDOW 0x03ff
#define TGEC_NUM_OF_PADDRS 1 /* number of pattern match registers (entries) */
#define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */
@ -238,225 +121,11 @@
#define TGEC_ID_MAC_VERSION 0x0000FF00
#define TGEC_ID_MAC_REV 0x000000ff
/* Command and Configuration Register (COMMAND_CONFIG) */
#define CMD_CFG_TX_PBL_FWD 0x00800000 /* 08 Transmit Preamble Forwarding (custom preamble).
*/
#define CMD_CFG_RX_PBL_FWD 0x00400000 /* 09 Receive Preamble Forwarding (custom preamble).
*/
#define RX_SFD_ANY 0x00200000 /* 10 Enables, when set, that any character is allowed at the SFD position of the preamble and the frame will be accepted.
*/
#define CMD_CFG_EN_TIMESTAMP 0x00100000 /* 11 EN_TIMESTAMP IEEE 1588 timeStamp functionality control.
* 0 disabled
* 1 enabled
*/
#define CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* 12 TX_ADDR_INS_SEL Transmit MAC address select
* 0 insert using first MAC address
* 1 insert using second MAC address
*/
#define CMD_CFG_LEN_CHK_NOSTDR 0x00040000 /* 13 LEN_CHK_NOSTDR
*/
#define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 NO_LEN_CHK Payload length check disable
* 0 MAC compares the frame payload length with the frame length/type field.
* 1 Payload length check is disabled.
*/
#define CMD_CFG_SEND_IDLE 0x00010000 /* 15 SEND_IDLE Force idle generation
* 0 Normal operation.
* 1 MAC permanently sends XGMII idle sequences even when faults are received.
*/
#define CMD_CFG_PHY_TX_EN 0x00008000 /* 16 PHY_TX_EN PHY transmit enable
* 0 PHY transmit is disabled.
* 1 PHY transmit is enabled.
*/
#define CMD_CFG_RX_ER_DISC 0x00004000 /* 17 RX_ER_DISC Receive error frame discard enable
* 0 Received error frames are processed.
* 1 Any frame received with an error is discarded.
*/
#define CMD_CFG_CMD_FRM_EN 0x00002000 /* 18 CMD_FRM_EN Command frame reception enable
* 0 Only Pause frames are accepted (all other command frames are rejected).
* 1 All command frames are accepted.
*/
#define CMD_CFG_STAT_CLR 0x00001000 /* 19 STAT_CLR Clear statistics
* 0 Normal operations.
* 1 All statistics counters are cleared.
*/
#define CMD_CFG_LOOPBACK_EN 0x00000400 /* 21 LOOPBAC_EN PHY interface loopback enable
* 0 Configure PHY for normal operation.
* 1 Configure PHY for loopback mode.
*/
#define CMD_CFG_TX_ADDR_INS 0x00000200 /* 22 TX_ADDR_INS Transmit source MAC address insertion
* 0 MAC transmits the source MAC address unmodified.
* 1 MAC overwrites the source MAC address with address specified by COMMAND_CONFIG[TX_ADDR_INS_SEL].
*/
#define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 PAUSE_IGNORE Ignore Pause frame quanta
* 0 MAC stops transmit process for the duration specified in the Pause frame quanta of a received Pause frame.
* 1 MAC ignores received Pause frames.
*/
#define CMD_CFG_PAUSE_FWD 0x00000080 /* 24 PAUSE_FWD Terminate/forward received Pause frames
* 0 MAC terminates and discards received Pause frames.
* 1 MAC forwards Pause frames to the user application.
*/
#define CMD_CFG_PROMIS_EN 0x00000010 /* 27 PROMIS_EN Promiscuous operation enable
* 0 Unicast frames with a destination address not matching the core MAC address (defined by registers, MAC_ADDR_0 and MAC_ADDR_1) are rejected.
* 1 All frames are received without any MAC address filtering.
*/
#define CMD_CFG_WAN_MODE 0x00000008 /* 28 WAN_MODE WAN mode enable
* 0 Configure MAC for LAN mode.
* 1 Configure MAC for WAN mode.
*/
#define CMD_CFG_RX_EN 0x00000002 /* 30 RX_EN MAC receive path enable
* 0 MAC receive path is disabled
* 1 MAC receive path is enabled.
*/
#define CMD_CFG_TX_EN 0x00000001 /* 31 TX_EN MAC transmit path enable
* 0 MAC transmit path is disabled
* 1 MAC transmit path is enabled.
*/
/* Hashtable Control Register (HASHTABLE_CTRL) */
#define HASH_CTRL_MCAST_SHIFT 23
#define HASH_CTRL_MCAST_RD 0x00000400 /* 22 MCAST_READ Entry Multicast frame reception for the hash entry.
* 0 disabled
* 1 enabled
*/
#define HASH_CTRL_MCAST_EN 0x00000200 /* 22 MCAST_EN Multicast frame reception for the hash entry.
* 0 disabled
* 1 enabled
*/
#define HASH_ADDR_MASK 0x000001ff /* 23-31 HASH_ADDR Hash table address code.
*/
/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
#define TX_IPG_LENGTH_MASK 0x000003ff
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/*
* 10G memory map
*/
typedef _Packed struct {
/* 10Ge General Control and Status */
volatile uint32_t tgec_id; /* 0x000 10GEC_ID - Controller ID register */
volatile uint32_t scratch; /* 0x004 */
volatile uint32_t cmd_conf_ctrl; /* 0x008 COMMAND_CONFIG - Control and configuration register */
volatile uint32_t mac_addr_0; /* 0x00C MAC_ADDR_0 - Lower 32 bits of the first 48-bit MAC address */
volatile uint32_t mac_addr_1; /* 0x010 MAC_ADDR_1 - Upper 16 bits of the first 48-bit MAC address */
volatile uint32_t maxfrm; /* 0x014 MAXFRM - Maximum frame length register */
volatile uint32_t pause_quant; /* 0x018 PAUSE_QUANT - Pause quanta register */
volatile uint32_t rx_fifo_sections; /* 0x01c */
volatile uint32_t tx_fifo_sections; /* 0x020 */
volatile uint32_t rx_fifo_almost_f_e; /* 0x024 */
volatile uint32_t tx_fifo_almost_f_e; /* 0x028 */
volatile uint32_t hashtable_ctrl; /* 0x02C HASHTABLE_CTRL - Hash table control register */
volatile uint32_t mdio_cfg_status; /* 0x030 */
volatile uint32_t mdio_command; /* 0x034 */
volatile uint32_t mdio_data; /* 0x038 */
volatile uint32_t mdio_regaddr; /* 0x03c */
volatile uint32_t status; /* 0x040 */
volatile uint32_t tx_ipg_len; /* 0x044 TX_IPG_LENGTH - Transmitter inter-packet-gap register */
volatile uint32_t mac_addr_2; /* 0x048 MAC_ADDR_2 - Lower 32 bits of the second 48-bit MAC address */
volatile uint32_t mac_addr_3; /* 0x04C MAC_ADDR_3 - Upper 16 bits of the second 48-bit MAC address */
volatile uint32_t rx_fifo_ptr_rd; /* 0x050 */
volatile uint32_t rx_fifo_ptr_wr; /* 0x054 */
volatile uint32_t tx_fifo_ptr_rd; /* 0x058 */
volatile uint32_t tx_fifo_ptr_wr; /* 0x05c */
volatile uint32_t imask; /* 0x060 IMASK - Interrupt mask register */
volatile uint32_t ievent; /* 0x064 IEVENT - Interrupt event register */
volatile uint32_t udp_port; /* 0x068 Defines a UDP Port number. When an UDP/IP frame is received with a matching UDP destination port, the receive status indication pin ff_rx_ts_frm will be asserted.*/
volatile uint32_t type_1588v2; /* 0x06c Type field for 1588v2 layer 2 frames. IEEE1588 defines the type 0x88f7 for 1588 frames. */
volatile uint32_t TENGEC_RESERVED4[4];
/*10Ge Statistics Counter */
volatile uint64_t TFRM; /* 80 aFramesTransmittedOK */
volatile uint64_t RFRM; /* 88 aFramesReceivedOK */
volatile uint64_t RFCS; /* 90 aFrameCheckSequenceErrors */
volatile uint64_t RALN; /* 98 aAlignmentErrors */
volatile uint64_t TXPF; /* A0 aPAUSEMACCtrlFramesTransmitted */
volatile uint64_t RXPF; /* A8 aPAUSEMACCtrlFramesReceived */
volatile uint64_t RLONG; /* B0 aFrameTooLongErrors */
volatile uint64_t RFLR; /* B8 aInRangeLengthErrors */
volatile uint64_t TVLAN; /* C0 VLANTransmittedOK */
volatile uint64_t RVLAN; /* C8 VLANReceivedOK */
volatile uint64_t TOCT; /* D0 ifOutOctets */
volatile uint64_t ROCT; /* D8 ifInOctets */
volatile uint64_t RUCA; /* E0 ifInUcastPkts */
volatile uint64_t RMCA; /* E8 ifInMulticastPkts */
volatile uint64_t RBCA; /* F0 ifInBroadcastPkts */
volatile uint64_t TERR; /* F8 ifOutErrors */
volatile uint32_t TENGEC_RESERVED6[2];
volatile uint64_t TUCA; /* 108 ifOutUcastPkts */
volatile uint64_t TMCA; /* 110 ifOutMulticastPkts */
volatile uint64_t TBCA; /* 118 ifOutBroadcastPkts */
volatile uint64_t RDRP; /* 120 etherStatsDropEvents */
volatile uint64_t REOCT; /* 128 etherStatsOctets */
volatile uint64_t RPKT; /* 130 etherStatsPkts */
volatile uint64_t TRUND; /* 138 etherStatsUndersizePkts */
volatile uint64_t R64; /* 140 etherStatsPkts64Octets */
volatile uint64_t R127; /* 148 etherStatsPkts65to127Octets */
volatile uint64_t R255; /* 150 etherStatsPkts128to255Octets */
volatile uint64_t R511; /* 158 etherStatsPkts256to511Octets */
volatile uint64_t R1023; /* 160 etherStatsPkts512to1023Octets */
volatile uint64_t R1518; /* 168 etherStatsPkts1024to1518Octets */
volatile uint64_t R1519X; /* 170 etherStatsPkts1519toX */
volatile uint64_t TROVR; /* 178 etherStatsOversizePkts */
volatile uint64_t TRJBR; /* 180 etherStatsJabbers */
volatile uint64_t TRFRG; /* 188 etherStatsFragments */
volatile uint64_t RERR; /* 190 ifInErrors */
} _PackedType t_TgecMemMap;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
typedef struct {
bool wanModeEnable; /* WAN Mode Enable. Sets WAN mode (1) or LAN mode (0, default) of operation. */
bool promiscuousModeEnable; /* Enables MAC promiscuous operation. When set to '1', all frames are received without any MAC address filtering, when set to '0' (Reset value) Unicast Frames with a destination address not matching the Core MAC Address (MAC Address programmed in Registers MAC_ADDR_0 and MAC_ADDR_1 or the MAC address programmed in Registers MAC_ADDR_2 and MAC_ADDR_3 ) are rejected. */
bool pauseForwardEnable; /* Terminate / Forward Pause Frames. If set to '1' pause frames are forwarded to the user application. When set to '0' (Reset value) pause frames are terminated and discarded within the MAC. */
bool pauseIgnore; /* Ignore Pause Frame Quanta. If set to '1' received pause frames are ignored by the MAC. When set to '0' (Reset value) the transmit process is stopped for the amount of time specified in the pause quanta received within a pause frame. */
bool txAddrInsEnable; /* Set Source MAC Address on Transmit.
If set to '1' the MAC overwrites the source MAC address received from the Client Interface with one of the MAC addresses (Refer to section 10.4)
If set to '0' (Reset value), the source MAC address from the Client Interface is transmitted unmodified to the line. */
bool loopbackEnable; /* PHY Interface Loopback. When set to '1', the signal loop_ena is set to '1', when set to '0' (Reset value) the signal loop_ena is set to '0'. */
bool cmdFrameEnable; /* Enables reception of all command frames. When set to '1' all Command Frames are accepted, when set to '0' (Reset Value) only Pause Frames are accepted and all other Command Frames are rejected. */
bool rxErrorDiscard; /* Receive Errored Frame Discard Enable. When set to ‘1’, any frame received with an error is discarded in the Core and not forwarded to the Client interface. When set to ‘0’ (Reset value), errored Frames are forwarded to the Client interface with ff_rx_err asserted. */
bool phyTxenaOn; /* PHY Transmit Enable. When set to '1', the signal phy_txena is set to '1', when set to '0' (Reset value) the signal phy_txena is set to '0' */
bool sendIdleEnable; /* Force Idle Generation. When set to '1', the MAC permanently sends XGMII Idle sequences even when faults are received. */
bool noLengthCheckEnable; /* Payload Length Check Disable. When set to ‘0’ (Reset value), the Core checks the frame's payload length with the Frame Length/Type field, when set to ‘1’, the payload length check is disabled. */
bool lgthCheckNostdr; /* The Core interprets the Length/Type field differently depending on the value of this Bit */
bool timeStampEnable; /* This bit selects between enabling and disabling the IEEE 1588 functionality.
1: IEEE 1588 is enabled.
0: IEEE 1588 is disabled. */
bool rxSfdAny; /* Enables, when set, that any character is allowed at the SFD position of the preamble and the frame will be accepted.
If cleared (default) the frame is accepted only if the 8th byte of the preamble contains the SFD value 0xd5. If another value is received, the frame is discarded and the alignment error counter increments. */
bool rxPblFwd; /* Receive Preamble Forwarding (custom preamble).
If set, the first word (ff_rx_sop) of every received frame contains the preamble of the frame. The frame data starts with the 2nd word from the FIFO.
If the bit is cleared (default) the preamble is removed from the frame before it is written into the receive FIFO. */
bool txPblFwd; /* Transmit Preamble Forwarding (custom preamble).
If set, the first word written into the TX FIFO is considered as frame preamble. The MAC will not add a preamble in front of the frame. Note that bits 7:0 of the preamble word will still be overwritten with the XGMII start character upon transmission.
If cleared (default) the MAC */
uint32_t txIpgLength; /*Transmit Inter-Packet-Gap (IPG) value.
A 6-bit value: Depending on LAN or WAN mode of operation (see COMMAND_CONFIG, 19.2.1 page 91) the value has the following meaning:
- LAN Mode: Number of octets in steps of 4. Valid values are 8, 12, 16, ... 100. DIC is fully supported (see 10.6.1 page 49) for any setting. A default of 12 (reset value) must be set to conform to IEEE802.3ae. Warning: When set to 8, PCS layers may not be able to perform clock rate compensation.
- WAN Mode: Stretch factor. Valid values are 4..15. The stretch factor is calculated as (value+1)*8. A default of 12 (reset value) must be set to conform to IEEE 802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). */
/*.. */
uint16_t maxFrameLength;
bool debugMode;
uint16_t pauseTime;
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
bool skipFman11Workaround;
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
} t_TgecDriverParam;
typedef struct {
t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */
t_Handle h_App; /**< Handle to the upper layer application */
t_TgecMemMap *p_MemMap; /**< pointer to 10G memory mapped registers. */
struct tgec_regs *p_MemMap; /**< pointer to 10G memory mapped registers. */
t_TgecMiiAccessMemMap *p_MiiMemMap; /**< pointer to MII memory mapped registers. */
uint64_t addr; /**< MAC address of device; */
e_EnetMode enetMode; /**< Ethernet physical interface */
@ -471,7 +140,7 @@ typedef struct {
bool debugMode;
uint8_t macId;
uint32_t exceptions;
t_TgecDriverParam *p_TgecDriverParam;
struct tgec_cfg *p_TgecDriverParam;
} t_Tgec;

32
sys/contrib/ncsw/Peripherals/FM/MAC/tgec_mii_acc.c
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,12 +31,15 @@
*/
#include "error_ext.h"
#include "std_ext.h"
#include "fm_mac.h"
#include "tgec.h"
#include "xx_ext.h"
#include "fm_common.h"
/*****************************************************************************/
t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec,
@ -46,12 +49,20 @@ t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec,
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
t_TgecMiiAccessMemMap *p_MiiAccess;
uint32_t cfgStatusReg;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Tgec->p_MiiMemMap;
/* Configure MII */
cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
cfgStatusReg &= ~MIIMCOM_DIV_MASK;
/* (one half of fm clock => 2.5Mhz) */
cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
@ -82,13 +93,20 @@ t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
t_TgecMiiAccessMemMap *p_MiiAccess;
uint32_t cfg_status;
uint32_t cfgStatusReg;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Tgec->p_MiiMemMap;
/* Configure MII */
cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
cfgStatusReg &= ~MIIMCOM_DIV_MASK;
/* (one half of fm clock => 2.5Mhz) */
cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
@ -110,12 +128,12 @@ t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,
*p_Data = (uint16_t)GET_UINT32(p_MiiAccess->mdio_data);
cfg_status = GET_UINT32(p_MiiAccess->mdio_cfg_status);
cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
if (cfg_status & MIIMIND_READ_ERROR)
if (cfgStatusReg & MIIMIND_READ_ERROR)
RETURN_ERROR(MINOR, E_INVALID_VALUE,
("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfg_status 0x%x",
((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfg_status));
("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfgStatusReg 0x%x",
((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfgStatusReg));
return E_OK;
}

7
sys/contrib/ncsw/Peripherals/FM/MAC/tgec_mii_acc.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __TGEC_MII_ACC_H
#define __TGEC_MII_ACC_H
@ -59,7 +60,6 @@
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/*----------------------------------------------------*/
/* MII Configuration Control Memory Map Registers */
@ -72,7 +72,6 @@ typedef _Packed struct t_TgecMiiAccessMemMap
volatile uint32_t mdio_regaddr; /* 0x03c */
} _PackedType t_TgecMiiAccessMemMap ;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */

237
sys/contrib/ncsw/Peripherals/FM/MACSEC/fm_macsec.c Normal file
View File

@ -0,0 +1,237 @@
/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec.c
@Description FM MACSEC driver routines implementation.
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "xx_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "debug_ext.h"
#include "fm_macsec.h"
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle FM_MACSEC_Config(t_FmMacsecParams *p_FmMacsecParam)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver;
SANITY_CHECK_RETURN_VALUE(p_FmMacsecParam, E_INVALID_HANDLE, NULL);
if (p_FmMacsecParam->guestMode)
p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)FM_MACSEC_GUEST_Config(p_FmMacsecParam);
else
p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)FM_MACSEC_MASTER_Config(p_FmMacsecParam);
if (!p_FmMacsecControllerDriver)
return NULL;
return (t_Handle)p_FmMacsecControllerDriver;
}
t_Error FM_MACSEC_Init(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_Init)
return p_FmMacsecControllerDriver->f_FM_MACSEC_Init(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_Free(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_Free)
return p_FmMacsecControllerDriver->f_FM_MACSEC_Free(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigUnknownSciFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment(h_FmMacsec, treatMode);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigInvalidTagsFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment(h_FmMacsec, deliverUncontrolled);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(t_Handle h_FmMacsec, bool discardUncontrolled)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(h_FmMacsec, discardUncontrolled);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigUntagFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment(h_FmMacsec, treatMode);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigPnExhaustionThreshold(t_Handle h_FmMacsec, uint32_t pnExhThr)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold(h_FmMacsec, pnExhThr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigKeysUnreadable(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigSectagWithoutSCI(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException(h_FmMacsec, exception, enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_GetRevision(t_Handle h_FmMacsec, uint32_t *p_MacsecRevision)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision)
return p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision(h_FmMacsec, p_MacsecRevision);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_Enable(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_Enable)
return p_FmMacsecControllerDriver->f_FM_MACSEC_Enable(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_Disable(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_Disable)
return p_FmMacsecControllerDriver->f_FM_MACSEC_Disable(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SetException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_SetException)
return p_FmMacsecControllerDriver->f_FM_MACSEC_SetException(h_FmMacsec, exception, enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}

203
sys/contrib/ncsw/Peripherals/FM/MACSEC/fm_macsec.h Normal file
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@ -0,0 +1,203 @@
/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec.h
@Description FM MACSEC internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_MACSEC_H
#define __FM_MACSEC_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_macsec_ext.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_MACSEC
typedef struct
{
t_Error (*f_FM_MACSEC_Init) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_Free) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_ConfigUnknownSciFrameTreatment) (t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode);
t_Error (*f_FM_MACSEC_ConfigInvalidTagsFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled);
t_Error (*f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment) (t_Handle h_FmMacsec, bool discardUncontrolled);
t_Error (*f_FM_MACSEC_ConfigChangedTextWithNoEncryptFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled);
t_Error (*f_FM_MACSEC_ConfigUntagFrameTreatment) (t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode);
t_Error (*f_FM_MACSEC_ConfigOnlyScbIsSetFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled);
t_Error (*f_FM_MACSEC_ConfigPnExhaustionThreshold) (t_Handle h_FmMacsec, uint32_t pnExhThr);
t_Error (*f_FM_MACSEC_ConfigKeysUnreadable) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_ConfigSectagWithoutSCI) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_ConfigException) (t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable);
t_Error (*f_FM_MACSEC_GetRevision) (t_Handle h_FmMacsec, uint32_t *p_MacsecRevision);
t_Error (*f_FM_MACSEC_Enable) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_Disable) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_SetException) (t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable);
} t_FmMacsecControllerDriver;
t_Handle FM_MACSEC_GUEST_Config(t_FmMacsecParams *p_FmMacsecParam);
t_Handle FM_MACSEC_MASTER_Config(t_FmMacsecParams *p_FmMacsecParams);
/***********************************************************************/
/* MACSEC internal routines */
/***********************************************************************/
/**************************************************************************//**
@Group FM_MACSEC_InterModule_grp FM MACSEC Inter-Module Unit
@Description FM MACSEC Inter Module functions -
These are not User API routines but routines that may be called
from other modules. This will be the case in a single core environment,
where instead of using the XX messaging mechanism, the routines may be
called from other modules. In a multicore environment, the other modules may
be run by other cores and therefore these routines may not be called directly.
@{
*//***************************************************************************/
#define MAX_NUM_OF_SA_PER_SC 4
typedef enum
{
e_SC_RX = 0,
e_SC_TX
} e_ScType;
typedef enum
{
e_SC_SA_A = 0,
e_SC_SA_B ,
e_SC_SA_C ,
e_SC_SA_D
} e_ScSaId;
typedef struct
{
uint32_t scId;
macsecSCI_t sci;
bool replayProtect;
uint32_t replayWindow;
e_FmMacsecValidFrameBehavior validateFrames;
uint16_t confidentialityOffset;
e_FmMacsecSecYCipherSuite cipherSuite;
} t_RxScParams;
typedef struct
{
uint32_t scId;
macsecSCI_t sci;
bool protectFrames;
e_FmMacsecSciInsertionMode sciInsertionMode;
bool confidentialityEnable;
uint16_t confidentialityOffset;
e_FmMacsecSecYCipherSuite cipherSuite;
} t_TxScParams;
typedef enum e_FmMacsecGlobalExceptions {
e_FM_MACSEC_EX_TX_SC, /**< Tx Sc 0 frame discarded error. */
e_FM_MACSEC_EX_ECC /**< MACSEC memory ECC multiple-bit error. */
} e_FmMacsecGlobalExceptions;
typedef enum e_FmMacsecGlobalEvents {
e_FM_MACSEC_EV_TX_SC_NEXT_PN /**< Tx Sc 0 Next Pn exhaustion threshold reached. */
} e_FmMacsecGlobalEvents;
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmMacsecEventModules{
e_FM_MACSEC_MOD_SC_TX,
e_FM_MACSEC_MOD_DUMMY_LAST
} e_FmMacsecEventModules;
typedef enum e_FmMacsecInterModuleEvent {
e_FM_MACSEC_EV_SC_TX,
e_FM_MACSEC_EV_ERR_SC_TX,
e_FM_MACSEC_EV_DUMMY_LAST
} e_FmMacsecInterModuleEvent;
#define NUM_OF_INTER_MODULE_EVENTS (NUM_OF_TX_SC * 2)
#define GET_MACSEC_MODULE_EVENT(mod, id, intrType, event) \
switch(mod){ \
case e_FM_MACSEC_MOD_SC_TX: \
event = (intrType == e_FM_INTR_TYPE_ERR) ? \
e_FM_MACSEC_EV_ERR_SC_TX: \
e_FM_MACSEC_EV_SC_TX; \
event += (uint8_t)(2 * id);break; \
break; \
default:event = e_FM_MACSEC_EV_DUMMY_LAST; \
break;}
void FmMacsecRegisterIntr(t_Handle h_FmMacsec,
e_FmMacsecEventModules module,
uint8_t modId,
e_FmIntrType intrType,
void (*f_Isr) (t_Handle h_Arg, uint32_t id),
t_Handle h_Arg);
void FmMacsecUnregisterIntr(t_Handle h_FmMacsec,
e_FmMacsecEventModules module,
uint8_t modId,
e_FmIntrType intrType);
t_Error FmMacsecAllocScs(t_Handle h_FmMacsec, e_ScType type, bool isPtp, uint32_t numOfScs, uint32_t *p_ScIds);
t_Error FmMacsecFreeScs(t_Handle h_FmMacsec, e_ScType type, uint32_t numOfScs, uint32_t *p_ScIds);
t_Error FmMacsecCreateRxSc(t_Handle h_FmMacsec, t_RxScParams *p_RxScParams);
t_Error FmMacsecDeleteRxSc(t_Handle h_FmMacsec, uint32_t scId);
t_Error FmMacsecCreateTxSc(t_Handle h_FmMacsec, t_TxScParams *p_RxScParams);
t_Error FmMacsecDeleteTxSc(t_Handle h_FmMacsec, uint32_t scId);
t_Error FmMacsecCreateRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key);
t_Error FmMacsecCreateTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecSAKey_t key);
t_Error FmMacsecDeleteRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId);
t_Error FmMacsecDeleteTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId);
t_Error FmMacsecRxSaSetReceive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, bool enableReceive);
t_Error FmMacsecRxSaUpdateNextPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtNextPN);
t_Error FmMacsecRxSaUpdateLowestPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtLowestPN);
t_Error FmMacsecTxSaSetActive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an);
t_Error FmMacsecTxSaGetActive(t_Handle h_FmMacsec, uint32_t scId, macsecAN_t *p_An);
t_Error FmMacsecSetPTP(t_Handle h_FmMacsec, bool enable);
t_Error FmMacsecSetException(t_Handle h_FmMacsec, e_FmMacsecGlobalExceptions exception, uint32_t scId, bool enable);
t_Error FmMacsecSetEvent(t_Handle h_FmMacsec, e_FmMacsecGlobalEvents event, uint32_t scId, bool enable);
#endif /* __FM_MACSEC_H */

68
sys/contrib/ncsw/etc/sprint.c → sys/contrib/ncsw/Peripherals/FM/MACSEC/fm_macsec_guest.c
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@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,52 +30,30 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*------------------------------------------------------*/
/* File: sprint.c */
/* */
/* Description: */
/* Debug routines (externals) */
/*------------------------------------------------------*/
#include "string_ext.h"
#include "stdlib_ext.h"
#include "ctype_ext.h"
#include "stdarg_ext.h"
#include "sprint_ext.h"
/******************************************************************************
@File fm_macsec.c
@Description FM MACSEC driver routines implementation.
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "xx_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "debug_ext.h"
#include "fm_macsec.h"
int Sprint(char * buf, const char *fmt, ...)
/****************************************/
/* static functions */
/****************************************/
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle FM_MACSEC_GUEST_Config(t_FmMacsecParams *p_FmMacsecParam)
{
va_list args;
int i;
va_start(args, fmt);
i=vsprintf(buf,fmt,args);
va_end(args);
return i;
UNUSED(p_FmMacsecParam);
return NULL;
}
int Snprint(char * buf, uint32_t size, const char *fmt, ...)
{
va_list args;
int i;
va_start(args, fmt);
i=vsnprintf(buf,size,fmt,args);
va_end(args);
return i;
}
#ifndef NCSW_VXWORKS
int Sscan(const char * buf, const char * fmt, ...)
{
va_list args;
int i;
va_start(args,fmt);
i = vsscanf(buf,fmt,args);
va_end(args);
return i;
}
#endif /* NCSW_VXWORKS */

1031
sys/contrib/ncsw/Peripherals/FM/MACSEC/fm_macsec_master.c Normal file
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479
sys/contrib/ncsw/Peripherals/FM/MACSEC/fm_macsec_master.h Normal file
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@ -0,0 +1,479 @@
/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec_master.h
@Description FM MACSEC internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_MACSEC_MASTER_H
#define __FM_MACSEC_MASTER_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_macsec.h"
#define MACSEC_ICV_SIZE 16
#define MACSEC_SECTAG_SIZE 16
#define MACSEC_SCI_SIZE 8
#define MACSEC_FCS_SIZE 4
/**************************************************************************//**
@Description Exceptions
*//***************************************************************************/
#define FM_MACSEC_EX_TX_SC_0 0x80000000
#define FM_MACSEC_EX_TX_SC(sc) (FM_MACSEC_EX_TX_SC_0 >> (sc))
#define FM_MACSEC_EX_ECC 0x00000001
#define GET_EXCEPTION_FLAG(bitMask, exception, id) switch (exception){ \
case e_FM_MACSEC_EX_TX_SC: \
bitMask = FM_MACSEC_EX_TX_SC(id); break; \
case e_FM_MACSEC_EX_ECC: \
bitMask = FM_MACSEC_EX_ECC; break; \
default: bitMask = 0;break;}
#define FM_MACSEC_USER_EX_SINGLE_BIT_ECC 0x80000000
#define FM_MACSEC_USER_EX_MULTI_BIT_ECC 0x40000000
#define GET_USER_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MACSEC_EX_SINGLE_BIT_ECC: \
bitMask = FM_MACSEC_USER_EX_SINGLE_BIT_ECC; break; \
case e_FM_MACSEC_EX_MULTI_BIT_ECC: \
bitMask = FM_MACSEC_USER_EX_MULTI_BIT_ECC; break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description Events
*//***************************************************************************/
#define FM_MACSEC_EV_TX_SC_0_NEXT_PN 0x80000000
#define FM_MACSEC_EV_TX_SC_NEXT_PN(sc) (FM_MACSEC_EV_TX_SC_0_NEXT_PN >> (sc))
#define GET_EVENT_FLAG(bitMask, event, id) switch (event){ \
case e_FM_MACSEC_EV_TX_SC_NEXT_PN: \
bitMask = FM_MACSEC_EV_TX_SC_NEXT_PN(id); break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description Defaults
*//***************************************************************************/
#define DEFAULT_userExceptions (FM_MACSEC_USER_EX_SINGLE_BIT_ECC |\
FM_MACSEC_USER_EX_MULTI_BIT_ECC)
#define DEFAULT_exceptions (FM_MACSEC_EX_TX_SC(0) |\
FM_MACSEC_EX_TX_SC(1) |\
FM_MACSEC_EX_TX_SC(2) |\
FM_MACSEC_EX_TX_SC(3) |\
FM_MACSEC_EX_TX_SC(4) |\
FM_MACSEC_EX_TX_SC(5) |\
FM_MACSEC_EX_TX_SC(6) |\
FM_MACSEC_EX_TX_SC(7) |\
FM_MACSEC_EX_TX_SC(8) |\
FM_MACSEC_EX_TX_SC(9) |\
FM_MACSEC_EX_TX_SC(10) |\
FM_MACSEC_EX_TX_SC(11) |\
FM_MACSEC_EX_TX_SC(12) |\
FM_MACSEC_EX_TX_SC(13) |\
FM_MACSEC_EX_TX_SC(14) |\
FM_MACSEC_EX_TX_SC(15) |\
FM_MACSEC_EX_ECC )
#define DEFAULT_events (FM_MACSEC_EV_TX_SC_NEXT_PN(0) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(1) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(2) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(3) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(4) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(5) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(6) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(7) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(8) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(9) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(10) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(11) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(12) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(13) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(14) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(15) )
#define DEFAULT_unknownSciFrameTreatment e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DISCARD_BOTH
#define DEFAULT_invalidTagsFrameTreatment FALSE
#define DEFAULT_encryptWithNoChangedTextFrameTreatment FALSE
#define DEFAULT_untagFrameTreatment e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DELIVER_UNCONTROLLED_DISCARD_CONTROLLED
#define DEFAULT_changedTextWithNoEncryptFrameTreatment FALSE
#define DEFAULT_onlyScbIsSetFrameTreatment FALSE
#define DEFAULT_keysUnreadable FALSE
#define DEFAULT_normalMode TRUE
#define DEFAULT_sc0ReservedForPTP FALSE
#define DEFAULT_initNextPn 1
#define DEFAULT_pnExhThr 0xffffffff
#define DEFAULT_sectagOverhead (MACSEC_ICV_SIZE + MACSEC_SECTAG_SIZE)
#define DEFAULT_mflSubtract MACSEC_FCS_SIZE
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
typedef _Packed struct
{
/* MACsec configuration */
volatile uint32_t cfg; /**< MACsec configuration */
volatile uint32_t et; /**< MACsec EtherType */
volatile uint8_t res1[56]; /**< reserved */
volatile uint32_t mfl; /**< Maximum Frame Length */
volatile uint32_t tpnet; /**< TX Packet Number exhaustion threshold */
volatile uint8_t res2[56]; /**< reserved */
volatile uint32_t rxsca; /**< RX SC access select */
volatile uint8_t res3[60]; /**< reserved */
volatile uint32_t txsca; /**< TX SC access select */
volatile uint8_t res4[60]; /**< reserved */
/* RX configuration, status and statistic */
volatile uint32_t rxsci1h; /**< RX Secure Channel Identifier first half */
volatile uint32_t rxsci2h; /**< RX Secure Channel Identifier second half */
volatile uint8_t res5[8]; /**< reserved */
volatile uint32_t ifio1hs; /**< ifInOctets first half Statistic */
volatile uint32_t ifio2hs; /**< ifInOctets second half Statistic */
volatile uint32_t ifiups; /**< ifInUcastPkts Statistic */
volatile uint8_t res6[4]; /**< reserved */
volatile uint32_t ifimps; /**< ifInMulticastPkts Statistic */
volatile uint32_t ifibps; /**< ifInBroadcastPkts Statistic */
volatile uint32_t rxsccfg; /**< RX Secure Channel configuration */
volatile uint32_t rpw; /**< replayWindow */
volatile uint8_t res7[16]; /**< reserved */
volatile uint32_t inov1hs; /**< InOctetsValidated first half Statistic */
volatile uint32_t inov2hs; /**< InOctetsValidated second half Statistic */
volatile uint32_t inod1hs; /**< InOctetsDecrypted first half Statistic */
volatile uint32_t inod2hs; /**< InOctetsDecrypted second half Statistic */
volatile uint32_t rxscipus; /**< RX Secure Channel InPktsUnchecked Statistic */
volatile uint32_t rxscipds; /**< RX Secure Channel InPktsDelayed Statistic */
volatile uint32_t rxscipls; /**< RX Secure Channel InPktsLate Statistic */
volatile uint8_t res8[4]; /**< reserved */
volatile uint32_t rxaninuss[MAX_NUM_OF_SA_PER_SC]; /**< RX AN 0-3 InNotUsingSA Statistic */
volatile uint32_t rxanipuss[MAX_NUM_OF_SA_PER_SC]; /**< RX AN 0-3 InPktsUnusedSA Statistic */
_Packed struct
{
volatile uint32_t rxsacs; /**< RX Security Association configuration and status */
volatile uint32_t rxsanpn; /**< RX Security Association nextPN */
volatile uint32_t rxsalpn; /**< RX Security Association lowestPN */
volatile uint32_t rxsaipos; /**< RX Security Association InPktsOK Statistic */
volatile uint32_t rxsak[4]; /**< RX Security Association key (128 bit) */
volatile uint32_t rxsah[4]; /**< RX Security Association hash (128 bit) */
volatile uint32_t rxsaipis; /**< RX Security Association InPktsInvalid Statistic */
volatile uint32_t rxsaipnvs; /**< RX Security Association InPktsNotValid Statistic */
volatile uint8_t res9[8]; /**< reserved */
} _PackedType fmMacsecRxScSa[NUM_OF_SA_PER_RX_SC];
/* TX configuration, status and statistic */
volatile uint32_t txsci1h; /**< TX Secure Channel Identifier first half */
volatile uint32_t txsci2h; /**< TX Secure Channel Identifier second half */
volatile uint8_t res10[8]; /**< reserved */
volatile uint32_t ifoo1hs; /**< ifOutOctets first half Statistic */
volatile uint32_t ifoo2hs; /**< ifOutOctets second half Statistic */
volatile uint32_t ifoups; /**< ifOutUcastPkts Statistic */
volatile uint32_t opus; /**< OutPktsUntagged Statistic */
volatile uint32_t ifomps; /**< ifOutMulticastPkts Statistic */
volatile uint32_t ifobps; /**< ifOutBroadcastPkts Statistic */
volatile uint32_t txsccfg; /**< TX Secure Channel configuration */
volatile uint32_t optls; /**< OutPktsTooLong Statistic */
volatile uint8_t res11[16]; /**< reserved */
volatile uint32_t oop1hs; /**< OutOctetsProtected first half Statistic */
volatile uint32_t oop2hs; /**< OutOctetsProtected second half Statistic */
volatile uint32_t ooe1hs; /**< OutOctetsEncrypted first half Statistic */
volatile uint32_t ooe2hs; /**< OutOctetsEncrypted second half Statistic */
volatile uint8_t res12[48]; /**< reserved */
_Packed struct
{
volatile uint32_t txsacs; /**< TX Security Association configuration and status */
volatile uint32_t txsanpn; /**< TX Security Association nextPN */
volatile uint32_t txsaopps; /**< TX Security Association OutPktsProtected Statistic */
volatile uint32_t txsaopes; /**< TX Security Association OutPktsEncrypted Statistic */
volatile uint32_t txsak[4]; /**< TX Security Association key (128 bit) */
volatile uint32_t txsah[4]; /**< TX Security Association hash (128 bit) */
volatile uint8_t res13[16]; /**< reserved */
} _PackedType fmMacsecTxScSa[NUM_OF_SA_PER_TX_SC];
volatile uint8_t res14[248]; /**< reserved */
/* Global configuration and status */
volatile uint32_t ip_rev1; /**< MACsec IP Block Revision 1 register */
volatile uint32_t ip_rev2; /**< MACsec IP Block Revision 2 register */
volatile uint32_t evr; /**< MACsec Event Register */
volatile uint32_t ever; /**< MACsec Event Enable Register */
volatile uint32_t evfr; /**< MACsec Event Force Register */
volatile uint32_t err; /**< MACsec Error Register */
volatile uint32_t erer; /**< MACsec Error Enable Register */
volatile uint32_t erfr; /**< MACsec Error Force Register */
volatile uint8_t res15[40]; /**< reserved */
volatile uint32_t meec; /**< MACsec Memory ECC Error Capture Register */
volatile uint32_t idle; /**< MACsec Idle status Register */
volatile uint8_t res16[184]; /**< reserved */
/* DEBUG */
volatile uint32_t rxec; /**< MACsec RX error capture Register */
volatile uint8_t res17[28]; /**< reserved */
volatile uint32_t txec; /**< MACsec TX error capture Register */
volatile uint8_t res18[220]; /**< reserved */
/* Macsec Rx global statistic */
volatile uint32_t ifiocp1hs; /**< ifInOctetsCp first half Statistic */
volatile uint32_t ifiocp2hs; /**< ifInOctetsCp second half Statistic */
volatile uint32_t ifiupcps; /**< ifInUcastPktsCp Statistic */
volatile uint8_t res19[4]; /**< reserved */
volatile uint32_t ifioup1hs; /**< ifInOctetsUp first half Statistic */
volatile uint32_t ifioup2hs; /**< ifInOctetsUp second half Statistic */
volatile uint32_t ifiupups; /**< ifInUcastPktsUp Statistic */
volatile uint8_t res20[4]; /**< reserved */
volatile uint32_t ifimpcps; /**< ifInMulticastPktsCp Statistic */
volatile uint32_t ifibpcps; /**< ifInBroadcastPktsCp Statistic */
volatile uint32_t ifimpups; /**< ifInMulticastPktsUp Statistic */
volatile uint32_t ifibpups; /**< ifInBroadcastPktsUp Statistic */
volatile uint32_t ipwts; /**< InPktsWithoutTag Statistic */
volatile uint32_t ipkays; /**< InPktsKaY Statistic */
volatile uint32_t ipbts; /**< InPktsBadTag Statistic */
volatile uint32_t ipsnfs; /**< InPktsSCINotFound Statistic */
volatile uint32_t ipuecs; /**< InPktsUnsupportedEC Statistic */
volatile uint32_t ipescbs; /**< InPktsEponSingleCopyBroadcast Statistic */
volatile uint32_t iptls; /**< InPktsTooLong Statistic */
volatile uint8_t res21[52]; /**< reserved */
/* Macsec Tx global statistic */
volatile uint32_t opds; /**< OutPktsDiscarded Statistic */
#if (DPAA_VERSION >= 11)
volatile uint8_t res22[124]; /**< reserved */
_Packed struct
{
volatile uint32_t rxsak[8]; /**< RX Security Association key (128/256 bit) */
volatile uint8_t res23[32]; /**< reserved */
} _PackedType rxScSaKey[NUM_OF_SA_PER_RX_SC];
_Packed struct
{
volatile uint32_t txsak[8]; /**< TX Security Association key (128/256 bit) */
volatile uint8_t res24[32]; /**< reserved */
} _PackedType txScSaKey[NUM_OF_SA_PER_TX_SC];
#endif /* (DPAA_VERSION >= 11) */
} _PackedType t_FmMacsecRegs;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description General defines
*//***************************************************************************/
#define SCI_HIGH_MASK 0xffffffff00000000LL
#define SCI_LOW_MASK 0x00000000ffffffffLL
#define LONG_SHIFT 32
#define GET_SCI_FIRST_HALF(sci) (uint32_t)((macsecSCI_t)((macsecSCI_t)(sci) & SCI_HIGH_MASK) >> LONG_SHIFT)
#define GET_SCI_SECOND_HALF(sci) (uint32_t)((macsecSCI_t)(sci) & SCI_LOW_MASK)
/**************************************************************************//**
@Description Configuration defines
*//***************************************************************************/
/* masks */
#define CFG_UECT 0x00000800
#define CFG_ESCBT 0x00000400
#define CFG_USFT 0x00000300
#define CFG_ITT 0x00000080
#define CFG_KFT 0x00000040
#define CFG_UFT 0x00000030
#define CFG_KSS 0x00000004
#define CFG_BYPN 0x00000002
#define CFG_S0I 0x00000001
#define ET_TYPE 0x0000ffff
#define MFL_MAX_LEN 0x0000ffff
#define RXSCA_SC_SEL 0x0000000f
#define TXSCA_SC_SEL 0x0000000f
#define IP_REV_1_IP_ID 0xffff0000
#define IP_REV_1_IP_MJ 0x0000ff00
#define IP_REV_1_IP_MM 0x000000ff
#define IP_REV_2_IP_INT 0x00ff0000
#define IP_REV_2_IP_ERR 0x0000ff00
#define IP_REV_2_IP_CFG 0x000000ff
#define MECC_CAP 0x80000000
#define MECC_CET 0x40000000
#define MECC_SERCNT 0x00ff0000
#define MECC_MEMADDR 0x000001ff
/* shifts */
#define CFG_UECT_SHIFT (31-20)
#define CFG_ESCBT_SHIFT (31-21)
#define CFG_USFT_SHIFT (31-23)
#define CFG_ITT_SHIFT (31-24)
#define CFG_KFT_SHIFT (31-25)
#define CFG_UFT_SHIFT (31-27)
#define CFG_KSS_SHIFT (31-29)
#define CFG_BYPN_SHIFT (31-30)
#define CFG_S0I_SHIFT (31-31)
#define IP_REV_1_IP_ID_SHIFT (31-15)
#define IP_REV_1_IP_MJ_SHIFT (31-23)
#define IP_REV_1_IP_MM_SHIFT (31-31)
#define IP_REV_2_IP_INT_SHIFT (31-15)
#define IP_REV_2_IP_ERR_SHIFT (31-23)
#define IP_REV_2_IP_CFG_SHIFT (31-31)
#define MECC_CAP_SHIFT (31-0)
#define MECC_CET_SHIFT (31-1)
#define MECC_SERCNT_SHIFT (31-15)
#define MECC_MEMADDR_SHIFT (31-31)
/**************************************************************************//**
@Description RX SC defines
*//***************************************************************************/
/* masks */
#define RX_SCCFG_SCI_EN_MASK 0x00000800
#define RX_SCCFG_RP_MASK 0x00000400
#define RX_SCCFG_VF_MASK 0x00000300
#define RX_SCCFG_CO_MASK 0x0000003f
/* shifts */
#define RX_SCCFG_SCI_EN_SHIFT (31-20)
#define RX_SCCFG_RP_SHIFT (31-21)
#define RX_SCCFG_VF_SHIFT (31-23)
#define RX_SCCFG_CO_SHIFT (31-31)
#define RX_SCCFG_CS_SHIFT (31-7)
/**************************************************************************//**
@Description RX SA defines
*//***************************************************************************/
/* masks */
#define RX_SACFG_ACTIVE 0x80000000
#define RX_SACFG_AN_MASK 0x00000006
#define RX_SACFG_EN_MASK 0x00000001
/* shifts */
#define RX_SACFG_AN_SHIFT (31-30)
#define RX_SACFG_EN_SHIFT (31-31)
/**************************************************************************//**
@Description TX SC defines
*//***************************************************************************/
/* masks */
#define TX_SCCFG_AN_MASK 0x000c0000
#define TX_SCCFG_ASA_MASK 0x00020000
#define TX_SCCFG_SCE_MASK 0x00010000
#define TX_SCCFG_CO_MASK 0x00003f00
#define TX_SCCFG_CE_MASK 0x00000010
#define TX_SCCFG_PF_MASK 0x00000008
#define TX_SCCFG_AIS_MASK 0x00000004
#define TX_SCCFG_UES_MASK 0x00000002
#define TX_SCCFG_USCB_MASK 0x00000001
/* shifts */
#define TX_SCCFG_AN_SHIFT (31-13)
#define TX_SCCFG_ASA_SHIFT (31-14)
#define TX_SCCFG_SCE_SHIFT (31-15)
#define TX_SCCFG_CO_SHIFT (31-23)
#define TX_SCCFG_CE_SHIFT (31-27)
#define TX_SCCFG_PF_SHIFT (31-28)
#define TX_SCCFG_AIS_SHIFT (31-29)
#define TX_SCCFG_UES_SHIFT (31-30)
#define TX_SCCFG_USCB_SHIFT (31-31)
#define TX_SCCFG_CS_SHIFT (31-7)
/**************************************************************************//**
@Description TX SA defines
*//***************************************************************************/
/* masks */
#define TX_SACFG_ACTIVE 0x80000000
typedef struct
{
void (*f_Isr) (t_Handle h_Arg, uint32_t id);
t_Handle h_SrcHandle;
} t_FmMacsecIntrSrc;
typedef struct
{
e_FmMacsecUnknownSciFrameTreatment unknownSciTreatMode;
bool invalidTagsDeliverUncontrolled;
bool changedTextWithNoEncryptDeliverUncontrolled;
bool onlyScbIsSetDeliverUncontrolled;
bool encryptWithNoChangedTextDiscardUncontrolled;
e_FmMacsecUntagFrameTreatment untagTreatMode;
uint32_t pnExhThr;
bool keysUnreadable;
bool byPassMode;
bool reservedSc0;
uint32_t sectagOverhead;
uint32_t mflSubtract;
} t_FmMacsecDriverParam;
typedef struct
{
t_FmMacsecControllerDriver fmMacsecControllerDriver;
t_Handle h_Fm;
t_FmMacsecRegs *p_FmMacsecRegs;
t_Handle h_FmMac; /**< A handle to the FM MAC object related to */
char fmMacsecModuleName[MODULE_NAME_SIZE];
t_FmMacsecIntrSrc intrMng[NUM_OF_INTER_MODULE_EVENTS];
uint32_t events;
uint32_t exceptions;
uint32_t userExceptions;
t_FmMacsecExceptionsCallback *f_Exception; /**< Exception Callback Routine */
t_Handle h_App; /**< A handle to an application layer object; This handle will
be passed by the driver upon calling the above callbacks */
bool rxScTable[NUM_OF_RX_SC];
uint32_t numRxScAvailable;
bool txScTable[NUM_OF_TX_SC];
uint32_t numTxScAvailable;
t_Handle rxScSpinLock;
t_Handle txScSpinLock;
t_FmMacsecDriverParam *p_FmMacsecDriverParam;
} t_FmMacsec;
#endif /* __FM_MACSEC_MASTER_H */

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@ -0,0 +1,883 @@
/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec_secy.c
@Description FM MACSEC SECY driver routines implementation.
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "xx_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "fm_macsec_secy.h"
/****************************************/
/* static functions */
/****************************************/
static void FmMacsecSecYExceptionsIsr(t_Handle h_FmMacsecSecY, uint32_t id)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
UNUSED(id);
SANITY_CHECK_RETURN(p_FmMacsecSecY, E_INVALID_HANDLE);
if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED)
p_FmMacsecSecY->f_Exception(p_FmMacsecSecY->h_App, e_FM_MACSEC_SECY_EX_FRAME_DISCARDED);
}
static void FmMacsecSecYEventsIsr(t_Handle h_FmMacsecSecY, uint32_t id)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
UNUSED(id);
SANITY_CHECK_RETURN(p_FmMacsecSecY, E_INVALID_HANDLE);
if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN)
p_FmMacsecSecY->f_Event(p_FmMacsecSecY->h_App, e_FM_MACSEC_SECY_EV_NEXT_PN);
}
static t_Error CheckFmMacsecSecYParameters(t_FmMacsecSecY *p_FmMacsecSecY)
{
if (!p_FmMacsecSecY->f_Exception)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceptions callback not provided"));
if (!p_FmMacsecSecY->f_Event)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Events callback not provided"));
if (!p_FmMacsecSecY->numOfRxSc)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Num of Rx Scs must be greater than '0'"));
return E_OK;
}
static t_Handle FmMacsecSecYCreateSc(t_FmMacsecSecY *p_FmMacsecSecY,
macsecSCI_t sci,
e_FmMacsecSecYCipherSuite cipherSuite,
e_ScType type)
{
t_SecYSc *p_ScTable;
void *p_Params;
uint32_t numOfSc,i;
t_Error err = E_OK;
t_RxScParams rxScParams;
t_TxScParams txScParams;
ASSERT_COND(p_FmMacsecSecY);
ASSERT_COND(p_FmMacsecSecY->h_FmMacsec);
if (type == e_SC_RX)
{
memset(&rxScParams, 0, sizeof(rxScParams));
i = (NUM_OF_RX_SC - 1);
p_ScTable = p_FmMacsecSecY->p_RxSc;
numOfSc = p_FmMacsecSecY->numOfRxSc;
rxScParams.confidentialityOffset = p_FmMacsecSecY->confidentialityOffset;
rxScParams.replayProtect = p_FmMacsecSecY->replayProtect;
rxScParams.replayWindow = p_FmMacsecSecY->replayWindow;
rxScParams.validateFrames = p_FmMacsecSecY->validateFrames;
rxScParams.cipherSuite = cipherSuite;
p_Params = &rxScParams;
}
else
{
memset(&txScParams, 0, sizeof(txScParams));
i = (NUM_OF_TX_SC - 1);
p_ScTable = p_FmMacsecSecY->p_TxSc;
numOfSc = p_FmMacsecSecY->numOfTxSc;
txScParams.sciInsertionMode = p_FmMacsecSecY->sciInsertionMode;
txScParams.protectFrames = p_FmMacsecSecY->protectFrames;
txScParams.confidentialityEnable = p_FmMacsecSecY->confidentialityEnable;
txScParams.confidentialityOffset = p_FmMacsecSecY->confidentialityOffset;
txScParams.cipherSuite = cipherSuite;
p_Params = &txScParams;
}
for (i=0;i<numOfSc;i++)
if (!p_ScTable[i].inUse)
break;
if (i == numOfSc)
{
REPORT_ERROR(MAJOR, E_FULL, ("FM MACSEC SECY SC"));
return NULL;
}
if (type == e_SC_RX)
{
((t_RxScParams *)p_Params)->scId = p_ScTable[i].scId;
((t_RxScParams *)p_Params)->sci = sci;
if ((err = FmMacsecCreateRxSc(p_FmMacsecSecY->h_FmMacsec, (t_RxScParams *)p_Params)) != E_OK)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY RX SC"));
return NULL;
}
}
else
{
((t_TxScParams *)p_Params)->scId = p_ScTable[i].scId;
((t_TxScParams *)p_Params)->sci = sci;
if ((err = FmMacsecCreateTxSc(p_FmMacsecSecY->h_FmMacsec, (t_TxScParams *)p_Params)) != E_OK)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY TX SC"));
return NULL;
}
}
p_ScTable[i].inUse = TRUE;
return &p_ScTable[i];
}
static t_Error FmMacsecSecYDeleteSc(t_FmMacsecSecY *p_FmMacsecSecY, t_SecYSc *p_FmSecYSc, e_ScType type)
{
t_Error err = E_OK;
ASSERT_COND(p_FmMacsecSecY);
ASSERT_COND(p_FmMacsecSecY->h_FmMacsec);
ASSERT_COND(p_FmSecYSc);
if (type == e_SC_RX)
{
if ((err = FmMacsecDeleteRxSc(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
}
else
if ((err = FmMacsecDeleteTxSc(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->inUse = FALSE;
return err;
}
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle FM_MACSEC_SECY_Config(t_FmMacsecSecYParams *p_FmMacsecSecYParam)
{
t_FmMacsecSecY *p_FmMacsecSecY;
/* Allocate FM MACSEC structure */
p_FmMacsecSecY = (t_FmMacsecSecY *) XX_Malloc(sizeof(t_FmMacsecSecY));
if (!p_FmMacsecSecY)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY driver structure"));
return NULL;
}
memset(p_FmMacsecSecY, 0, sizeof(t_FmMacsecSecY));
/* Allocate the FM MACSEC driver's parameters structure */
p_FmMacsecSecY->p_FmMacsecSecYDriverParam = (t_FmMacsecSecYDriverParam *)XX_Malloc(sizeof(t_FmMacsecSecYDriverParam));
if (!p_FmMacsecSecY->p_FmMacsecSecYDriverParam)
{
XX_Free(p_FmMacsecSecY);
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY driver parameters"));
return NULL;
}
memset(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, 0, sizeof(t_FmMacsecSecYDriverParam));
/* Initialize FM MACSEC SECY parameters which will be kept by the driver */
p_FmMacsecSecY->h_FmMacsec = p_FmMacsecSecYParam->h_FmMacsec;
p_FmMacsecSecY->f_Event = p_FmMacsecSecYParam->f_Event;
p_FmMacsecSecY->f_Exception = p_FmMacsecSecYParam->f_Exception;
p_FmMacsecSecY->h_App = p_FmMacsecSecYParam->h_App;
p_FmMacsecSecY->confidentialityEnable = DEFAULT_confidentialityEnable;
p_FmMacsecSecY->confidentialityOffset = DEFAULT_confidentialityOffset;
p_FmMacsecSecY->validateFrames = DEFAULT_validateFrames;
p_FmMacsecSecY->replayProtect = DEFAULT_replayEnable;
p_FmMacsecSecY->replayWindow = DEFAULT_replayWindow;
p_FmMacsecSecY->protectFrames = DEFAULT_protectFrames;
p_FmMacsecSecY->sciInsertionMode = DEFAULT_sciInsertionMode;
p_FmMacsecSecY->isPointToPoint = DEFAULT_ptp;
p_FmMacsecSecY->numOfRxSc = p_FmMacsecSecYParam->numReceiveChannels;
p_FmMacsecSecY->numOfTxSc = DEFAULT_numOfTxSc;
p_FmMacsecSecY->exceptions = DEFAULT_exceptions;
p_FmMacsecSecY->events = DEFAULT_events;
memcpy(&p_FmMacsecSecY->p_FmMacsecSecYDriverParam->txScParams,
&p_FmMacsecSecYParam->txScParams,
sizeof(t_FmMacsecSecYSCParams));
return p_FmMacsecSecY;
}
t_Error FM_MACSEC_SECY_Init(t_Handle h_FmMacsecSecY)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_FmMacsecSecYDriverParam *p_FmMacsecSecYDriverParam = NULL;
uint32_t rxScIds[NUM_OF_RX_SC], txScIds[NUM_OF_TX_SC], i, j;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_HANDLE);
CHECK_INIT_PARAMETERS(p_FmMacsecSecY, CheckFmMacsecSecYParameters);
p_FmMacsecSecYDriverParam = p_FmMacsecSecY->p_FmMacsecSecYDriverParam;
if ((p_FmMacsecSecY->isPointToPoint) &&
((err = FmMacsecSetPTP(p_FmMacsecSecY->h_FmMacsec, TRUE)) != E_OK))
RETURN_ERROR(MAJOR, err, ("Can't set Poin-to-Point"));
/* Rx Sc Allocation */
p_FmMacsecSecY->p_RxSc = (t_SecYSc *)XX_Malloc(sizeof(t_SecYSc) * p_FmMacsecSecY->numOfRxSc);
if (!p_FmMacsecSecY->p_RxSc)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY RX SC"));
memset(p_FmMacsecSecY->p_RxSc, 0, sizeof(t_SecYSc) * p_FmMacsecSecY->numOfRxSc);
if ((err = FmMacsecAllocScs(p_FmMacsecSecY->h_FmMacsec, e_SC_RX, p_FmMacsecSecY->isPointToPoint, p_FmMacsecSecY->numOfRxSc, rxScIds)) != E_OK)
{
if (p_FmMacsecSecY->p_TxSc)
XX_Free(p_FmMacsecSecY->p_TxSc);
if (p_FmMacsecSecY->p_RxSc)
XX_Free(p_FmMacsecSecY->p_RxSc);
return ERROR_CODE(err);
}
for (i=0; i<p_FmMacsecSecY->numOfRxSc; i++)
{
p_FmMacsecSecY->p_RxSc[i].scId = rxScIds[i];
p_FmMacsecSecY->p_RxSc[i].type = e_SC_RX;
for (j=0; j<MAX_NUM_OF_SA_PER_SC;j++)
p_FmMacsecSecY->p_RxSc[i].sa[j].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
}
/* Tx Sc Allocation */
p_FmMacsecSecY->p_TxSc = (t_SecYSc *)XX_Malloc(sizeof(t_SecYSc) * p_FmMacsecSecY->numOfTxSc);
if (!p_FmMacsecSecY->p_TxSc)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY TX SC"));
memset(p_FmMacsecSecY->p_TxSc, 0, sizeof(t_SecYSc) * p_FmMacsecSecY->numOfTxSc);
if ((err = FmMacsecAllocScs(p_FmMacsecSecY->h_FmMacsec, e_SC_TX, p_FmMacsecSecY->isPointToPoint, p_FmMacsecSecY->numOfTxSc, txScIds)) != E_OK)
{
if (p_FmMacsecSecY->p_TxSc)
XX_Free(p_FmMacsecSecY->p_TxSc);
if (p_FmMacsecSecY->p_RxSc)
XX_Free(p_FmMacsecSecY->p_RxSc);
return ERROR_CODE(err);
}
for (i=0; i<p_FmMacsecSecY->numOfTxSc; i++)
{
p_FmMacsecSecY->p_TxSc[i].scId = txScIds[i];
p_FmMacsecSecY->p_TxSc[i].type = e_SC_TX;
for (j=0; j<MAX_NUM_OF_SA_PER_SC;j++)
p_FmMacsecSecY->p_TxSc[i].sa[j].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
FmMacsecRegisterIntr(p_FmMacsecSecY->h_FmMacsec,
e_FM_MACSEC_MOD_SC_TX,
(uint8_t)txScIds[i],
e_FM_INTR_TYPE_ERR,
FmMacsecSecYExceptionsIsr,
p_FmMacsecSecY);
FmMacsecRegisterIntr(p_FmMacsecSecY->h_FmMacsec,
e_FM_MACSEC_MOD_SC_TX,
(uint8_t)txScIds[i],
e_FM_INTR_TYPE_NORMAL,
FmMacsecSecYEventsIsr,
p_FmMacsecSecY);
if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED)
FmMacsecSetException(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EX_TX_SC, txScIds[i], TRUE);
if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN)
FmMacsecSetEvent(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EV_TX_SC_NEXT_PN, txScIds[i], TRUE);
}
FmMacsecSecYCreateSc(p_FmMacsecSecY,
p_FmMacsecSecYDriverParam->txScParams.sci,
p_FmMacsecSecYDriverParam->txScParams.cipherSuite,
e_SC_TX);
XX_Free(p_FmMacsecSecYDriverParam);
p_FmMacsecSecY->p_FmMacsecSecYDriverParam = NULL;
return E_OK;
}
t_Error FM_MACSEC_SECY_Free(t_Handle h_FmMacsecSecY)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_Error err = E_OK;
uint32_t rxScIds[NUM_OF_RX_SC], txScIds[NUM_OF_TX_SC], i;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
if (p_FmMacsecSecY->isPointToPoint)
FmMacsecSetPTP(p_FmMacsecSecY->h_FmMacsec, FALSE);
if (p_FmMacsecSecY->p_RxSc)
{
for (i=0; i<p_FmMacsecSecY->numOfRxSc; i++)
rxScIds[i] = p_FmMacsecSecY->p_RxSc[i].scId;
if ((err = FmMacsecFreeScs(p_FmMacsecSecY->h_FmMacsec, e_SC_RX, p_FmMacsecSecY->numOfRxSc, rxScIds)) != E_OK)
return ERROR_CODE(err);
XX_Free(p_FmMacsecSecY->p_RxSc);
}
if (p_FmMacsecSecY->p_TxSc)
{
FmMacsecSecYDeleteSc(p_FmMacsecSecY, &p_FmMacsecSecY->p_TxSc[0], e_SC_TX);
for (i=0; i<p_FmMacsecSecY->numOfTxSc; i++) {
txScIds[i] = p_FmMacsecSecY->p_TxSc[i].scId;
FmMacsecUnregisterIntr(p_FmMacsecSecY->h_FmMacsec,
e_FM_MACSEC_MOD_SC_TX,
(uint8_t)txScIds[i],
e_FM_INTR_TYPE_ERR);
FmMacsecUnregisterIntr(p_FmMacsecSecY->h_FmMacsec,
e_FM_MACSEC_MOD_SC_TX,
(uint8_t)txScIds[i],
e_FM_INTR_TYPE_NORMAL);
if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED)
FmMacsecSetException(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EX_TX_SC, txScIds[i], FALSE);
if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN)
FmMacsecSetEvent(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EV_TX_SC_NEXT_PN, txScIds[i], FALSE);
}
if ((err = FmMacsecFreeScs(p_FmMacsecSecY->h_FmMacsec, e_SC_TX, p_FmMacsecSecY->numOfTxSc, txScIds)) != E_OK)
return ERROR_CODE(err);
XX_Free(p_FmMacsecSecY->p_TxSc);
}
XX_Free(p_FmMacsecSecY);
return err;
}
t_Error FM_MACSEC_SECY_ConfigSciInsertionMode(t_Handle h_FmMacsecSecY, e_FmMacsecSciInsertionMode sciInsertionMode)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->sciInsertionMode = sciInsertionMode;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigProtectFrames(t_Handle h_FmMacsecSecY, bool protectFrames)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->protectFrames = protectFrames;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigReplayWindow(t_Handle h_FmMacsecSecY, bool replayProtect, uint32_t replayWindow)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->replayProtect = replayProtect;
p_FmMacsecSecY->replayWindow = replayWindow;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigValidationMode(t_Handle h_FmMacsecSecY, e_FmMacsecValidFrameBehavior validateFrames)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->validateFrames = validateFrames;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigConfidentiality(t_Handle h_FmMacsecSecY, bool confidentialityEnable, uint16_t confidentialityOffset)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->confidentialityEnable = confidentialityEnable;
p_FmMacsecSecY->confidentialityOffset = confidentialityOffset;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigPointToPoint(t_Handle h_FmMacsecSecY)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->numOfRxSc = 1;
p_FmMacsecSecY->isPointToPoint = TRUE;
p_FmMacsecSecY->sciInsertionMode = e_FM_MACSEC_SCI_INSERTION_MODE_IMPLICT_PTP;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigException(t_Handle h_FmMacsecSecY, e_FmMacsecSecYExceptions exception, bool enable)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
uint32_t bitMask = 0;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
GET_EXCEPTION_FLAG(bitMask, exception);
if (bitMask)
{
if (enable)
p_FmMacsecSecY->exceptions |= bitMask;
else
p_FmMacsecSecY->exceptions &= ~bitMask;
}
else
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
uint32_t bitMask = 0;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
GET_EVENT_FLAG(bitMask, event);
if (bitMask)
{
if (enable)
p_FmMacsecSecY->events |= bitMask;
else
p_FmMacsecSecY->events &= ~bitMask;
}
else
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined event"));
return E_OK;
}
t_Handle FM_MACSEC_SECY_CreateRxSc(t_Handle h_FmMacsecSecY, t_FmMacsecSecYSCParams *p_ScParams)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_VALUE(p_FmMacsecSecY, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_ScParams, E_NULL_POINTER, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE, NULL);
return FmMacsecSecYCreateSc(p_FmMacsecSecY, p_ScParams->sci, p_ScParams->cipherSuite, e_SC_RX);
}
t_Error FM_MACSEC_SECY_DeleteRxSc(t_Handle h_FmMacsecSecY, t_Handle h_Sc)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
return FmMacsecSecYDeleteSc(p_FmMacsecSecY, p_FmSecYSc, e_SC_RX);
}
t_Error FM_MACSEC_SECY_CreateRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId != SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already assigned",an));
if ((err = FmMacsecCreateRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, (e_ScSaId)p_FmSecYSc->numOfSa, an, lowestPn, key)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->sa[an].saId = (e_ScSaId)p_FmSecYSc->numOfSa++;
return err;
}
t_Error FM_MACSEC_SECY_DeleteRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already deleted",an));
if ((err = FmMacsecDeleteRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->numOfSa--;
p_FmSecYSc->sa[an].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
/* TODO - check if statistics need to be read*/
return err;
}
t_Error FM_MACSEC_SECY_RxSaEnableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, TRUE)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->sa[an].active = TRUE;
return err;
}
t_Error FM_MACSEC_SECY_RxSaDisableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, FALSE)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->sa[an].active = FALSE;
return err;
}
t_Error FM_MACSEC_SECY_RxSaUpdateNextPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtNextPN)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecRxSaUpdateNextPn(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, updtNextPN)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_RxSaUpdateLowestPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtLowestPN)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecRxSaUpdateLowestPn(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, updtLowestPN)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_RxSaModifyKey(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, macsecSAKey_t key)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if (p_FmSecYSc->sa[an].active)
if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, FALSE)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
/* TODO - statistics should be read */
if ((err = FmMacsecCreateRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, an, 1, key)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
if (p_FmSecYSc->sa[an].active)
if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, TRUE)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_CreateTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an, macsecSAKey_t key)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId != SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, err, ("An %d is already assigned",an));
if ((err = FmMacsecCreateTxSa(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, (e_ScSaId)p_FmSecYSc->numOfSa, key)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->sa[an].saId = (e_ScSaId)p_FmSecYSc->numOfSa++;
return err;
}
t_Error FM_MACSEC_SECY_DeleteTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already deleted",an));
if ((err = FmMacsecDeleteTxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->numOfSa--;
p_FmSecYSc->sa[an].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
/* TODO - check if statistics need to be read*/
return err;
}
t_Error FM_MACSEC_SECY_TxSaModifyKey(t_Handle h_FmMacsecSecY, macsecAN_t nextActiveAn, macsecSAKey_t key)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
macsecAN_t currentAn;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(nextActiveAn < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if ((err = FmMacsecTxSaGetActive(p_FmMacsecSecY->h_FmMacsec,
p_FmSecYSc->scId,
&currentAn)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
if ((err = FmMacsecTxSaSetActive(p_FmMacsecSecY->h_FmMacsec,
p_FmSecYSc->scId,
p_FmSecYSc->sa[nextActiveAn].saId,
nextActiveAn)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
/* TODO - statistics should be read */
if ((err = FmMacsecCreateTxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[currentAn].saId, key)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_TxSaSetActive(t_Handle h_FmMacsecSecY, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecTxSaSetActive(p_FmMacsecSecY->h_FmMacsec,
p_FmSecYSc->scId,
p_FmSecYSc->sa[an].saId,
an)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_TxSaGetActive(t_Handle h_FmMacsecSecY, macsecAN_t *p_An)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_An, E_INVALID_HANDLE);
if ((err = FmMacsecTxSaGetActive(p_FmMacsecSecY->h_FmMacsec,
p_FmSecYSc->scId,
p_An)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_GetRxScPhysId(t_Handle h_FmMacsecSecY, t_Handle h_Sc, uint32_t *p_ScPhysId)
{
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(h_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(((t_FmMacsecSecY *)h_FmMacsecSecY)->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!((t_FmMacsecSecY *)h_FmMacsecSecY)->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
#ifdef DISABLE_SANITY_CHECKS
UNUSED(h_FmMacsecSecY);
#endif /* DISABLE_SANITY_CHECKS */
*p_ScPhysId = p_FmSecYSc->scId;
return err;
}
t_Error FM_MACSEC_SECY_GetTxScPhysId(t_Handle h_FmMacsecSecY, uint32_t *p_ScPhysId)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
*p_ScPhysId = p_FmSecYSc->scId;
return err;
}
t_Error FM_MACSEC_SECY_SetException(t_Handle h_FmMacsecSecY, e_FmMacsecExceptions exception, bool enable)
{
UNUSED(h_FmMacsecSecY);UNUSED(exception);UNUSED(enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_SetEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable)
{
UNUSED(h_FmMacsecSecY);UNUSED(event);UNUSED(enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_GetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_RxScGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, t_FmMacsecSecYRxScStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(h_Sc);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_RxSaGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, t_FmMacsecSecYRxSaStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(h_Sc);UNUSED(an);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_TxScGetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYTxScStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_TxSaGetStatistics(t_Handle h_FmMacsecSecY, macsecAN_t an, t_FmMacsecSecYTxSaStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(an);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}

144
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@ -0,0 +1,144 @@
/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec_secy.h
@Description FM MACSEC SecY internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_MACSEC_SECY_H
#define __FM_MACSEC_SECY_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_macsec.h"
/**************************************************************************//**
@Description Exceptions
*//***************************************************************************/
#define FM_MACSEC_SECY_EX_FRAME_DISCARDED 0x80000000
#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MACSEC_SECY_EX_FRAME_DISCARDED: \
bitMask = FM_MACSEC_SECY_EX_FRAME_DISCARDED; break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description Events
*//***************************************************************************/
#define FM_MACSEC_SECY_EV_NEXT_PN 0x80000000
#define GET_EVENT_FLAG(bitMask, event) switch (event){ \
case e_FM_MACSEC_SECY_EV_NEXT_PN: \
bitMask = FM_MACSEC_SECY_EV_NEXT_PN; break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description Defaults
*//***************************************************************************/
#define DEFAULT_exceptions (FM_MACSEC_SECY_EX_FRAME_DISCARDED)
#define DEFAULT_events (FM_MACSEC_SECY_EV_NEXT_PN)
#define DEFAULT_numOfTxSc 1
#define DEFAULT_confidentialityEnable FALSE
#define DEFAULT_confidentialityOffset 0
#define DEFAULT_sciInsertionMode e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_SECTAG
#define DEFAULT_validateFrames e_FM_MACSEC_VALID_FRAME_BEHAVIOR_STRICT
#define DEFAULT_replayEnable FALSE
#define DEFAULT_replayWindow 0
#define DEFAULT_protectFrames TRUE
#define DEFAULT_ptp FALSE
/**************************************************************************//**
@Description General defines
*//***************************************************************************/
#define SECY_AN_FREE_VALUE MAX_NUM_OF_SA_PER_SC
typedef struct {
e_ScSaId saId;
bool active;
union {
t_FmMacsecSecYRxSaStatistics rxSaStatistics;
t_FmMacsecSecYTxSaStatistics txSaStatistics;
};
} t_SecYSa;
typedef struct {
bool inUse;
uint32_t scId;
e_ScType type;
uint8_t numOfSa;
t_SecYSa sa[MAX_NUM_OF_SA_PER_SC];
union {
t_FmMacsecSecYRxScStatistics rxScStatistics;
t_FmMacsecSecYTxScStatistics txScStatistics;
};
} t_SecYSc;
typedef struct {
t_FmMacsecSecYSCParams txScParams; /**< Tx SC Params */
} t_FmMacsecSecYDriverParam;
typedef struct {
t_Handle h_FmMacsec;
bool confidentialityEnable; /**< TRUE - confidentiality protection and integrity protection
FALSE - no confidentiality protection, only integrity protection*/
uint16_t confidentialityOffset; /**< The number of initial octets of each MSDU without confidentiality protection
common values are 0, 30, and 50 */
bool replayProtect; /**< replay protection function mode */
uint32_t replayWindow; /**< the size of the replay window */
e_FmMacsecValidFrameBehavior validateFrames; /**< validation function mode */
e_FmMacsecSciInsertionMode sciInsertionMode;
bool protectFrames;
bool isPointToPoint;
e_FmMacsecSecYCipherSuite cipherSuite; /**< Cipher suite to be used for this SecY */
uint32_t numOfRxSc; /**< Number of receive channels */
uint32_t numOfTxSc; /**< Number of transmit channels */
t_SecYSc *p_RxSc;
t_SecYSc *p_TxSc;
uint32_t events;
uint32_t exceptions;
t_FmMacsecSecYExceptionsCallback *f_Exception; /**< TODO */
t_FmMacsecSecYEventsCallback *f_Event; /**< TODO */
t_Handle h_App;
t_FmMacsecSecYStatistics statistics;
t_FmMacsecSecYDriverParam *p_FmMacsecSecYDriverParam;
} t_FmMacsecSecY;
#endif /* __FM_MACSEC_SECY_H */

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@ -0,0 +1,360 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File crc64.h
@Description brief This file contains the CRC64 Table, and __inline__
functions used for calculating crc.
*//***************************************************************************/
#ifndef __CRC64_H
#define __CRC64_H
#include "std_ext.h"
#define BITS_PER_BYTE 8
#define CRC64_EXPON_ECMA_182 0xC96C5795D7870F42ULL
#define CRC64_DEFAULT_INITVAL 0xFFFFFFFFFFFFFFFFULL
#define CRC64_BYTE_MASK 0xFF
#define CRC64_TABLE_ENTRIES ( 1 << BITS_PER_BYTE )
#define CRC64_ODD_MASK 1
/**
\brief '64 bit crc' Table
*/
struct crc64_t {
uint64_t initial; /**< Initial seed */
uint64_t table[CRC64_TABLE_ENTRIES]; /**< CRC table entries */
};
static struct crc64_t CRC64_ECMA_182 = {
CRC64_DEFAULT_INITVAL,
{
0x0000000000000000ULL,
0xb32e4cbe03a75f6fULL,
0xf4843657a840a05bULL,
0x47aa7ae9abe7ff34ULL,
0x7bd0c384ff8f5e33ULL,
0xc8fe8f3afc28015cULL,
0x8f54f5d357cffe68ULL,
0x3c7ab96d5468a107ULL,
0xf7a18709ff1ebc66ULL,
0x448fcbb7fcb9e309ULL,
0x0325b15e575e1c3dULL,
0xb00bfde054f94352ULL,
0x8c71448d0091e255ULL,
0x3f5f08330336bd3aULL,
0x78f572daa8d1420eULL,
0xcbdb3e64ab761d61ULL,
0x7d9ba13851336649ULL,
0xceb5ed8652943926ULL,
0x891f976ff973c612ULL,
0x3a31dbd1fad4997dULL,
0x064b62bcaebc387aULL,
0xb5652e02ad1b6715ULL,
0xf2cf54eb06fc9821ULL,
0x41e11855055bc74eULL,
0x8a3a2631ae2dda2fULL,
0x39146a8fad8a8540ULL,
0x7ebe1066066d7a74ULL,
0xcd905cd805ca251bULL,
0xf1eae5b551a2841cULL,
0x42c4a90b5205db73ULL,
0x056ed3e2f9e22447ULL,
0xb6409f5cfa457b28ULL,
0xfb374270a266cc92ULL,
0x48190ecea1c193fdULL,
0x0fb374270a266cc9ULL,
0xbc9d3899098133a6ULL,
0x80e781f45de992a1ULL,
0x33c9cd4a5e4ecdceULL,
0x7463b7a3f5a932faULL,
0xc74dfb1df60e6d95ULL,
0x0c96c5795d7870f4ULL,
0xbfb889c75edf2f9bULL,
0xf812f32ef538d0afULL,
0x4b3cbf90f69f8fc0ULL,
0x774606fda2f72ec7ULL,
0xc4684a43a15071a8ULL,
0x83c230aa0ab78e9cULL,
0x30ec7c140910d1f3ULL,
0x86ace348f355aadbULL,
0x3582aff6f0f2f5b4ULL,
0x7228d51f5b150a80ULL,
0xc10699a158b255efULL,
0xfd7c20cc0cdaf4e8ULL,
0x4e526c720f7dab87ULL,
0x09f8169ba49a54b3ULL,
0xbad65a25a73d0bdcULL,
0x710d64410c4b16bdULL,
0xc22328ff0fec49d2ULL,
0x85895216a40bb6e6ULL,
0x36a71ea8a7ace989ULL,
0x0adda7c5f3c4488eULL,
0xb9f3eb7bf06317e1ULL,
0xfe5991925b84e8d5ULL,
0x4d77dd2c5823b7baULL,
0x64b62bcaebc387a1ULL,
0xd7986774e864d8ceULL,
0x90321d9d438327faULL,
0x231c512340247895ULL,
0x1f66e84e144cd992ULL,
0xac48a4f017eb86fdULL,
0xebe2de19bc0c79c9ULL,
0x58cc92a7bfab26a6ULL,
0x9317acc314dd3bc7ULL,
0x2039e07d177a64a8ULL,
0x67939a94bc9d9b9cULL,
0xd4bdd62abf3ac4f3ULL,
0xe8c76f47eb5265f4ULL,
0x5be923f9e8f53a9bULL,
0x1c4359104312c5afULL,
0xaf6d15ae40b59ac0ULL,
0x192d8af2baf0e1e8ULL,
0xaa03c64cb957be87ULL,
0xeda9bca512b041b3ULL,
0x5e87f01b11171edcULL,
0x62fd4976457fbfdbULL,
0xd1d305c846d8e0b4ULL,
0x96797f21ed3f1f80ULL,
0x2557339fee9840efULL,
0xee8c0dfb45ee5d8eULL,
0x5da24145464902e1ULL,
0x1a083bacedaefdd5ULL,
0xa9267712ee09a2baULL,
0x955cce7fba6103bdULL,
0x267282c1b9c65cd2ULL,
0x61d8f8281221a3e6ULL,
0xd2f6b4961186fc89ULL,
0x9f8169ba49a54b33ULL,
0x2caf25044a02145cULL,
0x6b055fede1e5eb68ULL,
0xd82b1353e242b407ULL,
0xe451aa3eb62a1500ULL,
0x577fe680b58d4a6fULL,
0x10d59c691e6ab55bULL,
0xa3fbd0d71dcdea34ULL,
0x6820eeb3b6bbf755ULL,
0xdb0ea20db51ca83aULL,
0x9ca4d8e41efb570eULL,
0x2f8a945a1d5c0861ULL,
0x13f02d374934a966ULL,
0xa0de61894a93f609ULL,
0xe7741b60e174093dULL,
0x545a57dee2d35652ULL,
0xe21ac88218962d7aULL,
0x5134843c1b317215ULL,
0x169efed5b0d68d21ULL,
0xa5b0b26bb371d24eULL,
0x99ca0b06e7197349ULL,
0x2ae447b8e4be2c26ULL,
0x6d4e3d514f59d312ULL,
0xde6071ef4cfe8c7dULL,
0x15bb4f8be788911cULL,
0xa6950335e42fce73ULL,
0xe13f79dc4fc83147ULL,
0x521135624c6f6e28ULL,
0x6e6b8c0f1807cf2fULL,
0xdd45c0b11ba09040ULL,
0x9aefba58b0476f74ULL,
0x29c1f6e6b3e0301bULL,
0xc96c5795d7870f42ULL,
0x7a421b2bd420502dULL,
0x3de861c27fc7af19ULL,
0x8ec62d7c7c60f076ULL,
0xb2bc941128085171ULL,
0x0192d8af2baf0e1eULL,
0x4638a2468048f12aULL,
0xf516eef883efae45ULL,
0x3ecdd09c2899b324ULL,
0x8de39c222b3eec4bULL,
0xca49e6cb80d9137fULL,
0x7967aa75837e4c10ULL,
0x451d1318d716ed17ULL,
0xf6335fa6d4b1b278ULL,
0xb199254f7f564d4cULL,
0x02b769f17cf11223ULL,
0xb4f7f6ad86b4690bULL,
0x07d9ba1385133664ULL,
0x4073c0fa2ef4c950ULL,
0xf35d8c442d53963fULL,
0xcf273529793b3738ULL,
0x7c0979977a9c6857ULL,
0x3ba3037ed17b9763ULL,
0x888d4fc0d2dcc80cULL,
0x435671a479aad56dULL,
0xf0783d1a7a0d8a02ULL,
0xb7d247f3d1ea7536ULL,
0x04fc0b4dd24d2a59ULL,
0x3886b22086258b5eULL,
0x8ba8fe9e8582d431ULL,
0xcc0284772e652b05ULL,
0x7f2cc8c92dc2746aULL,
0x325b15e575e1c3d0ULL,
0x8175595b76469cbfULL,
0xc6df23b2dda1638bULL,
0x75f16f0cde063ce4ULL,
0x498bd6618a6e9de3ULL,
0xfaa59adf89c9c28cULL,
0xbd0fe036222e3db8ULL,
0x0e21ac88218962d7ULL,
0xc5fa92ec8aff7fb6ULL,
0x76d4de52895820d9ULL,
0x317ea4bb22bfdfedULL,
0x8250e80521188082ULL,
0xbe2a516875702185ULL,
0x0d041dd676d77eeaULL,
0x4aae673fdd3081deULL,
0xf9802b81de97deb1ULL,
0x4fc0b4dd24d2a599ULL,
0xfceef8632775faf6ULL,
0xbb44828a8c9205c2ULL,
0x086ace348f355aadULL,
0x34107759db5dfbaaULL,
0x873e3be7d8faa4c5ULL,
0xc094410e731d5bf1ULL,
0x73ba0db070ba049eULL,
0xb86133d4dbcc19ffULL,
0x0b4f7f6ad86b4690ULL,
0x4ce50583738cb9a4ULL,
0xffcb493d702be6cbULL,
0xc3b1f050244347ccULL,
0x709fbcee27e418a3ULL,
0x3735c6078c03e797ULL,
0x841b8ab98fa4b8f8ULL,
0xadda7c5f3c4488e3ULL,
0x1ef430e13fe3d78cULL,
0x595e4a08940428b8ULL,
0xea7006b697a377d7ULL,
0xd60abfdbc3cbd6d0ULL,
0x6524f365c06c89bfULL,
0x228e898c6b8b768bULL,
0x91a0c532682c29e4ULL,
0x5a7bfb56c35a3485ULL,
0xe955b7e8c0fd6beaULL,
0xaeffcd016b1a94deULL,
0x1dd181bf68bdcbb1ULL,
0x21ab38d23cd56ab6ULL,
0x9285746c3f7235d9ULL,
0xd52f0e859495caedULL,
0x6601423b97329582ULL,
0xd041dd676d77eeaaULL,
0x636f91d96ed0b1c5ULL,
0x24c5eb30c5374ef1ULL,
0x97eba78ec690119eULL,
0xab911ee392f8b099ULL,
0x18bf525d915feff6ULL,
0x5f1528b43ab810c2ULL,
0xec3b640a391f4fadULL,
0x27e05a6e926952ccULL,
0x94ce16d091ce0da3ULL,
0xd3646c393a29f297ULL,
0x604a2087398eadf8ULL,
0x5c3099ea6de60cffULL,
0xef1ed5546e415390ULL,
0xa8b4afbdc5a6aca4ULL,
0x1b9ae303c601f3cbULL,
0x56ed3e2f9e224471ULL,
0xe5c372919d851b1eULL,
0xa26908783662e42aULL,
0x114744c635c5bb45ULL,
0x2d3dfdab61ad1a42ULL,
0x9e13b115620a452dULL,
0xd9b9cbfcc9edba19ULL,
0x6a978742ca4ae576ULL,
0xa14cb926613cf817ULL,
0x1262f598629ba778ULL,
0x55c88f71c97c584cULL,
0xe6e6c3cfcadb0723ULL,
0xda9c7aa29eb3a624ULL,
0x69b2361c9d14f94bULL,
0x2e184cf536f3067fULL,
0x9d36004b35545910ULL,
0x2b769f17cf112238ULL,
0x9858d3a9ccb67d57ULL,
0xdff2a94067518263ULL,
0x6cdce5fe64f6dd0cULL,
0x50a65c93309e7c0bULL,
0xe388102d33392364ULL,
0xa4226ac498dedc50ULL,
0x170c267a9b79833fULL,
0xdcd7181e300f9e5eULL,
0x6ff954a033a8c131ULL,
0x28532e49984f3e05ULL,
0x9b7d62f79be8616aULL,
0xa707db9acf80c06dULL,
0x14299724cc279f02ULL,
0x5383edcd67c06036ULL,
0xe0ada17364673f59ULL
}
};
/**
\brief Initializes the crc seed
*/
static __inline__ uint64_t crc64_init(void)
{
return CRC64_ECMA_182.initial;
}
/**
\brief Computes 64 bit the crc
\param[in] data Pointer to the Data in the frame
\param[in] len Length of the Data
\param[in] crc seed
\return calculated crc
*/
static __inline__ uint64_t crc64_compute(void const *data,
uint32_t len,
uint64_t seed)
{
uint32_t i;
uint64_t crc = seed;
uint8_t *bdata = (uint8_t *) data;
for (i = 0; i < len; i++)
crc =
CRC64_ECMA_182.
table[(crc ^ *bdata++) & CRC64_BYTE_MASK] ^ (crc >> 8);
return crc;
}
#endif /* __CRC64_H */

8734
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_cc.c
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257
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_cc.h
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@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_cc.h
@ -49,6 +50,8 @@
/* Coarse classification defines */
/***********************************************************************/
#define CC_MAX_NUM_OF_KEYS (FM_PCD_MAX_NUM_OF_KEYS + 1)
#define CC_PC_FF_MACDST 0x00
#define CC_PC_FF_MACSRC 0x01
#define CC_PC_FF_ETYPE 0x02
@ -81,6 +84,9 @@
#define CC_PC_FF_IPV6SRC1 0x10
#define CC_PC_FF_IPV6SRC2 0x1e
#define CC_PC_FF_IPV6HOP_LIMIT 0x2a
#define CC_PC_FF_IPPID 0x24
#define CC_PC_FF_IPDSCP 0x76
#define CC_PC_FF_GREPTYPE 0x11
#define CC_PC_FF_MINENCAP_PTYPE 0x12
@ -101,6 +107,7 @@
#define CC_PC_GENERIC_WITH_MASK 0x28
#define CC_PC_GENERIC_IC_GMASK 0x2B
#define CC_PC_GENERIC_IC_HASH_INDEXED 0x2C
#define CC_PC_GENERIC_IC_AGING_MASK 0x2D
#define CC_PR_OFFSET 0x25
#define CC_PR_WITHOUT_OFFSET 0x26
@ -126,9 +133,10 @@
#define CC_SIZE_ILLEGAL 0
#define FM_PCD_CC_KEYS_MATCH_TABLE_ALIGN 16
#define FM_PCD_CC_AD_TABLE_ALIGN 256
#define FM_PCD_CC_AD_TABLE_ALIGN 16
#define FM_PCD_CC_AD_ENTRY_SIZE 16
#define FM_PCD_CC_NUM_OF_KEYS 255
#define FM_PCD_CC_TREE_ADDR_ALIGN 256
#define FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE 0x00000000
#define FM_PCD_AD_RESULT_DATA_FLOW_TYPE 0x80000000
@ -137,17 +145,37 @@
#define FM_PCD_AD_RESULT_NADEN 0x20000000
#define FM_PCD_AD_RESULT_STATISTICS_EN 0x40000000
#define FM_PCD_AD_CONT_LOOKUP_TYPE 0x40000000
#define FM_PCD_AD_CONT_LOOKUP_LCL_MASK 0x00800000
#define FM_PCD_AD_STATS_TYPE 0x40000000
#define FM_PCD_AD_STATS_FLR_ADDR_MASK 0x00FFFFFF
#define FM_PCD_AD_STATS_COUNTERS_ADDR_MASK 0x00FFFFFF
#define FM_PCD_AD_STATS_NEXT_ACTION_MASK 0xFFFF0000
#define FM_PCD_AD_STATS_NEXT_ACTION_SHIFT 12
#define FM_PCD_AD_STATS_NAD_EN 0x00008000
#define FM_PCD_AD_STATS_OP_CODE 0x00000036
#define FM_PCD_AD_STATS_FLR_EN 0x00004000
#define FM_PCD_AD_STATS_COND_EN 0x00002000
#define FM_PCD_AD_BYPASS_TYPE 0xc0000000
#define FM_PCD_AD_TYPE_MASK 0xc0000000
#define FM_PCD_AD_OPCODE_MASK 0x0000000f
#define FM_PCD_AD_PROFILEID_FOR_CNTRL_SHIFT 16
#if (DPAA_VERSION >= 11)
#define FM_PCD_AD_RESULT_VSP_SHIFT 24
#define FM_PCD_AD_RESULT_NO_OM_VSPE 0x02000000
#define FM_PCD_AD_RESULT_VSP_MASK 0x3f
#define FM_PCD_AD_NCSPFQIDM_MASK 0x80000000
#endif /* (DPAA_VERSION >= 11) */
#define GLBL_MASK_FOR_HASH_INDEXED 0xfff00000
#define CC_GLBL_MASK_SIZE 4
#define CC_AGING_MASK_SIZE 4
typedef uint32_t ccPrivateInfo_t; /**< private info of CC: */
@ -157,156 +185,215 @@ typedef uint32_t ccPrivateInfo_t; /**< private info of CC: */
#define CC_PRIVATE_INFO_IC_KEY_EXACT_MATCH 0x20000000
#define CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP 0x10000000
#define CC_BUILD_AGING_MASK(numOfKeys) ((((1LL << ((numOfKeys) + 1)) - 1)) << (31 - (numOfKeys)))
/***********************************************************************/
/* Memory map */
/***********************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct {
typedef struct
{
volatile uint32_t fqid;
volatile uint32_t plcrProfile;
volatile uint32_t nia;
volatile uint32_t res;
} _PackedType t_AdOfTypeResult;
volatile uint32_t res;
} t_AdOfTypeResult;
typedef _Packed struct {
typedef struct
{
volatile uint32_t ccAdBase;
volatile uint32_t matchTblPtr;
volatile uint32_t pcAndOffsets;
volatile uint32_t gmask;
} _PackedType t_AdOfTypeContLookup;
} t_AdOfTypeContLookup;
typedef _Packed union {
typedef struct
{
volatile uint32_t profileTableAddr;
volatile uint32_t reserved;
volatile uint32_t nextActionIndx;
volatile uint32_t statsTableAddr;
} t_AdOfTypeStats;
typedef union
{
volatile t_AdOfTypeResult adResult;
volatile t_AdOfTypeContLookup adContLookup;
} _PackedType t_Ad;
} t_Ad;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/***********************************************************************/
/* Driver's internal structures */
/* Driver's internal structures */
/***********************************************************************/
typedef enum e_ModifyState {
e_MODIFY_STATE_ADD = 0,
e_MODIFY_STATE_REMOVE,
e_MODIFY_STATE_CHANGE
} e_ModifyState;
typedef struct t_FmPcdStatsObj
{
t_Handle h_StatsAd;
t_Handle h_StatsCounters;
t_List node;
} t_FmPcdStatsObj;
typedef struct
{
uint8_t key[FM_PCD_MAX_SIZE_OF_KEY];
uint8_t mask[FM_PCD_MAX_SIZE_OF_KEY];
typedef struct {
t_FmPcdCcNextEngineParams nextEngineParams;
uint32_t requiredAction;
uint32_t shadowAction;
} t_FmPcdCcNextEngineAndRequiredActionParams;
typedef struct {
t_Handle p_Ad;
e_FmPcdEngine fmPcdEngine;
bool adAllocated;
bool isTree;
t_FmPcdStatsObj *p_StatsObj;
uint32_t myInfo;
t_List *h_CcNextNodesLst;
t_Handle h_AdditionalInfo;
t_Handle h_Node;
} t_FmPcdCcKeyAndNextEngineParams;
typedef struct
{
t_Handle p_Ad;
e_FmPcdEngine fmPcdEngine;
bool adAllocated;
bool isTree;
uint32_t myInfo;
t_List *h_CcNextNodesLst;
t_Handle h_AdditionalInfo;
t_Handle h_Node;
} t_FmPcdModifyCcAdditionalParams;
typedef struct {
t_Handle p_AdTableNew;
t_Handle p_KeysMatchTableNew;
t_Handle p_AdTableOld;
t_Handle p_KeysMatchTableOld;
uint16_t numOfKeys;
t_Handle h_CurrentNode;
uint16_t keyIndex;
t_Handle h_NodeForAdd;
t_Handle h_NodeForRmv;
t_Handle h_ManipForRmv;
bool tree;
typedef struct
{
t_Handle p_AdTableNew;
t_Handle p_KeysMatchTableNew;
t_Handle p_AdTableOld;
t_Handle p_KeysMatchTableOld;
uint16_t numOfKeys;
t_Handle h_CurrentNode;
uint16_t savedKeyIndex;
t_Handle h_NodeForAdd;
t_Handle h_NodeForRmv;
t_Handle h_ManipForRmv;
t_Handle h_ManipForAdd;
t_FmPcdStatsObj *p_StatsObjForRmv;
#if (DPAA_VERSION >= 11)
t_Handle h_FrmReplicForAdd;
t_Handle h_FrmReplicForRmv;
#endif /* (DPAA_VERSION >= 11) */
bool tree;
t_FmPcdCcNextEngineAndRequiredActionParams nextEngineAndRequiredAction[256];
t_FmPcdCcKeyAndNextEngineParams keyAndNextEngineParams[CC_MAX_NUM_OF_KEYS];
} t_FmPcdModifyCcKeyAdditionalParams;
typedef struct {
t_Handle h_Manip;
t_Handle h_CcNode;
typedef struct
{
t_Handle h_Manip;
t_Handle h_CcNode;
} t_CcNextEngineInfo;
typedef struct {
uint16_t numOfKeys;
bool glblMaskUpdated;
t_Handle p_GlblMask;
bool lclMask;
uint8_t parseCode;
uint8_t offset;
uint8_t prsArrayOffset;
bool ctrlFlow;
uint8_t owners;
typedef struct
{
uint16_t numOfKeys;
uint16_t maxNumOfKeys;
uint8_t ccKeySizeAccExtraction;
uint8_t sizeOfExtraction;
uint8_t glblMaskSize;
bool maskSupport;
uint32_t keysMatchTableMaxSize;
t_Handle h_KeysMatchTable;
t_Handle h_AdTable;
e_FmPcdCcStatsMode statisticsMode;
uint32_t numOfStatsFLRs;
uint32_t countersArraySize;
t_List ccPrevNodesLst;
bool isHashBucket; /**< Valid for match table node that is a bucket of a hash table only */
t_Handle h_MissStatsCounters; /**< Valid for hash table node and match table that is a bucket;
Holds the statistics counters allocated by the hash table and
are shared by all hash table buckets; */
t_Handle h_PrivMissStatsCounters; /**< Valid for match table node that is a bucket of a hash table only;
Holds the statistics counters that were allocated for this node
and replaced by the shared counters (allocated by the hash table); */
bool statsEnForMiss; /**< Valid for hash table node only; TRUE is statistics are currently
enabled for hash 'miss', FALSE otherwise; This parameter effects the
returned statistics count to user, statistics AD always present for 'miss'
for all hash buckets; */
bool glblMaskUpdated;
t_Handle p_GlblMask;
bool lclMask;
uint8_t parseCode;
uint8_t offset;
uint8_t prsArrayOffset;
bool ctrlFlow;
uint16_t owners;
t_List ccTreeIdLst;
t_List ccTreesLst;
uint8_t ccKeySizeAccExtraction;
uint8_t sizeOfExtraction;
uint8_t glblMaskSize;
t_Handle h_FmPcd;
uint32_t shadowAction;
bool modifiedState;
uint8_t userSizeOfExtraction;
t_Handle h_KeysMatchTable;
t_Handle h_AdTable;
t_Handle h_StatsAds;
t_Handle h_TmpAd;
t_Handle h_Ad;
t_Handle h_StatsFLRs;
t_FmPcdCcNextEngineAndRequiredActionParams nextEngineAndRequiredAction[256];
t_List availableStatsLst;
t_List ccPrevNodesLst;
t_List ccTreeIdLst;
t_List ccTreesLst;
t_Handle h_FmPcd;
uint32_t shadowAction;
uint8_t userSizeOfExtraction;
uint8_t userOffset;
uint8_t kgHashShift; /* used in hash-table */
t_Handle h_Spinlock;
t_FmPcdCcKeyAndNextEngineParams keyAndNextEngineParams[CC_MAX_NUM_OF_KEYS];
} t_FmPcdCcNode;
typedef struct {
typedef struct
{
t_FmPcdCcNode *p_FmPcdCcNode;
bool occupied;
uint8_t owners;
uint16_t owners;
volatile bool lock;
} t_FmPcdCcNodeArray;
typedef struct {
typedef struct
{
uint8_t numOfEntriesInGroup;
uint32_t totalBitsMask;
uint8_t baseGroupEntry;
} t_FmPcdCcGroupParam;
typedef struct {
typedef struct
{
t_Handle h_FmPcd;
uint8_t netEnvId;
uintptr_t ccTreeBaseAddr;
uint8_t numOfGrps;
t_FmPcdCcGroupParam fmPcdGroupParam[FM_PCD_MAX_NUM_OF_CC_GROUPS];
t_List fmPortsLst;
volatile bool lock;
t_FmPcdLock *p_Lock;
uint8_t numOfEntries;
uint8_t owners;
t_Handle *fmPcdCcSavedManipParams[256];
uint16_t owners;
t_Handle h_FmPcdCcSavedManipParams;
bool modifiedState;
uint32_t requiredAction;
t_FmPcdCcNextEngineAndRequiredActionParams nextEngineAndRequiredAction[FM_PCD_MAX_NUM_OF_KEYS];
t_Handle h_IpReassemblyManip;
t_Handle h_CapwapReassemblyManip;
t_FmPcdCcKeyAndNextEngineParams keyAndNextEngineParams[FM_PCD_MAX_NUM_OF_CC_GROUPS];
} t_FmPcdCcTree;
typedef struct {
t_FmPcdCcTree *p_FmPcdCcTree;
bool occupied;
uint8_t owners;
volatile bool lock;
} t_FmPcdCcTreeArray;
bool FmPcdManipIsManipNode(t_Handle h_Ad);
t_Error FmPcdCcNodeTreeTryLock(t_Handle h_FmPcd,t_Handle h_FmPcdCcNode, t_List *p_List);
void FmPcdCcNodeTreeReleaseLock(t_Handle h_FmPcd, t_List *p_List);
t_Error FmPcdUpdateCcShadow (t_FmPcd *p_FmPcd, uint32_t size, uint32_t align);
#endif /* __FM_CC_H */

3667
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_kg.c
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sys/contrib/ncsw/Peripherals/FM/Pcd/fm_kg.h Normal file
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@ -0,0 +1,206 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_kg.h
@Description FM KG private header
*//***************************************************************************/
#ifndef __FM_KG_H
#define __FM_KG_H
#include "std_ext.h"
/***********************************************************************/
/* Keygen defines */
/***********************************************************************/
/* maskes */
#if (DPAA_VERSION >= 11)
#define KG_SCH_VSP_SHIFT_MASK 0x0003f000
#define KG_SCH_OM_VSPE 0x00000001
#define KG_SCH_VSP_NO_KSP_EN 0x80000000
#define MAX_SP_SHIFT 23
#define KG_SCH_VSP_MASK_SHIFT 12
#define KG_SCH_VSP_SHIFT 24
#endif /* (DPAA_VERSION >= 11) */
typedef uint32_t t_KnownFieldsMasks;
#define KG_SCH_KN_PORT_ID 0x80000000
#define KG_SCH_KN_MACDST 0x40000000
#define KG_SCH_KN_MACSRC 0x20000000
#define KG_SCH_KN_TCI1 0x10000000
#define KG_SCH_KN_TCI2 0x08000000
#define KG_SCH_KN_ETYPE 0x04000000
#define KG_SCH_KN_PPPSID 0x02000000
#define KG_SCH_KN_PPPID 0x01000000
#define KG_SCH_KN_MPLS1 0x00800000
#define KG_SCH_KN_MPLS2 0x00400000
#define KG_SCH_KN_MPLS_LAST 0x00200000
#define KG_SCH_KN_IPSRC1 0x00100000
#define KG_SCH_KN_IPDST1 0x00080000
#define KG_SCH_KN_PTYPE1 0x00040000
#define KG_SCH_KN_IPTOS_TC1 0x00020000
#define KG_SCH_KN_IPV6FL1 0x00010000
#define KG_SCH_KN_IPSRC2 0x00008000
#define KG_SCH_KN_IPDST2 0x00004000
#define KG_SCH_KN_PTYPE2 0x00002000
#define KG_SCH_KN_IPTOS_TC2 0x00001000
#define KG_SCH_KN_IPV6FL2 0x00000800
#define KG_SCH_KN_GREPTYPE 0x00000400
#define KG_SCH_KN_IPSEC_SPI 0x00000200
#define KG_SCH_KN_IPSEC_NH 0x00000100
#define KG_SCH_KN_IPPID 0x00000080
#define KG_SCH_KN_L4PSRC 0x00000004
#define KG_SCH_KN_L4PDST 0x00000002
#define KG_SCH_KN_TFLG 0x00000001
typedef uint8_t t_GenericCodes;
#define KG_SCH_GEN_SHIM1 0x70
#define KG_SCH_GEN_DEFAULT 0x10
#define KG_SCH_GEN_PARSE_RESULT_N_FQID 0x20
#define KG_SCH_GEN_START_OF_FRM 0x40
#define KG_SCH_GEN_SHIM2 0x71
#define KG_SCH_GEN_IP_PID_NO_V 0x72
#define KG_SCH_GEN_ETH 0x03
#define KG_SCH_GEN_ETH_NO_V 0x73
#define KG_SCH_GEN_SNAP 0x04
#define KG_SCH_GEN_SNAP_NO_V 0x74
#define KG_SCH_GEN_VLAN1 0x05
#define KG_SCH_GEN_VLAN1_NO_V 0x75
#define KG_SCH_GEN_VLAN2 0x06
#define KG_SCH_GEN_VLAN2_NO_V 0x76
#define KG_SCH_GEN_ETH_TYPE 0x07
#define KG_SCH_GEN_ETH_TYPE_NO_V 0x77
#define KG_SCH_GEN_PPP 0x08
#define KG_SCH_GEN_PPP_NO_V 0x78
#define KG_SCH_GEN_MPLS1 0x09
#define KG_SCH_GEN_MPLS2 0x19
#define KG_SCH_GEN_MPLS3 0x29
#define KG_SCH_GEN_MPLS1_NO_V 0x79
#define KG_SCH_GEN_MPLS_LAST 0x0a
#define KG_SCH_GEN_MPLS_LAST_NO_V 0x7a
#define KG_SCH_GEN_IPV4 0x0b
#define KG_SCH_GEN_IPV6 0x1b
#define KG_SCH_GEN_L3_NO_V 0x7b
#define KG_SCH_GEN_IPV4_TUNNELED 0x0c
#define KG_SCH_GEN_IPV6_TUNNELED 0x1c
#define KG_SCH_GEN_MIN_ENCAP 0x2c
#define KG_SCH_GEN_IP2_NO_V 0x7c
#define KG_SCH_GEN_GRE 0x0d
#define KG_SCH_GEN_GRE_NO_V 0x7d
#define KG_SCH_GEN_TCP 0x0e
#define KG_SCH_GEN_UDP 0x1e
#define KG_SCH_GEN_IPSEC_AH 0x2e
#define KG_SCH_GEN_SCTP 0x3e
#define KG_SCH_GEN_DCCP 0x4e
#define KG_SCH_GEN_IPSEC_ESP 0x6e
#define KG_SCH_GEN_L4_NO_V 0x7e
#define KG_SCH_GEN_NEXTHDR 0x7f
/* shifts */
#define KG_SCH_PP_SHIFT_HIGH_SHIFT 27
#define KG_SCH_PP_SHIFT_LOW_SHIFT 12
#define KG_SCH_PP_MASK_SHIFT 16
#define KG_SCH_MODE_CCOBASE_SHIFT 24
#define KG_SCH_DEF_MAC_ADDR_SHIFT 30
#define KG_SCH_DEF_TCI_SHIFT 28
#define KG_SCH_DEF_ENET_TYPE_SHIFT 26
#define KG_SCH_DEF_PPP_SESSION_ID_SHIFT 24
#define KG_SCH_DEF_PPP_PROTOCOL_ID_SHIFT 22
#define KG_SCH_DEF_MPLS_LABEL_SHIFT 20
#define KG_SCH_DEF_IP_ADDR_SHIFT 18
#define KG_SCH_DEF_PROTOCOL_TYPE_SHIFT 16
#define KG_SCH_DEF_IP_TOS_TC_SHIFT 14
#define KG_SCH_DEF_IPV6_FLOW_LABEL_SHIFT 12
#define KG_SCH_DEF_IPSEC_SPI_SHIFT 10
#define KG_SCH_DEF_L4_PORT_SHIFT 8
#define KG_SCH_DEF_TCP_FLAG_SHIFT 6
#define KG_SCH_HASH_CONFIG_SHIFT_SHIFT 24
#define KG_SCH_GEN_MASK_SHIFT 16
#define KG_SCH_GEN_HT_SHIFT 8
#define KG_SCH_GEN_SIZE_SHIFT 24
#define KG_SCH_GEN_DEF_SHIFT 29
#define FM_PCD_KG_KGAR_NUM_SHIFT 16
/* others */
#define NUM_OF_SW_DEFAULTS 3
#define MAX_PP_SHIFT 23
#define MAX_KG_SCH_SIZE 16
#define MASK_FOR_GENERIC_BASE_ID 0x20
#define MAX_HASH_SHIFT 40
#define MAX_KG_SCH_FQID_BIT_OFFSET 31
#define MAX_KG_SCH_PP_BIT_OFFSET 15
#define MAX_DIST_FQID_SHIFT 23
#define GET_MASK_SEL_SHIFT(shift,i) \
switch (i) { \
case (0):shift = 26;break; \
case (1):shift = 20;break; \
case (2):shift = 10;break; \
case (3):shift = 4;break; \
default: \
RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); \
}
#define GET_MASK_OFFSET_SHIFT(shift,i) \
switch (i) { \
case (0):shift = 16;break; \
case (1):shift = 0;break; \
case (2):shift = 28;break; \
case (3):shift = 24;break; \
default: \
RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); \
}
#define GET_MASK_SHIFT(shift,i) \
switch (i) { \
case (0):shift = 24;break; \
case (1):shift = 16;break; \
case (2):shift = 8;break; \
case (3):shift = 0;break; \
default: \
RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); \
}
/***********************************************************************/
/* Keygen defines */
/***********************************************************************/
#define KG_DOUBLE_MEANING_REGS_OFFSET 0x100
#define NO_VALIDATION 0x70
#define KG_ACTION_REG_TO 1024
#define KG_MAX_PROFILE 255
#define SCHEME_ALWAYS_DIRECT 0xFFFFFFFF
#endif /* __FM_KG_H */

6526
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_manip.c
View File

File diff suppressed because it is too large Load Diff

477
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_manip.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_manip.h
@ -49,30 +50,46 @@
/* Header manipulations defines */
/***********************************************************************/
#define NUM_OF_SCRATCH_POOL_BUFFERS 1000 /*TODO - Change it!!*/
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
#define HMAN_OC_RMV_N_OR_INSRT_INT_FRM_HDR 0x2e
#define HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER 0x31
#define HMAN_OC_CAPWAP_FRAGMENTATION 0x33
#define HMAN_OC_IPSEC 0x34
#define HMAN_OC_IP_FRAGMENTATION 0x74
#define HMAN_OC_IP_REASSEMBLY 0xB4
#define HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX 0x2f
#define HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST 0x30
#define HMAN_OC_CAPWAP_REASSEMBLY 0x11 /* dummy */
#define HMAN_OC_CAPWAP_INDEXED_STATS 0x32 /* dummy */
#define HMAN_OC_CAPWAP_FRAGMENTATION 0x33
#else
#define HMAN_OC_CAPWAP_MANIP 0x2F
#define HMAN_OC_CAPWAP_FRAG_CHECK 0x2E
#define HMAN_OC_CAPWAP_FRAGMENTATION 0x33
#define HMAN_OC_CAPWAP_REASSEMBLY 0x30
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
#define HMAN_OC_IP_MANIP 0x34
#define HMAN_OC_IP_FRAGMENTATION 0x74
#define HMAN_OC_IP_REASSEMBLY 0xB4
#define HMAN_OC_IPSEC_MANIP 0xF4
#define HMAN_OC 0x35
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
#define HMAN_RMV_HDR 0x80000000
#define HMAN_INSRT_INT_FRM_HDR 0x40000000
#define UDP_UDPHECKSUM_FIELD_OFFSET_FROM_UDP 6
#define UDP_UDPCHECKSUM_FIELD_SIZE 2
#define UDP_CHECKSUM_FIELD_OFFSET_FROM_UDP 6
#define UDP_CHECKSUM_FIELD_SIZE 2
#define UDP_LENGTH_FIELD_OFFSET_FROM_UDP 4
#define IP_DSCECN_FIELD_OFFSET_FROM_IP 1
#define IP_TOTALLENGTH_FIELD_OFFSET_FROM_IP 2
#define IP_HDRCHECKSUM_FIELD_OFFSET_FROM_IP 10
#define IPv4_DSCECN_FIELD_OFFSET_FROM_IP 1
#define IPv4_TOTALLENGTH_FIELD_OFFSET_FROM_IP 2
#define IPv4_HDRCHECKSUM_FIELD_OFFSET_FROM_IP 10
#define VLAN_TAG_FIELD_OFFSET_FROM_ETH 12
#define IP_ID_FIELD_OFFSET_FROM_IP 4
#define IPv4_ID_FIELD_OFFSET_FROM_IP 4
#define FM_PCD_MANIP_CAPWAP_REASM_TABLE_SIZE 80
#define IPv6_PAYLOAD_LENGTH_OFFSET_FROM_IP 4
#define IPv6_NEXT_HEADER_OFFSET_FROM_IP 6
#define FM_PCD_MANIP_CAPWAP_REASM_TABLE_SIZE 0x80
#define FM_PCD_MANIP_CAPWAP_REASM_TABLE_ALIGN 8
#define FM_PCD_MANIP_CAPWAP_REASM_RFD_SIZE 32
#define FM_PCD_MANIP_CAPWAP_REASM_AUTO_LEARNING_HASH_ENTRY_SIZE 4
@ -89,28 +106,219 @@
#define FM_PCD_MANIP_INDEXED_STATS_ENTRY_SIZE 4
#define FM_PCD_MANIP_INDEXED_STATS_CNIA 0x20000000
#define FM_PCD_MANIP_INDEXED_STATS_DPD 0x10000000
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
#define FM_PCD_MANIP_IPSEC_CALC_UDP_LENGTH 0x01000000
#define FM_PCD_MANIP_IPSEC_CNIA 0x20000000
#if (DPAA_VERSION >= 11)
#define FM_PCD_MANIP_CAPWAP_DTLS 0x00040000
#define FM_PCD_MANIP_CAPWAP_NADEN 0x20000000
#define e_FM_MANIP_CAPWAP_INDX 0
#define FM_PCD_MANIP_CAPWAP_FRAG_CHECK_MTU_SHIFT 16
#define FM_PCD_MANIP_CAPWAP_FRAG_CHECK_NO_FRAGMENTATION 0xFFFF0000
#define FM_PCD_MANIP_CAPWAP_FRAG_CHECK_CNIA 0x20000000
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
#define FM_PCD_MANIP_IP_REASM_TABLE_SIZE 0x40
#define FM_PCD_MANIP_IP_REASM_TABLE_ALIGN 8
#define FM_PCD_MANIP_CAPWAP_FRAG_COMPRESS_EN 0x04000000
#define FM_PCD_MANIP_CAPWAP_FRAG_SCRATCH_BPID 24
#define FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_EN 0x08000000
#define FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_MASK 0xFF000000
#define FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_SHIFT 24
#endif /* (DPAA_VERSION >= 11) */
#define FM_PCD_MANIP_REASM_TABLE_SIZE 0x40
#define FM_PCD_MANIP_REASM_TABLE_ALIGN 8
#define FM_PCD_MANIP_REASM_COMMON_PARAM_TABLE_SIZE 64
#define FM_PCD_MANIP_REASM_COMMON_PARAM_TABLE_ALIGN 8
#define FM_PCD_MANIP_REASM_TIME_OUT_BETWEEN_FRAMES 0x80000000
#define FM_PCD_MANIP_REASM_COUPLING_ENABLE 0x40000000
#define FM_PCD_MANIP_REASM_COUPLING_MASK 0xFF000000
#define FM_PCD_MANIP_REASM_COUPLING_SHIFT 24
#define FM_PCD_MANIP_REASM_LIODN_MASK 0x0000003F
#define FM_PCD_MANIP_REASM_LIODN_SHIFT 56
#define FM_PCD_MANIP_REASM_ELIODN_MASK 0x000003c0
#define FM_PCD_MANIP_REASM_ELIODN_SHIFT 38
#define FM_PCD_MANIP_REASM_COMMON_INT_BUFFER_IDX_MASK 0x000000FF
#define FM_PCD_MANIP_REASM_COMMON_INT_BUFFER_IDX_SHIFT 24
#define FM_PCD_MANIP_REASM_TIMEOUT_THREAD_THRESH 1024
#define FM_PCD_MANIP_IP_MTU_SHIFT 16
#define FM_PCD_MANIP_IP_NO_FRAGMENTATION 0xFFFF0000
#define FM_PCD_MANIP_IP_CNIA 0x20000000
#define FM_PCD_MANIP_IP_FRAG_DF_SHIFT 28
#define FM_PCD_MANIP_IP_FRAG_SCRATCH_BPID 24
#define FM_PCD_MANIP_IP_FRAG_SG_BDID_EN 0x08000000
#define FM_PCD_MANIP_IP_FRAG_SG_BDID_MASK 0xFF000000
#define FM_PCD_MANIP_IP_FRAG_SG_BDID_SHIFT 24
#define FM_PCD_MANIP_IPSEC_DEC 0x10000000
#define FM_PCD_MANIP_IPSEC_VIPV_EN 0x08000000
#define FM_PCD_MANIP_IPSEC_ECN_EN 0x04000000
#define FM_PCD_MANIP_IPSEC_DSCP_EN 0x02000000
#define FM_PCD_MANIP_IPSEC_VIPL_EN 0x01000000
#define FM_PCD_MANIP_IPSEC_NADEN 0x20000000
#define FM_PCD_MANIP_IPSEC_IP_HDR_LEN_MASK 0x00FF0000
#define FM_PCD_MANIP_IPSEC_IP_HDR_LEN_SHIFT 16
#define FM_PCD_MANIP_IPSEC_ARW_SIZE_MASK 0xFFFF0000
#define FM_PCD_MANIP_IPSEC_ARW_SIZE_SHIFT 16
#define FM_PCD_MANIP_IP_REASM_COMMON_PARAM_TABLE_SIZE 64
#define FM_PCD_MANIP_IP_REASM_COMMON_PARAM_TABLE_ALIGN 8
#define FM_PCD_MANIP_IP_REASM_TIME_OUT_BETWEEN_FRAMES 0x80000000
#define e_FM_MANIP_IP_INDX 1
#define FM_PCD_MANIP_IP_REASM_LIODN_MASK 0x000003F0
#define FM_PCD_MANIP_IP_REASM_LIODN_SHIFT 56
#define FM_PCD_MANIP_IP_REASM_ELIODN_MASK 0x0000000F
#define FM_PCD_MANIP_IP_REASM_ELIODN_SHIFT 44
#endif /* UNDER_CONSTRUCTION_FRAG_REASSEMBLY */
#define HMCD_OPCODE_GENERIC_RMV 0x01
#define HMCD_OPCODE_GENERIC_INSRT 0x02
#define HMCD_OPCODE_GENERIC_REPLACE 0x05
#define HMCD_OPCODE_L2_RMV 0x08
#define HMCD_OPCODE_L2_INSRT 0x09
#define HMCD_OPCODE_VLAN_PRI_UPDATE 0x0B
#define HMCD_OPCODE_IPV4_UPDATE 0x0C
#define HMCD_OPCODE_IPV6_UPDATE 0x10
#define HMCD_OPCODE_TCP_UDP_UPDATE 0x0E
#define HMCD_OPCODE_TCP_UDP_CHECKSUM 0x14
#define HMCD_OPCODE_REPLACE_IP 0x12
#define HMCD_OPCODE_RMV_TILL 0x15
#define HMCD_OPCODE_UDP_INSRT 0x16
#define HMCD_OPCODE_IP_INSRT 0x17
#define HMCD_OPCODE_CAPWAP_RMV 0x18
#define HMCD_OPCODE_CAPWAP_INSRT 0x18
#define HMCD_OPCODE_GEN_FIELD_REPLACE 0x19
#define HMCD_LAST 0x00800000
#define HMCD_DSCP_VALUES 64
#define HMCD_BASIC_SIZE 4
#define HMCD_PTR_SIZE 4
#define HMCD_PARAM_SIZE 4
#define HMCD_IPV4_ADDR_SIZE 4
#define HMCD_IPV6_ADDR_SIZE 0x10
#define HMCD_L4_HDR_SIZE 8
#define HMCD_CAPWAP_INSRT 0x00010000
#define HMCD_INSRT_UDP_LITE 0x00010000
#define HMCD_IP_ID_MASK 0x0000FFFF
#define HMCD_IP_SIZE_MASK 0x0000FF00
#define HMCD_IP_SIZE_SHIFT 8
#define HMCD_IP_LAST_PID_MASK 0x000000FF
#define HMCD_IP_OR_QOS 0x00010000
#define HMCD_IP_L4_CS_CALC 0x00040000
#define HMCD_IP_DF_MODE 0x00400000
#define HMCD_OC_SHIFT 24
#define HMCD_RMV_OFFSET_SHIFT 0
#define HMCD_RMV_SIZE_SHIFT 8
#define HMCD_INSRT_OFFSET_SHIFT 0
#define HMCD_INSRT_SIZE_SHIFT 8
#define HMTD_CFG_TYPE 0x4000
#define HMTD_CFG_EXT_HMCT 0x0080
#define HMTD_CFG_PRS_AFTER_HM 0x0040
#define HMTD_CFG_NEXT_AD_EN 0x0020
#define HMCD_RMV_L2_ETHERNET 0
#define HMCD_RMV_L2_STACKED_QTAGS 1
#define HMCD_RMV_L2_ETHERNET_AND_MPLS 2
#define HMCD_RMV_L2_MPLS 3
#define HMCD_RMV_L2_PPPOE 4
#define HMCD_INSRT_L2_MPLS 0
#define HMCD_INSRT_N_UPDATE_L2_MPLS 1
#define HMCD_INSRT_L2_PPPOE 2
#define HMCD_INSRT_L2_SIZE_SHIFT 24
#define HMCD_L2_MODE_SHIFT 16
#define HMCD_VLAN_PRI_REP_MODE_SHIFT 16
#define HMCD_VLAN_PRI_UPDATE 0
#define HMCD_VLAN_PRI_UPDATE_DSCP_TO_VPRI 1
#define HMCD_IPV4_UPDATE_TTL 0x00000001
#define HMCD_IPV4_UPDATE_TOS 0x00000002
#define HMCD_IPV4_UPDATE_DST 0x00000020
#define HMCD_IPV4_UPDATE_SRC 0x00000040
#define HMCD_IPV4_UPDATE_ID 0x00000080
#define HMCD_IPV4_UPDATE_TOS_SHIFT 8
#define HMCD_IPV6_UPDATE_HL 0x00000001
#define HMCD_IPV6_UPDATE_TC 0x00000002
#define HMCD_IPV6_UPDATE_DST 0x00000040
#define HMCD_IPV6_UPDATE_SRC 0x00000080
#define HMCD_IPV6_UPDATE_TC_SHIFT 8
#define HMCD_TCP_UDP_UPDATE_DST 0x00004000
#define HMCD_TCP_UDP_UPDATE_SRC 0x00008000
#define HMCD_TCP_UDP_UPDATE_SRC_SHIFT 16
#define HMCD_IP_REPLACE_REPLACE_IPV4 0x00000000
#define HMCD_IP_REPLACE_REPLACE_IPV6 0x00010000
#define HMCD_IP_REPLACE_TTL_HL 0x00200000
#define HMCD_IP_REPLACE_ID 0x00400000
#define HMCD_IP_REPLACE_L3HDRSIZE_SHIFT 24
#define HMCD_GEN_FIELD_SIZE_SHIFT 16
#define HMCD_GEN_FIELD_SRC_OFF_SHIFT 8
#define HMCD_GEN_FIELD_DST_OFF_SHIFT 0
#define HMCD_GEN_FIELD_MASK_EN 0x00400000
#define HMCD_GEN_FIELD_MASK_OFF_SHIFT 16
#define HMCD_GEN_FIELD_MASK_SHIFT 24
#define DSCP_TO_VLAN_TABLE_SIZE 32
#define MANIP_GET_HMCT_SIZE(h_Manip) (((t_FmPcdManip *)h_Manip)->tableSize)
#define MANIP_GET_DATA_SIZE(h_Manip) (((t_FmPcdManip *)h_Manip)->dataSize)
#define MANIP_GET_HMCT_PTR(h_Manip) (((t_FmPcdManip *)h_Manip)->p_Hmct)
#define MANIP_GET_DATA_PTR(h_Manip) (((t_FmPcdManip *)h_Manip)->p_Data)
#define MANIP_SET_HMCT_PTR(h_Manip, h_NewPtr) (((t_FmPcdManip *)h_Manip)->p_Hmct = h_NewPtr)
#define MANIP_SET_DATA_PTR(h_Manip, h_NewPtr) (((t_FmPcdManip *)h_Manip)->p_Data = h_NewPtr)
#define MANIP_GET_HMTD_PTR(h_Manip) (((t_FmPcdManip *)h_Manip)->h_Ad)
#define MANIP_DONT_REPARSE(h_Manip) (((t_FmPcdManip *)h_Manip)->dontParseAfterManip)
#define MANIP_SET_PREV(h_Manip, h_Prev) (((t_FmPcdManip *)h_Manip)->h_PrevManip = h_Prev)
#define MANIP_GET_OWNERS(h_Manip) (((t_FmPcdManip *)h_Manip)->owner)
#define MANIP_GET_TYPE(h_Manip) (((t_FmPcdManip *)h_Manip)->type)
#define MANIP_SET_UNIFIED_TBL_PTR_INDICATION(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedTablePtr = TRUE)
#define MANIP_GET_MURAM(h_Manip) (((t_FmPcd *)((t_FmPcdManip *)h_Manip)->h_FmPcd)->h_FmMuram)
#define MANIP_FREE_HMTD(h_Manip) \
{if (((t_FmPcdManip *)h_Manip)->muramAllocate) \
FM_MURAM_FreeMem(((t_FmPcd *)((t_FmPcdManip *)h_Manip)->h_FmPcd)->h_FmMuram, ((t_FmPcdManip *)h_Manip)->h_Ad);\
else \
XX_Free(((t_FmPcdManip *)h_Manip)->h_Ad); \
((t_FmPcdManip *)h_Manip)->h_Ad = NULL; \
}
/* position regarding Manip SW structure */
#define MANIP_IS_FIRST(h_Manip) (!(((t_FmPcdManip *)h_Manip)->h_PrevManip))
#define MANIP_IS_CASCADED(h_Manip) (((t_FmPcdManip *)h_Manip)->cascaded)
#define MANIP_IS_UNIFIED(h_Manip) (!(((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_NONE))
#define MANIP_IS_UNIFIED_NON_FIRST(h_Manip) ((((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_MID) || \
(((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_LAST))
#define MANIP_IS_UNIFIED_NON_LAST(h_Manip) ((((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_FIRST) ||\
(((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_MID))
#define MANIP_IS_UNIFIED_FIRST(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_FIRST)
#define MANIP_IS_UNIFIED_LAST(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_LAST)
#define MANIP_UPDATE_UNIFIED_POSITION(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedPosition = \
(((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_NONE)? \
e_MANIP_UNIFIED_LAST : e_MANIP_UNIFIED_MID)
typedef enum e_ManipUnifiedPosition {
e_MANIP_UNIFIED_NONE = 0,
e_MANIP_UNIFIED_FIRST,
e_MANIP_UNIFIED_MID,
e_MANIP_UNIFIED_LAST
} e_ManipUnifiedPosition;
typedef enum e_ManipInfo {
e_MANIP_HMTD,
e_MANIP_HMCT,
e_MANIP_HANDLER_TABLE_OWNER
}e_ManipInfo;
/***********************************************************************/
/* Memory map */
/***********************************************************************/
@ -118,7 +326,8 @@
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
typedef _Packed struct {
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
typedef struct t_CapwapReasmPram {
volatile uint32_t mode;
volatile uint32_t autoLearnHashTblPtr;
volatile uint32_t intStatsTblPtr;
@ -141,20 +350,20 @@ typedef _Packed struct {
volatile uint32_t totalMoreThan16FramesCounter;
volatile uint32_t internalBufferBusy;
volatile uint32_t externalBufferBusy;
volatile uint8_t res[16];
} _PackedType t_CapwapReasmPram;
volatile uint32_t reserved1[4];
} t_CapwapReasmPram;
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
typedef _Packed struct t_IpReasmPram{
typedef _Packed struct t_ReassTbl {
volatile uint16_t waysNumAndSetSize;
volatile uint16_t autoLearnHashKeyMask;
volatile uint32_t ipReassCommonPrmTblPtr;
volatile uint32_t reassCommonPrmTblPtr;
volatile uint32_t liodnAlAndAutoLearnHashTblPtrHi;
volatile uint32_t autoLearnHashTblPtrLow;
volatile uint32_t liodnSlAndAutoLearnSetLockTblPtrHi;
volatile uint32_t autoLearnSetLockTblPtrLow;
volatile uint16_t minFragSize;
volatile uint16_t reserved1;
volatile uint16_t minFragSize; /* Not relevant for CAPWAP*/
volatile uint16_t maxReassemblySize; /* Only relevant for CAPWAP*/
volatile uint32_t totalSuccessfullyReasmFramesCounter;
volatile uint32_t totalValidFragmentCounter;
volatile uint32_t totalProcessedFragCounter;
@ -163,27 +372,38 @@ typedef _Packed struct t_IpReasmPram{
volatile uint32_t totalDiscardedFragsCounter;
volatile uint32_t totalMoreThan16FramesCounter;
volatile uint32_t reserved2[2];
} _PackedType t_IpReasmPram;
} _PackedType t_ReassTbl;
typedef _Packed struct t_IpReasmCommonTbl{
typedef struct t_ReassCommonTbl {
volatile uint32_t timeoutModeAndFqid;
volatile uint32_t reassFrmDescIndexPoolTblPtr;
volatile uint32_t liodnAndReassFrmDescPoolPtrHi;
volatile uint32_t reassFrmDescPoolPtrLow;
volatile uint32_t timeOutTblPtr;
volatile uint32_t expirationDelay;
volatile uint32_t reseervd1;
volatile uint32_t reseervd2;
volatile uint32_t internalBufferManagement;
volatile uint32_t reserved2;
volatile uint32_t totalTimeOutCounter;
volatile uint32_t totalRfdPoolBusyCounter;
volatile uint32_t totalInternalBufferBusy;
volatile uint32_t totalExternalBufferBusy;
volatile uint32_t reserved3[4];
} _PackedType t_IpReasmCommonTbl;
volatile uint32_t totalSgFragmentCounter;
volatile uint32_t totalDmaSemaphoreDepletionCounter;
volatile uint32_t totalNCSPCounter;
volatile uint32_t discardMask;
} t_ReassCommonTbl;
#endif /*UNDER_CONSTRUCTION_FRAG_REASSEMBLY*/
typedef _Packed struct t_Hmtd {
volatile uint16_t cfg;
volatile uint8_t eliodnOffset;
volatile uint8_t extHmcdBasePtrHi;
volatile uint32_t hmcdBasePtr;
volatile uint16_t nextAdIdx;
volatile uint8_t res1;
volatile uint8_t opCode;
volatile uint32_t res2;
} _PackedType t_Hmtd;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
@ -192,98 +412,125 @@ typedef _Packed struct t_IpReasmCommonTbl{
/***********************************************************************/
/* Driver's internal structures */
/***********************************************************************/
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
typedef struct
{
t_Handle p_AutoLearnHashTbl;
t_Handle p_ReassmFrmDescrPoolTbl;
t_Handle p_ReassmFrmDescrIndxPoolTbl;
t_Handle p_TimeOutTbl;
uint8_t maxNumFramesInProcess;
uint16_t maxNumFramesInProcess;
uint8_t numOfTasks;
uint8_t poolId;
//uint8_t poolId;
uint8_t prOffset;
uint16_t dataOffset;
uint8_t poolIndx;
uint8_t sgBpid;
uint8_t hwPortId;
uint32_t fqidForTimeOutFrames;
uint32_t timeoutRoutineRequestTime;
uint32_t bitFor1Micro;
} t_FragParams;
} t_CapwapFragParams;
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
typedef struct
{
t_Handle h_Frag;
t_Handle h_FragId;
uint8_t poolId;
uint16_t dataOffset;
uint8_t poolIndx;
}t_IpFragParams;
t_AdOfTypeContLookup *p_Frag;
#if (DPAA_VERSION == 10)
uint8_t scratchBpid;
#endif /* (DPAA_VERSION == 10) */
} t_FragParams;
typedef struct t_IpReassmParams
typedef struct t_ReassmParams
{
t_Handle h_Ipv4Ad;
t_Handle h_Ipv6Ad;
e_NetHeaderType hdr; /**< Header selection */
uint32_t fqidForTimeOutFrames;
uint16_t dataOffset;
t_Handle h_IpReassCommonParamsTbl;
t_Handle h_Ipv4ReassParamsTblPtr;
t_Handle h_Ipv6ReassParamsTblPtr;
t_Handle h_Ipv4AutoLearnHashTbl;
t_Handle h_Ipv6AutoLearnHashTbl;
t_Handle h_Ipv4AutoLearnSetLockTblPtr;
t_Handle h_Ipv6AutoLearnSetLockTblPtr;
t_Handle h_ReassmFrmDescrIndxPoolTbl;
t_Handle h_ReassmFrmDescrPoolTbl;
t_Handle h_TimeOutTbl;
uint32_t maxNumFramesInProcess;
uint32_t liodnOffset;
uint32_t minFragSize;
uint8_t dataMemId; /**< Memory partition ID for data buffers */
uint32_t bpid;
e_NetHeaderType hdr; /* Header selection */
t_ReassCommonTbl *p_ReassCommonTbl;
uintptr_t reassFrmDescrIndxPoolTblAddr;
uintptr_t reassFrmDescrPoolTblAddr;
uintptr_t timeOutTblAddr;
uintptr_t internalBufferPoolManagementIndexAddr;
uintptr_t internalBufferPoolAddr;
uint32_t maxNumFramesInProcess;
uint8_t sgBpid;
uint8_t dataMemId;
uint16_t dataLiodnOffset;
uint32_t fqidForTimeOutFrames;
e_FmPcdManipReassemTimeOutMode timeOutMode;
e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry;
uint32_t timeoutThresholdForReassmProcess;
}t_IpReassmParams;
typedef struct t_IpCommonReassmParams
{
uint8_t numOfTasks;
uint32_t bitFor1Micro;
t_Handle h_ReassmFrmDescrPoolTbl;
t_Handle h_ReassmFrmDescrIndxPoolTbl;
t_Handle h_TimeOutTbl;
}t_IpCommonReassmParams;
#endif /*UNDER_CONSTRUCTION_FRAG_REASSEMBLY*/
union {
struct {
t_Handle h_Ipv4Ad;
t_Handle h_Ipv6Ad;
bool ipv6Assigned;
t_ReassTbl *p_Ipv4ReassTbl;
t_ReassTbl *p_Ipv6ReassTbl;
uintptr_t ipv4AutoLearnHashTblAddr;
uintptr_t ipv6AutoLearnHashTblAddr;
uintptr_t ipv4AutoLearnSetLockTblAddr;
uintptr_t ipv6AutoLearnSetLockTblAddr;
uint16_t minFragSize[2];
e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry[2];
uint8_t relativeSchemeId[2];
t_Handle h_Ipv4Scheme;
t_Handle h_Ipv6Scheme;
uint32_t nonConsistentSpFqid;
} ip;
struct {
t_Handle h_Ad;
t_ReassTbl *p_ReassTbl;
uintptr_t autoLearnHashTblAddr;
uintptr_t autoLearnSetLockTblAddr;
uint16_t maxRessembledsSize;
e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry;
uint8_t relativeSchemeId;
t_Handle h_Scheme;
} capwap;
};
} t_ReassmParams;
typedef struct{
bool muramAllocate;
t_Handle h_Ad;
uint32_t type;
bool rmv;
bool insrt;
uint8_t *p_Template;
t_Handle h_Frag;
bool frag;
bool reassm;
uint16_t sizeForFragmentation;
uint8_t owner;
uint32_t updateParams;
uint32_t shadowUpdateParams;
t_FragParams fragParams;
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
t_IpReassmParams ipReassmParams;
t_IpFragParams ipFragParams;
#endif /* UNDER_CONSTRUCTION_FRAG_REASSEMBLY */
uint8_t icOffset;
uint16_t ownerTmp;
bool cnia;
t_Handle p_StatsTbl;
t_Handle h_FmPcd;
e_FmPcdManipType type;
t_FmPcdManipParams manipParams;
bool muramAllocate;
t_Handle h_Ad;
uint32_t opcode;
bool rmv;
bool insrt;
t_Handle h_NextManip;
t_Handle h_PrevManip;
e_FmPcdManipType nextManipType;
/* HdrManip parameters*/
uint8_t *p_Hmct;
uint8_t *p_Data;
bool dontParseAfterManip;
bool fieldUpdate;
bool custom;
uint16_t tableSize;
uint8_t dataSize;
bool cascaded;
e_ManipUnifiedPosition unifiedPosition;
/* end HdrManip */
uint8_t *p_Template;
uint16_t owner;
uint32_t updateParams;
uint32_t shadowUpdateParams;
bool frag;
bool reassm;
uint16_t sizeForFragmentation;
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
t_Handle h_Frag;
t_CapwapFragParams capwapFragParams;
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
union {
t_ReassmParams reassmParams;
t_FragParams fragParams;
};
uint8_t icOffset;
uint16_t ownerTmp;
bool cnia;
t_Handle p_StatsTbl;
t_Handle h_FmPcd;
t_List nodesLst;
t_Handle h_Spinlock;
} t_FmPcdManip;
typedef struct t_FmPcdCcSavedManipParams
@ -293,15 +540,13 @@ typedef struct t_FmPcdCcSavedManipParams
struct
{
uint16_t dataOffset;
uint8_t poolId;
//uint8_t poolId;
}capwapParams;
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
struct
{
uint16_t dataOffset;
uint8_t poolId;
}ipParams;
#endif /*UNDER_CONSTRUCTION_FRAG_REASSEMBLY*/
};
} t_FmPcdCcSavedManipParams;

1684
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_pcd.c
View File

File diff suppressed because it is too large Load Diff

574
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_pcd.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_pcd.h
@ -42,15 +43,25 @@
#include "error_ext.h"
#include "list_ext.h"
#include "fm_pcd_ext.h"
#include "fm_common.h"
#include "fsl_fman_prs.h"
#include "fsl_fman_kg.h"
#define __ERR_MODULE__ MODULE_FM_PCD
/**************************************************************************//**
@Group FM_PCD_Runtime_grp FM PCD Runtime Unit
@{
*//***************************************************************************/
/****************************/
/* Defaults */
/****************************/
#define DEFAULT_plcrAutoRefresh FALSE
#define DEFAULT_fmPcdKgErrorExceptions (FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW)
#define DEFAULT_fmPcdPlcrErrorExceptions (FM_PCD_EX_PLCR_DOUBLE_ECC | FM_PCD_EX_PLCR_INIT_ENTRY_ERROR)
#define DEFAULT_fmPcdPlcrExceptions 0
#define DEFAULT_fmPcdPrsErrorExceptions (FM_PCD_EX_PRS_DOUBLE_ECC)
#define DEFAULT_fmPcdPrsExceptions FM_PCD_EX_PRS_SINGLE_ECC
#define DEFAULT_numOfUsedProfilesPerWindow 16
#define DEFAULT_numOfSharedPlcrProfiles 4
/****************************/
/* Network defines */
@ -67,28 +78,26 @@
/****************************/
#define ILLEGAL_CLS_PLAN 0xff
#define ILLEGAL_NETENV 0xff
#define FM_PCD_MAX_NUM_OF_ALIAS_HDRS 3
/****************************/
/* Error defines */
/****************************/
#define FM_PCD_EX_KG_DOUBLE_ECC 0x80000000
#define FM_PCD_EX_KG_KEYSIZE_OVERFLOW 0x40000000
#define FM_PCD_EX_PLCR_DOUBLE_ECC 0x20000000
#define FM_PCD_EX_PLCR_INIT_ENTRY_ERROR 0x10000000
#define FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE 0x08000000
#define FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE 0x04000000
#define FM_PCD_EX_PRS_DOUBLE_ECC 0x02000000
#define FM_PCD_EX_PRS_SINGLE_ECC 0x01000000
#define GET_FM_PCD_EXCEPTION_FLAG(bitMask, exception) \
switch(exception){ \
switch (exception){ \
case e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC: \
bitMask = FM_PCD_EX_KG_DOUBLE_ECC; break; \
bitMask = FM_EX_KG_DOUBLE_ECC; break; \
case e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC: \
bitMask = FM_PCD_EX_PLCR_DOUBLE_ECC; break; \
case e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW: \
bitMask = FM_PCD_EX_KG_KEYSIZE_OVERFLOW; break; \
bitMask = FM_EX_KG_KEYSIZE_OVERFLOW; break; \
case e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR: \
bitMask = FM_PCD_EX_PLCR_INIT_ENTRY_ERROR; break; \
case e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE: \
@ -101,290 +110,24 @@ switch(exception){ \
bitMask = FM_PCD_EX_PRS_SINGLE_ECC; break; \
default: bitMask = 0;break;}
/***********************************************************************/
/* SW parser L4 shells patch */
/***********************************************************************/
#ifdef FM_PRS_L4_SHELL_ERRATA_FMANb
#define SW_PRS_L4_PATCH \
{ 0x31,0x92,0x02,0x1f,0x00,0x32,0x00,0x78, \
0x00,0x34,0x32,0xf0,0x00,0x50,0x00,0x0c, \
0x28,0x5e,0x83,0x8e,0x29,0x32,0xaf,0x8e, \
0x31,0xb2,0x9f,0xff,0x00,0x06,0xaf,0xbf, \
0x00,0x06,0x29,0x36,0x00,0x01,0x1b,0xff, \
0x32,0xf0,0x00,0x50,0x00,0x08,0x28,0x5e, \
0x08,0x99,0x00,0x00,0x9f,0x8e,0x31,0xb2, \
0x9f,0xff,0x00,0x06,0x29,0x36,0x00,0x01, \
0x1b,0xff,0x32,0xf0,0x00,0x50,0x00,0x04, \
0x28,0x5e,0x8f,0x9e,0x29,0x32,0x31,0xb2, \
0x8f,0xbf,0x00,0x06,0x29,0x36,0x00,0x01, \
0x1b,0xff,0x32,0xf0,0x00,0x50,0x00,0x04, \
0x28,0x5e,0x8f,0x9e,0x29,0x32,0x31,0xb2, \
0x8f,0xbf,0x00,0x06,0x29,0x36,0x00,0x01, \
0x1b,0xff,0x00,0x00,0x00,0x00,0x00,0x00};
#define SW_PRS_L4_PATCH_SIZE 120
#endif /* FM_PRS_L4_SHELL_ERRATA_FMANb */
/****************************/
/* Parser defines */
/****************************/
/* masks */
#define PRS_ERR_CAP 0x80000000
#define PRS_ERR_TYPE_DOUBLE 0x40000000
#define PRS_ERR_SINGLE_ECC_CNT_MASK 0x00FF0000
#define PRS_ERR_ADDR_MASK 0x000001FF
#define FM_PCD_PRS_RPIMAC_EN 0x00000001
#define FM_PCD_PRS_SINGLE_ECC 0x00004000
#define FM_PCD_PRS_PORT_IDLE_STS 0xffff0000
#define FM_PCD_PRS_DOUBLE_ECC 0x00004000
#define FM_PCD_PRS_PPSC_ALL_PORTS 0xffff0000
/* others */
#define PRS_MAX_CYCLE_LIMIT 8191
#define PRS_SW_DATA 0x00000800
#define PRS_REGS_OFFSET 0x00000840
#define GET_FM_PCD_PRS_PORT_ID(prsPortId,hardwarePortId) \
prsPortId = (uint8_t)(hardwarePortId & 0x0f)
#define GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId) \
bitMask = 0x80000000>>prsPortId
/***********************************************************************/
/* Keygen defines */
/***********************************************************************/
/* Masks */
#define FM_PCD_KG_KGGCR_EN 0x80000000
#define KG_SCH_GEN_VALID 0x80000000
#define KG_SCH_GEN_EXTRACT_TYPE 0x00008000
#define KG_ERR_CAP 0x80000000
#define KG_ERR_TYPE_DOUBLE 0x40000000
#define KG_ERR_ADDR_MASK 0x00000FFF
#define FM_PCD_KG_DOUBLE_ECC 0x80000000
#define FM_PCD_KG_KEYSIZE_OVERFLOW 0x40000000
#define KG_SCH_MODE_EN 0x80000000
/* shifts */
#define FM_PCD_KG_PE_CPP_MASK_SHIFT 16
#define FM_PCD_KG_KGAR_WSEL_SHIFT 8
/* others */
#define KG_DOUBLE_MEANING_REGS_OFFSET 0x100
#define NO_VALIDATION 0x70
#define KG_ACTION_REG_TO 1024
#define KG_MAX_PROFILE 255
#define SCHEME_ALWAYS_DIRECT 0xFFFFFFFF
typedef struct {
bool known;
uint8_t id;
} t_FmPcdKgSchemesExtractsEntry;
typedef struct {
t_FmPcdKgSchemesExtractsEntry extractsArray[FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY];
} t_FmPcdKgSchemesExtracts;
/***********************************************************************/
/* Policer defines */
/***********************************************************************/
/* masks */
#define FM_PCD_PLCR_PEMODE_PI 0x80000000
#define FM_PCD_PLCR_PEMODE_CBLND 0x40000000
#define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000
#define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000
#define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000
#define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000
#define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000
#define FM_PCD_PLCR_PEMODE_DEFC_R 0x08000000
#define FM_PCD_PLCR_PEMODE_DEFC_OVERRIDE 0x0C000000
#define FM_PCD_PLCR_PEMODE_OVCLR_MASK 0x03000000
#define FM_PCD_PLCR_PEMODE_OVCLR_Y 0x01000000
#define FM_PCD_PLCR_PEMODE_OVCLR_R 0x02000000
#define FM_PCD_PLCR_PEMODE_OVCLR_G_NC 0x03000000
#define FM_PCD_PLCR_PEMODE_PKT 0x00800000
#define FM_PCD_PLCR_PEMODE_FPP_MASK 0x001F0000
#define FM_PCD_PLCR_PEMODE_FPP_SHIFT 16
#define FM_PCD_PLCR_PEMODE_FLS_MASK 0x0000F000
#define FM_PCD_PLCR_PEMODE_FLS_L2 0x00003000
#define FM_PCD_PLCR_PEMODE_FLS_L3 0x0000B000
#define FM_PCD_PLCR_PEMODE_FLS_L4 0x0000E000
#define FM_PCD_PLCR_PEMODE_FLS_FULL 0x0000F000
#define FM_PCD_PLCR_PEMODE_RBFLS 0x00000800
#define FM_PCD_PLCR_PEMODE_TRA 0x00000004
#define FM_PCD_PLCR_PEMODE_TRB 0x00000002
#define FM_PCD_PLCR_PEMODE_TRC 0x00000001
#define FM_PCD_PLCR_GCR_STEN 0x40000000
#define FM_PCD_PLCR_DOUBLE_ECC 0x80000000
#define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000
#define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000
#define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000
#define FM_PCD_PLCR_NIA_VALID 0x80000000
#define FM_PCD_PLCR_GCR_EN 0x80000000
#define FM_PCD_PLCR_GCR_STEN 0x40000000
#define FM_PCD_PLCR_GCR_DAR 0x20000000
#define FM_PCD_PLCR_GCR_DEFNIA 0x00FFFFFF
#define FM_PCD_PLCR_NIA_ABS 0x00000100
#define FM_PCD_PLCR_GSR_BSY 0x80000000
#define FM_PCD_PLCR_GSR_DQS 0x60000000
#define FM_PCD_PLCR_GSR_RPB 0x20000000
#define FM_PCD_PLCR_GSR_FQS 0x0C000000
#define FM_PCD_PLCR_GSR_LPALG 0x0000C000
#define FM_PCD_PLCR_GSR_LPCA 0x00003000
#define FM_PCD_PLCR_GSR_LPNUM 0x000000FF
#define FM_PCD_PLCR_EVR_PSIC 0x80000000
#define FM_PCD_PLCR_EVR_AAC 0x40000000
#define FM_PCD_PLCR_PAR_PSI 0x20000000
#define FM_PCD_PLCR_PAR_PNUM 0x00FF0000
/* PWSEL Selctive select options */
#define FM_PCD_PLCR_PAR_PWSEL_PEMODE 0x00008000 /* 0 */
#define FM_PCD_PLCR_PAR_PWSEL_PEGNIA 0x00004000 /* 1 */
#define FM_PCD_PLCR_PAR_PWSEL_PEYNIA 0x00002000 /* 2 */
#define FM_PCD_PLCR_PAR_PWSEL_PERNIA 0x00001000 /* 3 */
#define FM_PCD_PLCR_PAR_PWSEL_PECIR 0x00000800 /* 4 */
#define FM_PCD_PLCR_PAR_PWSEL_PECBS 0x00000400 /* 5 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPIR_EIR 0x00000200 /* 6 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPBS_EBS 0x00000100 /* 7 */
#define FM_PCD_PLCR_PAR_PWSEL_PELTS 0x00000080 /* 8 */
#define FM_PCD_PLCR_PAR_PWSEL_PECTS 0x00000040 /* 9 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPTS_ETS 0x00000020 /* 10 */
#define FM_PCD_PLCR_PAR_PWSEL_PEGPC 0x00000010 /* 11 */
#define FM_PCD_PLCR_PAR_PWSEL_PEYPC 0x00000008 /* 12 */
#define FM_PCD_PLCR_PAR_PWSEL_PERPC 0x00000004 /* 13 */
#define FM_PCD_PLCR_PAR_PWSEL_PERYPC 0x00000002 /* 14 */
#define FM_PCD_PLCR_PAR_PWSEL_PERRPC 0x00000001 /* 15 */
#define FM_PCD_PLCR_PAR_PMR_BRN_1TO1 0x0000 /* - Full bit replacement. {PBNUM[0:N-1]
1-> 2^N specific locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_2TO2 0x1 /* - {PBNUM[0:N-2],PNUM[N-1]}.
2-> 2^(N-1) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_4TO4 0x2 /* - {PBNUM[0:N-3],PNUM[N-2:N-1]}.
4-> 2^(N-2) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_8TO8 0x3 /* - {PBNUM[0:N-4],PNUM[N-3:N-1]}.
8->2^(N-3) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_16TO16 0x4 /* - {PBNUM[0:N-5],PNUM[N-4:N-1]}.
16-> 2^(N-4) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_32TO32 0x5 /* {PBNUM[0:N-6],PNUM[N-5:N-1]}.
32-> 2^(N-5) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_64TO64 0x6 /* {PBNUM[0:N-7],PNUM[N-6:N-1]}.
64-> 2^(N-6) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_128TO128 0x7 /* {PBNUM[0:N-8],PNUM[N-7:N-1]}.
128-> 2^(N-7) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_256TO256 0x8 /* - No bit replacement for N=8. {PNUM[N-8:N-1]}.
When N=8 this option maps all 256 profiles by the DISPATCH bus into one group. */
#define FM_PCD_PLCR_PMR_V 0x80000000
#define PLCR_ERR_ECC_CAP 0x80000000
#define PLCR_ERR_ECC_TYPE_DOUBLE 0x40000000
#define PLCR_ERR_ECC_PNUM_MASK 0x00000FF0
#define PLCR_ERR_ECC_OFFSET_MASK 0x0000000F
#define PLCR_ERR_UNINIT_CAP 0x80000000
#define PLCR_ERR_UNINIT_NUM_MASK 0x000000FF
#define PLCR_ERR_UNINIT_PID_MASK 0x003f0000
#define PLCR_ERR_UNINIT_ABSOLUTE_MASK 0x00008000
/* shifts */
#define PLCR_ERR_ECC_PNUM_SHIFT 4
#define PLCR_ERR_UNINIT_PID_SHIFT 16
#define FM_PCD_PLCR_PMR_BRN_SHIFT 16
/* others */
#define WAIT_FOR_PLCR_EVR_AAC \
{\
uint32_t count = 0; \
uint32_t tmpReg32; \
while (count < FM_PCD_PLCR_POLL) \
{ \
tmpReg32 = GET_UINT32(p_FmPcdPlcrRegs->fmpl_evr);\
if (!( tmpReg32 & FM_PCD_PLCR_EVR_AAC)) break;\
count++;\
}\
}
#define WAIT_FOR_PLCR_PAR_GO \
{\
uint32_t count = 0; \
uint32_t tmpReg32; \
while (count < FM_PCD_PLCR_POLL) \
{ \
tmpReg32 = GET_UINT32(p_FmPcdPlcrRegs->fmpl_par);\
if (!( tmpReg32 & FM_PCD_PLCR_PAR_GO)) break;\
count++; \
}\
}
#define PLCR_PORT_WINDOW_SIZE(hardwarePortId)
/****************************/
/* Defaults */
/****************************/
#define DEFAULT_plcrAutoRefresh FALSE
#define DEFAULT_prsMaxParseCycleLimit 0
#define DEFAULT_fmPcdKgErrorExceptions (FM_PCD_EX_KG_DOUBLE_ECC | FM_PCD_EX_KG_KEYSIZE_OVERFLOW)
#define DEFAULT_fmPcdPlcrErrorExceptions (FM_PCD_EX_PLCR_DOUBLE_ECC | FM_PCD_EX_PLCR_INIT_ENTRY_ERROR)
#define DEFAULT_fmPcdPlcrExceptions 0
#define DEFAULT_fmPcdPrsErrorExceptions (FM_PCD_EX_PRS_DOUBLE_ECC)
#define DEFAULT_fmPcdPrsExceptions FM_PCD_EX_PRS_SINGLE_ECC
#define DEFAULT_numOfUsedProfilesPerWindow 16
#define DEFAULT_numOfSharedPlcrProfiles 4
/***********************************************************************/
/* Memory map */
/***********************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct {
volatile uint32_t kgoe_sp;
volatile uint32_t kgoe_cpp;
} _PackedType t_FmPcdKgPortConfigRegs;
typedef _Packed struct {
volatile uint32_t kgcpe[8];
} _PackedType t_FmPcdKgClsPlanRegs;
typedef _Packed union {
t_FmPcdKgInterModuleSchemeRegs schemeRegs;
t_FmPcdKgPortConfigRegs portRegs;
t_FmPcdKgClsPlanRegs clsPlanRegs;
} _PackedType u_FmPcdKgIndirectAccessRegs;
typedef _Packed struct {
volatile uint32_t kggcr;
volatile uint32_t res0;
volatile uint32_t res1;
volatile uint32_t kgeer;
volatile uint32_t kgeeer;
volatile uint32_t res2;
volatile uint32_t res3;
volatile uint32_t kgseer;
volatile uint32_t kgseeer;
volatile uint32_t kggsr;
volatile uint32_t kgtpc;
volatile uint32_t kgserc;
volatile uint32_t res4[4];
volatile uint32_t kgfdor;
volatile uint32_t kggdv0r;
volatile uint32_t kggdv1r;
volatile uint32_t res5[5];
volatile uint32_t kgfer;
volatile uint32_t kgfeer;
volatile uint32_t res6[38];
u_FmPcdKgIndirectAccessRegs indirectAccessRegs;
volatile uint32_t res[42]; /*(0xfc-sizeof(u_FmPcdKgIndirectAccessRegs))/4 */
volatile uint32_t kgar;
} _PackedType t_FmPcdKgRegs;
typedef _Packed struct {
typedef struct {
/* General Configuration and Status Registers */
volatile uint32_t fmpl_gcr; /* 0x000 FMPL_GCR - FM Policer General Configuration */
volatile uint32_t fmpl_gsr; /* 0x004 FMPL_GSR - FM Policer Global Status Register */
@ -404,7 +147,7 @@ typedef _Packed struct {
volatile uint32_t fmpl_res0[21]; /* 0x038 - 0x08B Reserved */
/* Profile RAM Access Registers */
volatile uint32_t fmpl_par; /* 0x08C FMPL_PAR - FM Policer Profile Action Register*/
t_FmPcdPlcrInterModuleProfileRegs profileRegs;
t_FmPcdPlcrProfileRegs profileRegs;
/* Error Capture Registers */
volatile uint32_t fmpl_serc; /* 0x100 FMPL_SERC - FM Policer Soft Error Capture */
volatile uint32_t fmpl_upcr; /* 0x104 FMPL_UPCR - FM Policer Uninitialized Profile Capture Register */
@ -415,42 +158,8 @@ typedef _Packed struct {
volatile uint32_t fmpl_dpmr; /* 0x200 FMPL_DPMR - FM Policer Default Mapping Register */
volatile uint32_t fmpl_pmr[63]; /*+default 0x204-0x2FF FMPL_PMR1 - FMPL_PMR63, - FM Policer Profile Mapping Registers.
(for port-ID 1-11, only for supported Port-ID registers) */
} _PackedType t_FmPcdPlcrRegs;
} t_FmPcdPlcrRegs;
typedef _Packed struct {
volatile uint32_t rpclim;
volatile uint32_t rpimac;
volatile uint32_t pmeec;
volatile uint32_t res1[5];
volatile uint32_t pevr;
volatile uint32_t pever;
volatile uint32_t pevfr;
volatile uint32_t perr;
volatile uint32_t perer;
volatile uint32_t perfr;
volatile uint32_t res2[0xA];
volatile uint32_t ppsc;
volatile uint32_t res3;
volatile uint32_t pds;
volatile uint32_t l2rrs;
volatile uint32_t l3rrs;
volatile uint32_t l4rrs;
volatile uint32_t srrs;
volatile uint32_t l2rres;
volatile uint32_t l3rres;
volatile uint32_t l4rres;
volatile uint32_t srres;
volatile uint32_t spcs;
volatile uint32_t spscs;
volatile uint32_t hxscs;
volatile uint32_t mrcs;
volatile uint32_t mwcs;
volatile uint32_t mrscs;
volatile uint32_t mwscs;
volatile uint32_t fcscs;
} _PackedType t_FmPcdPrsRegs;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
@ -460,6 +169,15 @@ typedef _Packed struct {
/* Driver's internal structures */
/***********************************************************************/
typedef struct {
bool known;
uint8_t id;
} t_FmPcdKgSchemesExtractsEntry;
typedef struct {
t_FmPcdKgSchemesExtractsEntry extractsArray[FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY];
} t_FmPcdKgSchemesExtracts;
typedef struct {
t_Handle h_Manip;
bool keepRes;
@ -472,12 +190,18 @@ typedef struct {
between the port and PCD regarding the KG scheme.
*//***************************************************************************/
typedef struct {
uint8_t netEnvId; /* in */
uint8_t numOfDistinctionUnits; /* in */
uint8_t unitIds[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; /* in */
uint32_t vector; /* out */
uint8_t netEnvId; /* in */
uint8_t numOfDistinctionUnits; /* in */
uint8_t unitIds[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; /* in */
uint32_t vector; /* out */
} t_NetEnvParams;
typedef struct {
bool allocated;
uint8_t ownerId; /* guestId for KG in multi-partition only.
portId for PLCR in any environment */
} t_FmPcdAllocMng;
typedef struct {
volatile bool lock;
bool used;
@ -490,7 +214,9 @@ typedef struct {
} t_FmPcdKgClsPlanGrp;
typedef struct {
volatile bool lock;
t_Handle h_FmPcd;
uint8_t schemeId;
t_FmPcdLock *p_Lock;
bool valid;
uint8_t netEnvId;
uint8_t owners;
@ -502,29 +228,34 @@ typedef struct {
t_FmPcdKgKeyOrder orderedArray;
e_FmPcdEngine nextEngine;
e_FmPcdDoneAction doneAction;
uint8_t pointedOwners;
bool requiredActionFlag;
uint32_t requiredAction;
bool extractedOrs;
uint8_t bitOffsetInPlcrProfile;
bool directPlcr;
#if (DPAA_VERSION >= 11)
bool vspe;
#endif
} t_FmPcdKgScheme;
typedef struct {
bool allocated;
uint8_t ownerId; /* guestId for KG in multi-partition only,
portId for PLCR in any environment */
} t_FmPcdAllocMng;
typedef union {
struct fman_kg_scheme_regs schemeRegs;
struct fman_kg_pe_regs portRegs;
struct fman_kg_cp_regs clsPlanRegs;
} u_FmPcdKgIndirectAccessRegs;
typedef struct {
t_FmPcdKgRegs *p_FmPcdKgRegs;
uint32_t schemeExceptionsBitMask;
uint8_t numOfSchemes;
uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES];
t_FmPcdKgScheme schemes[FM_PCD_KG_NUM_OF_SCHEMES];
t_FmPcdKgClsPlanGrp clsPlanGrps[FM_MAX_NUM_OF_PORTS];
uint8_t emptyClsPlanGrpId;
t_FmPcdAllocMng schemesMng[FM_PCD_KG_NUM_OF_SCHEMES]; /* only for MASTER ! */
t_FmPcdAllocMng clsPlanBlocksMng[FM_PCD_MAX_NUM_OF_CLS_PLANS/CLS_PLAN_NUM_PER_GRP];
struct fman_kg_regs *p_FmPcdKgRegs;
uint32_t schemeExceptionsBitMask;
uint8_t numOfSchemes;
t_Handle h_HwSpinlock;
uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES];
t_FmPcdKgScheme schemes[FM_PCD_KG_NUM_OF_SCHEMES];
t_FmPcdKgClsPlanGrp clsPlanGrps[FM_MAX_NUM_OF_PORTS];
uint8_t emptyClsPlanGrpId;
t_FmPcdAllocMng schemesMng[FM_PCD_KG_NUM_OF_SCHEMES]; /* only for MASTER ! */
t_FmPcdAllocMng clsPlanBlocksMng[FM_PCD_MAX_NUM_OF_CLS_PLANS/CLS_PLAN_NUM_PER_GRP];
u_FmPcdKgIndirectAccessRegs *p_IndirectAccessRegs;
} t_FmPcdKg;
typedef struct {
@ -534,11 +265,13 @@ typedef struct {
} t_FmPcdPlcrMapParam;
typedef struct {
bool valid;
volatile bool lock;
t_FmPcdAllocMng profilesMng;
uint8_t pointedOwners;
uint32_t requiredAction;
uint16_t absoluteProfileId;
t_Handle h_FmPcd;
bool valid;
t_FmPcdLock *p_Lock;
t_FmPcdAllocMng profilesMng;
bool requiredActionFlag;
uint32_t requiredAction;
e_FmPcdEngine nextEngineOnGreen; /**< Green next engine type */
u_FmPcdPlcrNextEngineParams paramsOnGreen; /**< Green next engine params */
@ -551,17 +284,21 @@ typedef struct {
typedef struct {
t_FmPcdPlcrRegs *p_FmPcdPlcrRegs;
uint16_t partPlcrProfilesBase;
uint16_t partNumOfPlcrProfiles;
t_FmPcdPlcrProfile profiles[FM_PCD_PLCR_NUM_ENTRIES];
uint16_t numOfSharedProfiles;
uint16_t sharedProfilesIds[FM_PCD_PLCR_NUM_ENTRIES];
t_FmPcdPlcrMapParam portsMapping[FM_MAX_NUM_OF_PORTS];
t_Handle h_HwSpinlock;
t_Handle h_SwSpinlock;
} t_FmPcdPlcr;
typedef struct {
uint32_t *p_SwPrsCode;
uint32_t *p_CurrSwPrs;
uint8_t currLabel;
t_FmPcdPrsRegs *p_FmPcdPrsRegs;
struct fman_prs_regs *p_FmPcdPrsRegs;
t_FmPcdPrsLabelParams labelsTable[FM_PCD_PRS_NUM_OF_LABELS];
uint32_t fmPcdPrsPortIdStatistics;
} t_FmPcdPrs;
@ -575,11 +312,14 @@ typedef struct {
typedef struct {
e_NetHeaderType hdr;
protocolOpt_t opt; /* only one option !! */
e_NetHeaderType aliasHdr;
} t_FmPcdNetEnvAliases;
typedef struct {
volatile bool lock;
uint8_t netEnvId;
t_Handle h_FmPcd;
t_Handle h_Spinlock;
bool used;
uint8_t owners;
uint8_t clsPlanGrpId;
@ -587,21 +327,26 @@ typedef struct {
uint32_t unitsVectors[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS];
uint32_t lcvs[FM_PCD_PRS_NUM_OF_HDRS];
uint32_t macsecVector;
t_FmPcdNetEnvAliases aliasHdrs[FM_PCD_MAX_NUM_OF_PRIVATE_HDRS];
t_FmPcdNetEnvAliases aliasHdrs[FM_PCD_MAX_NUM_OF_ALIAS_HDRS];
} t_FmPcdNetEnv;
typedef struct {
struct fman_prs_cfg dfltCfg;
bool plcrAutoRefresh;
uint16_t prsMaxParseCycleLimit;
} t_FmPcdDriverParam;
typedef struct {
t_Handle h_Fm;
t_Handle h_FmMuram;
t_FmRevisionInfo fmRevInfo;
uint64_t physicalMuramBase;
volatile bool lock;
t_Handle h_Spinlock;
t_List freeLocksLst;
t_List acquiredLocksLst;
t_Handle h_IpcSession; /* relevant for guest only */
bool enabled;
uint8_t guestId; /**< Guest Partition Id */
@ -613,42 +358,48 @@ typedef struct {
t_FmPcdPlcr *p_FmPcdPlcr;
t_FmPcdPrs *p_FmPcdPrs;
void *p_CcShadow; /**< CC MURAM shadow */
uint32_t ccShadowSize;
uint32_t ccShadowAlign;
volatile bool shadowLock;
t_Handle h_ShadowSpinlock;
t_Handle h_Hc;
uint32_t exceptions;
t_FmPcdExceptionCallback *f_Exception;
t_FmPcdIdExceptionCallback *f_FmPcdIndexedException;
t_Handle h_App;
uintptr_t ipv6FrameIdAddr;
uintptr_t capwapFrameIdAddr;
bool advancedOffloadSupport;
t_FmPcdDriverParam *p_FmPcdDriverParam;
} t_FmPcd;
#if (DPAA_VERSION >= 11)
typedef uint8_t t_FmPcdFrmReplicUpdateType;
#define FRM_REPLIC_UPDATE_COUNTER 0x01
#define FRM_REPLIC_UPDATE_INFO 0x02
#endif /* (DPAA_VERSION >= 11) */
/***********************************************************************/
/* PCD internal routines */
/***********************************************************************/
/**************************************************************************//**
@Group FM_PCD_InterModule_grp FM PCD Inter-Module Unit
@Description FM PCD Inter Module functions -
These are not User API routines but routines that may be called
from other modules. This will be the case in a single core environment,
where instead of useing the XX messeging mechanism, the routines may be
called from other modules. In a multicore environment, the other modules may
be run by other cores and therefor these routines may not be called directly.
@{
*//***************************************************************************/
t_Error PcdGetVectorForOpt(t_FmPcd *p_FmPcd, uint8_t netEnvId, protocolOpt_t opt, uint32_t *p_Vector);
t_Error PcdGetUnitsVector(t_FmPcd *p_FmPcd, t_NetEnvParams *p_Params);
bool PcdNetEnvIsUnitWithoutOpts(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint32_t unitVector);
t_Error PcdGetClsPlanGrpParams(t_FmPcd *p_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_GrpParams);
void FmPcdSetClsPlanGrpId(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint8_t clsPlanGrpId);
e_NetHeaderType FmPcdGetAliasHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr);
uint8_t FmPcdNetEnvGetUnitIdForSingleHdr(t_Handle h_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr);
uint8_t FmPcdNetEnvGetUnitIdForSingleHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr);
uint8_t FmPcdNetEnvGetUnitId(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr, bool interchangeable, protocolOpt_t opt);
t_Error FmPcdManipBuildIpReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, t_Handle h_CcTree, t_Handle h_Manip, bool isIpv4, uint8_t groupId);
t_Error FmPcdManipDeleteIpReassmSchemes(t_Handle h_Manip);
t_Error FmPcdManipBuildCapwapReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, t_Handle h_CcTree, t_Handle h_Manip, uint8_t groupId);
t_Error FmPcdManipDeleteCapwapReassmSchemes(t_Handle h_Manip);
bool FmPcdManipIpReassmIsIpv6Hdr(t_Handle h_Manip);
t_Handle KgConfig( t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams);
t_Error KgInit(t_FmPcd *p_FmPcd);
@ -666,15 +417,21 @@ t_Error FmPcdKgFreeSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t g
/* only for SINGLE partittion */
t_Error KgBindPortToSchemes(t_Handle h_FmPcd , uint8_t hardwarePortId, uint32_t spReg);
t_FmPcdLock *FmPcdAcquireLock(t_Handle h_FmPcd);
void FmPcdReleaseLock(t_Handle h_FmPcd, t_FmPcdLock *p_Lock);
t_Handle PlcrConfig(t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams);
t_Error PlcrInit(t_FmPcd *p_FmPcd);
t_Error PlcrFree(t_FmPcd *p_FmPcd);
void PlcrEnable(t_FmPcd *p_FmPcd);
void PlcrDisable(t_FmPcd *p_FmPcd);
t_Error PlcrFreeProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, uint16_t num, uint16_t base);
t_Error PlcrAllocProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, uint16_t numOfProfiles, uint16_t *p_Base);
t_Error PlcrAllocSharedProfiles(t_FmPcd *p_FmPcd, uint16_t numOfProfiles, uint16_t *profilesIds);
void PlcrFreeSharedProfiles(t_FmPcd *p_FmPcd, uint16_t numOfProfiles, uint16_t *profilesIds);
uint16_t PlcrAllocProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId);
void PlcrFreeProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId);
t_Error PlcrSetPortProfiles(t_FmPcd *p_FmPcd,
uint8_t hardwarePortId,
uint16_t numOfProfiles,
uint16_t base);
t_Error PlcrClearPortProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId);
t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams);
t_Error PrsInit(t_FmPcd *p_FmPcd);
@ -683,19 +440,56 @@ void PrsDisable(t_FmPcd *p_FmPcd);
void PrsFree(t_FmPcd *p_FmPcd );
t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include);
t_Handle FmPcdCcConfig(t_Handle h_FmPcd, t_FmPcdParams *p_FmPcdParams);
t_Error FmPcdCcGetGrpParams(t_Handle treeId, uint8_t grpId, uint32_t *p_GrpBits, uint8_t *p_GrpBase);
uint8_t FmPcdCcGetOffset(t_Handle h_CcNode);
uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode);
uint16_t FmPcdCcGetNumOfKeys(t_Handle h_CcNode);
t_Error ValidateNextEngineParams(t_Handle h_FmPcd, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams, e_FmPcdCcStatsMode supportedStatsMode);
void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add);
t_Error FmPcdManipCheckParamsForCcNextEgine(t_FmPcdCcNextEngineParams *p_InfoForManip, uint32_t *requiredAction);
void FmPcdManipUpdateAdResultForCc(t_Handle h_Manip, t_Handle p_Ad, t_Handle *p_AdNew);
t_Error FmPcdManipCheckParamsForCcNextEngine(t_FmPcdCcNextEngineParams *p_InfoForManip, uint32_t *requiredAction);
void FmPcdManipUpdateAdResultForCc(t_Handle h_Manip,
t_FmPcdCcNextEngineParams *p_CcNextEngineParams,
t_Handle p_Ad,
t_Handle *p_AdNewPtr);
void FmPcdManipUpdateAdContLookupForCc(t_Handle h_Manip, t_Handle p_Ad, t_Handle *p_AdNew, uint32_t adTableOffset);
uint32_t FmPcdManipCheckNia(t_Handle h_FmPcd, t_Handle h_Ad);
void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add);
t_Error FmPcdManipCheckParamsWithCcNodeParams(t_Handle h_Manip, t_Handle h_FmPcdCcNode);
#ifdef FM_CAPWAP_SUPPORT
t_Handle FmPcdManipApplSpecificBuild(void);
bool FmPcdManipIsCapwapApplSpecific(t_Handle h_Manip);
#endif /* FM_CAPWAP_SUPPORT */
#if (DPAA_VERSION >= 11)
void * FrmReplicGroupGetSourceTableDescriptor(t_Handle h_ReplicGroup);
void FrmReplicGroupUpdateOwner(t_Handle h_ReplicGroup, bool add);
void FrmReplicGroupUpdateAd(t_Handle h_ReplicGroup, void *p_Ad, t_Handle *h_AdNew);
void FmPcdCcGetAdTablesThatPointOnReplicGroup(t_Handle h_Node,
t_Handle h_ReplicGroup,
t_List *p_AdTables,
uint32_t *p_NumOfAdTables);
#endif /* (DPAA_VERSION >= 11) */
void EnqueueNodeInfoToRelevantLst(t_List *p_List, t_CcNodeInformation *p_CcInfo, t_Handle h_Spinlock);
void DequeueNodeInfoFromRelevantLst(t_List *p_List, t_Handle h_Info, t_Handle h_Spinlock);
t_CcNodeInformation* FindNodeInfoInReleventLst(t_List *p_List, t_Handle h_Info, t_Handle h_Spinlock);
t_List *FmPcdManipGetSpinlock(t_Handle h_Manip);
t_List *FmPcdManipGetNodeLstPointedOnThisManip(t_Handle h_Manip);
typedef struct
{
t_Handle h_StatsAd;
t_Handle h_StatsCounters;
#if (DPAA_VERSION >= 11)
t_Handle h_StatsFLRs;
#endif /* (DPAA_VERSION >= 11) */
} t_FmPcdCcStatsParams;
void NextStepAd(t_Handle h_Ad,
t_FmPcdCcStatsParams *p_FmPcdCcStatsParams,
t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams,
t_FmPcd *p_FmPcd);
void ReleaseLst(t_List *p_List);
static __inline__ t_Handle FmPcdGetMuramHandle(t_Handle h_FmPcd)
{
@ -711,5 +505,39 @@ static __inline__ uint64_t FmPcdGetMuramPhysBase(t_Handle h_FmPcd)
return p_FmPcd->physicalMuramBase;
}
static __inline__ uint32_t FmPcdLockSpinlock(t_FmPcdLock *p_Lock)
{
ASSERT_COND(p_Lock);
return XX_LockIntrSpinlock(p_Lock->h_Spinlock);
}
static __inline__ void FmPcdUnlockSpinlock(t_FmPcdLock *p_Lock, uint32_t flags)
{
ASSERT_COND(p_Lock);
XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, flags);
}
static __inline__ bool FmPcdLockTryLock(t_FmPcdLock *p_Lock)
{
uint32_t intFlags;
ASSERT_COND(p_Lock);
intFlags = XX_LockIntrSpinlock(p_Lock->h_Spinlock);
if (p_Lock->flag)
{
XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, intFlags);
return FALSE;
}
p_Lock->flag = TRUE;
XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, intFlags);
return TRUE;
}
static __inline__ void FmPcdLockUnlock(t_FmPcdLock *p_Lock)
{
ASSERT_COND(p_Lock);
p_Lock->flag = FALSE;
}
#endif /* __FM_PCD_H */

154
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_pcd_ipc.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_pcd_ipc.h
@ -53,7 +54,6 @@
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/**************************************************************************//**
@Description Structure for getting a sw parser address according to a label
@ -63,7 +63,7 @@
*//***************************************************************************/
typedef _Packed struct t_FmPcdIpcSwPrsLable
{
uint32_t enumHdr; /**< IN. The existance of this header will envoke
uint32_t enumHdr; /**< IN. The existence of this header will invoke
the sw parser code. */
uint8_t indexPerHdr; /**< IN. Normally 0, if more than one sw parser
attachments for the same header, use this
@ -79,38 +79,25 @@ typedef _Packed struct t_FmPcdIpcSwPrsLable
Some fields are optional (depending on configuration) and
will be analized by the port and FM modules accordingly.
*//***************************************************************************/
typedef struct t_FmPcdIpcKgSchemesParams
{
uint8_t guestId; /**< IN */
uint8_t numOfSchemes; /**< IN */
uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES]; /**< OUT */
uint8_t guestId;
uint8_t numOfSchemes;
uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES];
} _PackedType t_FmPcdIpcKgSchemesParams;
typedef struct t_FmPcdIpcKgClsPlanParams
{
uint8_t guestId; /**< IN */
uint16_t numOfClsPlanEntries; /**< IN */
uint8_t clsPlanBase; /**< IN in alloc only */
uint8_t guestId;
uint16_t numOfClsPlanEntries;
uint8_t clsPlanBase;
} _PackedType t_FmPcdIpcKgClsPlanParams;
typedef _Packed struct t_FmPcdIpcPlcrAllocParams
{
uint16_t num;
uint8_t hardwarePortId;
uint16_t plcrProfilesBase;
} _PackedType t_FmPcdIpcPlcrAllocParams;
typedef _Packed struct t_FmPcdIpcSharedPlcrAllocParams
{
uint16_t num; /**< IN */
//uint16_t profilesIds[FM_PCD_PLCR_NUM_ENTRIES]; /**< OUT */
uint32_t sharedProfilesMask[8];
} _PackedType t_FmPcdIpcSharedPlcrAllocParams;
typedef _Packed struct t_FmPcdIpcPrsIncludePort
{
uint8_t hardwarePortId; /* IN */
bool include; /* IN */
uint8_t hardwarePortId;
bool include;
} _PackedType t_FmPcdIpcPrsIncludePort;
@ -118,19 +105,22 @@ typedef _Packed struct t_FmPcdIpcPrsIncludePort
#define FM_PCD_MAX_MSG_SIZE 36
#define FM_PCD_MAX_REPLY_BODY_SIZE 36
typedef _Packed struct
{
typedef _Packed struct {
uint32_t msgId;
uint8_t msgBody[FM_PCD_MAX_MSG_SIZE];
} _PackedType t_FmPcdIpcMsg;
typedef _Packed struct t_FmPcdIpcReply
{
typedef _Packed struct t_FmPcdIpcReply {
uint32_t error;
uint8_t replyBody[FM_PCD_MAX_REPLY_BODY_SIZE];
} _PackedType t_FmPcdIpcReply;
#define MEM_MAP_END
typedef _Packed struct t_FmIpcResourceAllocParams {
uint8_t guestId;
uint16_t base;
uint16_t num;
}_PackedType t_FmIpcResourceAllocParams;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
@ -160,7 +150,7 @@ typedef _Packed struct t_FmPcdIpcReply
@Description Used by FM PCD front-end in order to allocate Policer profiles
@Param[in/out] t_FmPcdIpcKgSchemesParams Pointer
@Param[in/out] t_FmIpcResourceAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_PROFILES 5
@ -169,10 +159,30 @@ typedef _Packed struct t_FmPcdIpcReply
@Description Used by FM PCD front-end in order to Free Policer profiles
@Param[in/out] t_FmPcdIpcPlcrAllocParams Pointer
@Param[in/out] t_FmIpcResourceAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_PROFILES 6
/**************************************************************************//**
@Function FM_PCD_SET_PORT_PROFILES
@Description Used by FM PCD front-end in order to allocate Policer profiles
for specific port
@Param[in/out] t_FmIpcResourceAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_SET_PORT_PROFILES 7
/**************************************************************************//**
@Function FM_PCD_CLEAR_PORT_PROFILES
@Description Used by FM PCD front-end in order to allocate Policer profiles
for specific port
@Param[in/out] t_FmIpcResourceAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_CLEAR_PORT_PROFILES 8
/**************************************************************************//**
@Function FM_PCD_GET_PHYS_MURAM_BASE
@ -180,7 +190,7 @@ typedef _Packed struct t_FmPcdIpcReply
@Param[in/out] t_FmPcdIcPhysAddr Pointer
*//***************************************************************************/
#define FM_PCD_GET_PHYS_MURAM_BASE 7
#define FM_PCD_GET_PHYS_MURAM_BASE 9
/**************************************************************************//**
@Function FM_PCD_GET_SW_PRS_OFFSET
@ -190,25 +200,7 @@ typedef _Packed struct t_FmPcdIpcReply
@Param[in/out] t_FmPcdIpcSwPrsLable Pointer
*//***************************************************************************/
#define FM_PCD_GET_SW_PRS_OFFSET 8
/**************************************************************************//**
@Function FM_PCD_ALLOC_SHARED_PROFILES
@Description Used by FM PCD front-end in order to allocate shared profiles
@Param[in/out] t_FmPcdIpcSharedPlcrAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_SHARED_PROFILES 9
/**************************************************************************//**
@Function FM_PCD_FREE_SHARED_PROFILES
@Description Used by FM PCD front-end in order to free shared profiles
@Param[in/out] t_FmPcdIpcSharedPlcrAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_SHARED_PROFILES 10
#define FM_PCD_GET_SW_PRS_OFFSET 10
/**************************************************************************//**
@Function FM_PCD_MASTER_IS_ENABLED
@ -230,51 +222,6 @@ typedef _Packed struct t_FmPcdIpcReply
*//***************************************************************************/
#define FM_PCD_GUEST_DISABLE 16
/**************************************************************************//**
@Function FM_PCD_DUMP_REGS
@Description Used by FM front-end to dump all PCD registers
@Param[in] None
*//***************************************************************************/
#define FM_PCD_DUMP_REGS 17
/**************************************************************************//**
@Function FM_PCD_KG_DUMP_REGS
@Description Used by FM front-end to dump KG registers
@Param[in] None
*//***************************************************************************/
#define FM_PCD_KG_DUMP_REGS 18
/**************************************************************************//**
@Function FM_PCD_PLCR_DUMP_REGS
@Description Used by FM front-end to dump PLCR registers
@Param[in] None
*//***************************************************************************/
#define FM_PCD_PLCR_DUMP_REGS 19
/**************************************************************************//**
@Function FM_PCD_PLCR_PROFILE_DUMP_REGS
@Description Used by FM front-end to dump PLCR specified profile registers
@Param[in] t_Handle Pointer
*//***************************************************************************/
#define FM_PCD_PLCR_PROFILE_DUMP_REGS 20
/**************************************************************************//**
@Function FM_PCD_PRS_DUMP_REGS
@Description Used by FM front-end to dump PRS registers
@Param[in] None
*//***************************************************************************/
#define FM_PCD_PRS_DUMP_REGS 21
/**************************************************************************//**
@Function FM_PCD_FREE_KG_CLSPLAN
@ -282,7 +229,7 @@ typedef _Packed struct t_FmPcdIpcReply
@Param[in/out] t_FmPcdIpcKgClsPlanParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_KG_CLSPLAN 22
#define FM_PCD_FREE_KG_CLSPLAN 22
/**************************************************************************//**
@Function FM_PCD_ALLOC_KG_CLSPLAN
@ -291,7 +238,7 @@ typedef _Packed struct t_FmPcdIpcReply
@Param[in/out] t_FmPcdIpcKgClsPlanParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_KG_CLSPLAN 23
#define FM_PCD_ALLOC_KG_CLSPLAN 23
/**************************************************************************//**
@Function FM_PCD_MASTER_IS_ALIVE
@ -319,6 +266,13 @@ typedef _Packed struct t_FmPcdIpcReply
@Param[in/out] t_FmPcdIpcPrsIncludePort Pointer
*//***************************************************************************/
#define FM_PCD_PRS_INC_PORT_STATS 26
#if (DPAA_VERSION >= 11)
/* TODO - doc */
#define FM_PCD_ALLOC_SP 27
#endif /* (DPAA_VERSION >= 11) */
/** @} */ /* end of FM_PCD_IPC_grp group */
/** @} */ /* end of FM_grp group */

2111
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_plcr.c
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165
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_plcr.h Normal file
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@ -0,0 +1,165 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_plcr.h
@Description FM Policer private header
*//***************************************************************************/
#ifndef __FM_PLCR_H
#define __FM_PLCR_H
#include "std_ext.h"
/***********************************************************************/
/* Policer defines */
/***********************************************************************/
#define FM_PCD_PLCR_PAR_GO 0x80000000
#define FM_PCD_PLCR_PAR_PWSEL_MASK 0x0000FFFF
#define FM_PCD_PLCR_PAR_R 0x40000000
/* shifts */
#define FM_PCD_PLCR_PAR_PNUM_SHIFT 16
/* masks */
#define FM_PCD_PLCR_PEMODE_PI 0x80000000
#define FM_PCD_PLCR_PEMODE_CBLND 0x40000000
#define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000
#define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000
#define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000
#define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000
#define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000
#define FM_PCD_PLCR_PEMODE_DEFC_R 0x08000000
#define FM_PCD_PLCR_PEMODE_DEFC_OVERRIDE 0x0C000000
#define FM_PCD_PLCR_PEMODE_OVCLR_MASK 0x03000000
#define FM_PCD_PLCR_PEMODE_OVCLR_Y 0x01000000
#define FM_PCD_PLCR_PEMODE_OVCLR_R 0x02000000
#define FM_PCD_PLCR_PEMODE_OVCLR_G_NC 0x03000000
#define FM_PCD_PLCR_PEMODE_PKT 0x00800000
#define FM_PCD_PLCR_PEMODE_FPP_MASK 0x001F0000
#define FM_PCD_PLCR_PEMODE_FPP_SHIFT 16
#define FM_PCD_PLCR_PEMODE_FLS_MASK 0x0000F000
#define FM_PCD_PLCR_PEMODE_FLS_L2 0x00003000
#define FM_PCD_PLCR_PEMODE_FLS_L3 0x0000B000
#define FM_PCD_PLCR_PEMODE_FLS_L4 0x0000E000
#define FM_PCD_PLCR_PEMODE_FLS_FULL 0x0000F000
#define FM_PCD_PLCR_PEMODE_RBFLS 0x00000800
#define FM_PCD_PLCR_PEMODE_TRA 0x00000004
#define FM_PCD_PLCR_PEMODE_TRB 0x00000002
#define FM_PCD_PLCR_PEMODE_TRC 0x00000001
#define FM_PCD_PLCR_DOUBLE_ECC 0x80000000
#define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000
#define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000
#define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000
#define FM_PCD_PLCR_NIA_VALID 0x80000000
#define FM_PCD_PLCR_GCR_EN 0x80000000
#define FM_PCD_PLCR_GCR_STEN 0x40000000
#define FM_PCD_PLCR_GCR_DAR 0x20000000
#define FM_PCD_PLCR_GCR_DEFNIA 0x00FFFFFF
#define FM_PCD_PLCR_NIA_ABS 0x00000100
#define FM_PCD_PLCR_GSR_BSY 0x80000000
#define FM_PCD_PLCR_GSR_DQS 0x60000000
#define FM_PCD_PLCR_GSR_RPB 0x20000000
#define FM_PCD_PLCR_GSR_FQS 0x0C000000
#define FM_PCD_PLCR_GSR_LPALG 0x0000C000
#define FM_PCD_PLCR_GSR_LPCA 0x00003000
#define FM_PCD_PLCR_GSR_LPNUM 0x000000FF
#define FM_PCD_PLCR_EVR_PSIC 0x80000000
#define FM_PCD_PLCR_EVR_AAC 0x40000000
#define FM_PCD_PLCR_PAR_PSI 0x20000000
#define FM_PCD_PLCR_PAR_PNUM 0x00FF0000
/* PWSEL Selctive select options */
#define FM_PCD_PLCR_PAR_PWSEL_PEMODE 0x00008000 /* 0 */
#define FM_PCD_PLCR_PAR_PWSEL_PEGNIA 0x00004000 /* 1 */
#define FM_PCD_PLCR_PAR_PWSEL_PEYNIA 0x00002000 /* 2 */
#define FM_PCD_PLCR_PAR_PWSEL_PERNIA 0x00001000 /* 3 */
#define FM_PCD_PLCR_PAR_PWSEL_PECIR 0x00000800 /* 4 */
#define FM_PCD_PLCR_PAR_PWSEL_PECBS 0x00000400 /* 5 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPIR_EIR 0x00000200 /* 6 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPBS_EBS 0x00000100 /* 7 */
#define FM_PCD_PLCR_PAR_PWSEL_PELTS 0x00000080 /* 8 */
#define FM_PCD_PLCR_PAR_PWSEL_PECTS 0x00000040 /* 9 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPTS_ETS 0x00000020 /* 10 */
#define FM_PCD_PLCR_PAR_PWSEL_PEGPC 0x00000010 /* 11 */
#define FM_PCD_PLCR_PAR_PWSEL_PEYPC 0x00000008 /* 12 */
#define FM_PCD_PLCR_PAR_PWSEL_PERPC 0x00000004 /* 13 */
#define FM_PCD_PLCR_PAR_PWSEL_PERYPC 0x00000002 /* 14 */
#define FM_PCD_PLCR_PAR_PWSEL_PERRPC 0x00000001 /* 15 */
#define FM_PCD_PLCR_PAR_PMR_BRN_1TO1 0x0000 /* - Full bit replacement. {PBNUM[0:N-1]
1-> 2^N specific locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_2TO2 0x1 /* - {PBNUM[0:N-2],PNUM[N-1]}.
2-> 2^(N-1) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_4TO4 0x2 /* - {PBNUM[0:N-3],PNUM[N-2:N-1]}.
4-> 2^(N-2) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_8TO8 0x3 /* - {PBNUM[0:N-4],PNUM[N-3:N-1]}.
8->2^(N-3) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_16TO16 0x4 /* - {PBNUM[0:N-5],PNUM[N-4:N-1]}.
16-> 2^(N-4) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_32TO32 0x5 /* {PBNUM[0:N-6],PNUM[N-5:N-1]}.
32-> 2^(N-5) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_64TO64 0x6 /* {PBNUM[0:N-7],PNUM[N-6:N-1]}.
64-> 2^(N-6) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_128TO128 0x7 /* {PBNUM[0:N-8],PNUM[N-7:N-1]}.
128-> 2^(N-7) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_256TO256 0x8 /* - No bit replacement for N=8. {PNUM[N-8:N-1]}.
When N=8 this option maps all 256 profiles by the DISPATCH bus into one group. */
#define FM_PCD_PLCR_PMR_V 0x80000000
#define PLCR_ERR_ECC_CAP 0x80000000
#define PLCR_ERR_ECC_TYPE_DOUBLE 0x40000000
#define PLCR_ERR_ECC_PNUM_MASK 0x00000FF0
#define PLCR_ERR_ECC_OFFSET_MASK 0x0000000F
#define PLCR_ERR_UNINIT_CAP 0x80000000
#define PLCR_ERR_UNINIT_NUM_MASK 0x000000FF
#define PLCR_ERR_UNINIT_PID_MASK 0x003f0000
#define PLCR_ERR_UNINIT_ABSOLUTE_MASK 0x00008000
/* shifts */
#define PLCR_ERR_ECC_PNUM_SHIFT 4
#define PLCR_ERR_UNINIT_PID_SHIFT 16
#define FM_PCD_PLCR_PMR_BRN_SHIFT 16
#define PLCR_PORT_WINDOW_SIZE(hardwarePortId)
#endif /* __FM_PLCR_H */

636
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_prs.c
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@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,11 +30,13 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_pcd.c
@Description FM PCD ...
*//***************************************************************************/
#include <linux/math64.h>
#include "std_ext.h"
#include "error_ext.h"
#include "string_ext.h"
@ -44,8 +46,48 @@
#include "fm_common.h"
#include "fm_pcd.h"
#include "fm_pcd_ipc.h"
#include "fm_prs.h"
#include "fsl_fman_prs.h"
static void PcdPrsErrorException(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
uint32_t event, ev_mask;
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
ev_mask = fman_prs_get_err_ev_mask(PrsRegs);
event = fman_prs_get_err_event(PrsRegs, ev_mask);
fman_prs_ack_err_event(PrsRegs, event);
DBG(TRACE, ("parser error - 0x%08x\n",event));
if(event & FM_PCD_PRS_DOUBLE_ECC)
p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC);
}
static void PcdPrsException(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
uint32_t event, ev_mask;
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
ev_mask = fman_prs_get_expt_ev_mask(PrsRegs);
event = fman_prs_get_expt_event(PrsRegs, ev_mask);
ASSERT_COND(event & FM_PCD_PRS_SINGLE_ECC);
DBG(TRACE, ("parser event - 0x%08x\n",event));
fman_prs_ack_expt_event(PrsRegs, event);
p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC);
}
t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams)
{
t_FmPcdPrs *p_FmPcdPrs;
@ -61,81 +103,216 @@ t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams)
return NULL;
}
memset(p_FmPcdPrs, 0, sizeof(t_FmPcdPrs));
fman_prs_defconfig(&p_FmPcd->p_FmPcdDriverParam->dfltCfg);
if (p_FmPcd->guestId == NCSW_MASTER_ID)
{
baseAddr = FmGetPcdPrsBaseAddr(p_FmPcdParams->h_Fm);
p_FmPcdPrs->p_SwPrsCode = (uint32_t *)UINT_TO_PTR(baseAddr);
p_FmPcdPrs->p_FmPcdPrsRegs = (t_FmPcdPrsRegs *)UINT_TO_PTR(baseAddr + PRS_REGS_OFFSET);
p_FmPcdPrs->p_FmPcdPrsRegs = (struct fman_prs_regs *)UINT_TO_PTR(baseAddr + PRS_REGS_OFFSET);
}
p_FmPcdPrs->fmPcdPrsPortIdStatistics = 0;
p_FmPcd->p_FmPcdDriverParam->prsMaxParseCycleLimit = DEFAULT_prsMaxParseCycleLimit;
p_FmPcd->exceptions |= (DEFAULT_fmPcdPrsErrorExceptions | DEFAULT_fmPcdPrsExceptions);
p_FmPcdPrs->fmPcdPrsPortIdStatistics = p_FmPcd->p_FmPcdDriverParam->dfltCfg.port_id_stat;
p_FmPcd->p_FmPcdDriverParam->prsMaxParseCycleLimit = p_FmPcd->p_FmPcdDriverParam->dfltCfg.max_prs_cyc_lim;
p_FmPcd->exceptions |= p_FmPcd->p_FmPcdDriverParam->dfltCfg.prs_exceptions;
return p_FmPcdPrs;
}
static void PcdPrsErrorException(t_Handle h_FmPcd)
#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT))
static uint8_t swPrsPatch[] = SW_PRS_UDP_LITE_PATCH;
#else
static uint8_t swPrsPatch[] = SW_PRS_OFFLOAD_PATCH;
#endif /* FM_CAPWAP_SUPPORT */
t_Error PrsInit(t_FmPcd *p_FmPcd)
{
t_FmPcdDriverParam *p_Param = p_FmPcd->p_FmPcdDriverParam;
uint32_t *p_TmpCode;
uint32_t *p_LoadTarget = (uint32_t *)PTR_MOVE(p_FmPcd->p_FmPcdPrs->p_SwPrsCode,
FM_PCD_SW_PRS_SIZE-FM_PCD_PRS_SW_PATCHES_SIZE);
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
uint32_t i;
ASSERT_COND(sizeof(swPrsPatch) <= (FM_PCD_PRS_SW_PATCHES_SIZE-FM_PCD_PRS_SW_TAIL_SIZE));
/* nothing to do in guest-partition */
if (p_FmPcd->guestId != NCSW_MASTER_ID)
return E_OK;
p_TmpCode = (uint32_t *)XX_MallocSmart(ROUND_UP(sizeof(swPrsPatch),4), 0, sizeof(uint32_t));
if (!p_TmpCode)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Tmp Sw-Parser code allocation FAILED"));
memset((uint8_t *)p_TmpCode, 0, ROUND_UP(sizeof(swPrsPatch),4));
memcpy((uint8_t *)p_TmpCode, (uint8_t *)swPrsPatch, sizeof(swPrsPatch));
fman_prs_init(PrsRegs, &p_Param->dfltCfg);
/* register even if no interrupts enabled, to allow future enablement */
FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR, PcdPrsErrorException, p_FmPcd);
/* register even if no interrupts enabled, to allow future enablement */
FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL, PcdPrsException, p_FmPcd);
if(p_FmPcd->exceptions & FM_PCD_EX_PRS_SINGLE_ECC)
FmEnableRamsEcc(p_FmPcd->h_Fm);
if(p_FmPcd->exceptions & FM_PCD_EX_PRS_DOUBLE_ECC)
FmEnableRamsEcc(p_FmPcd->h_Fm);
/* load sw parser Ip-Frag patch */
for (i=0; i<DIV_CEIL(sizeof(swPrsPatch), 4); i++)
WRITE_UINT32(p_LoadTarget[i], GET_UINT32(p_TmpCode[i]));
XX_FreeSmart(p_TmpCode);
return E_OK;
}
void PrsFree(t_FmPcd *p_FmPcd)
{
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR);
/* register even if no interrupts enabled, to allow future enablement */
FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL);
}
void PrsEnable(t_FmPcd *p_FmPcd)
{
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
fman_prs_enable(PrsRegs);
}
void PrsDisable(t_FmPcd *p_FmPcd)
{
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
fman_prs_disable(PrsRegs);
}
int PrsIsEnabled(t_FmPcd *p_FmPcd)
{
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
return fman_prs_is_enabled(PrsRegs);
}
t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include)
{
struct fman_prs_regs *PrsRegs;
uint32_t bitMask = 0;
uint8_t prsPortId;
SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
GET_FM_PCD_PRS_PORT_ID(prsPortId, hardwarePortId);
GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId);
if (include)
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics |= bitMask;
else
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics &= ~bitMask;
fman_prs_set_stst_port_msk(PrsRegs,
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics);
return E_OK;
}
t_Error FmPcdPrsIncludePortInStatistics(t_Handle h_FmPcd, uint8_t hardwarePortId, bool include)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
t_Error err;
SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
if ((p_FmPcd->guestId != NCSW_MASTER_ID) &&
p_FmPcd->h_IpcSession)
{
t_FmPcdIpcPrsIncludePort prsIncludePortParams;
t_FmPcdIpcMsg msg;
prsIncludePortParams.hardwarePortId = hardwarePortId;
prsIncludePortParams.include = include;
memset(&msg, 0, sizeof(msg));
msg.msgId = FM_PCD_PRS_INC_PORT_STATS;
memcpy(msg.msgBody, &prsIncludePortParams, sizeof(prsIncludePortParams));
err = XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId) +sizeof(prsIncludePortParams),
NULL,
NULL,
NULL,
NULL);
if (err != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
return E_OK;
}
else if (p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED,
("running in guest-mode without IPC!"));
return PrsIncludePortInStatistics(p_FmPcd, hardwarePortId, include);
}
uint32_t FmPcdGetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t indexPerHdr)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
uint32_t event, mask, force;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
event = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perr);
mask = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perer);
event &= mask;
/* clear the forced events */
force = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perfr);
if(force & event)
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perfr, force & ~event);
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perr, event);
DBG(TRACE, ("parser error - 0x%08x\n",event));
if(event & FM_PCD_PRS_DOUBLE_ECC)
p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC);
}
static void PcdPrsException(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
uint32_t event, force;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
event = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pevr);
event &= GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pever);
ASSERT_COND(event & FM_PCD_PRS_SINGLE_ECC);
DBG(TRACE, ("parser event - 0x%08x\n",event));
/* clear the forced events */
force = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pevfr);
if(force & event)
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pevfr, force & ~event);
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pevr, event);
p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC);
}
static uint32_t GetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t indexPerHdr)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
int i;
t_FmPcdPrsLabelParams *p_Label;
int i;
SANITY_CHECK_RETURN_VALUE(p_FmPcd, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE, 0);
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
if ((p_FmPcd->guestId != NCSW_MASTER_ID) &&
p_FmPcd->h_IpcSession)
{
t_Error err = E_OK;
t_FmPcdIpcSwPrsLable labelParams;
t_FmPcdIpcMsg msg;
uint32_t prsOffset = 0;
t_FmPcdIpcReply reply;
uint32_t replyLength;
memset(&reply, 0, sizeof(reply));
memset(&msg, 0, sizeof(msg));
labelParams.enumHdr = (uint32_t)hdr;
labelParams.indexPerHdr = indexPerHdr;
msg.msgId = FM_PCD_GET_SW_PRS_OFFSET;
memcpy(msg.msgBody, &labelParams, sizeof(labelParams));
replyLength = sizeof(uint32_t) + sizeof(uint32_t);
err = XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId) +sizeof(labelParams),
(uint8_t*)&reply,
&replyLength,
NULL,
NULL);
if (err != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
if (replyLength != sizeof(uint32_t) + sizeof(uint32_t))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch"));
memcpy((uint8_t*)&prsOffset, reply.replyBody, sizeof(uint32_t));
return prsOffset;
}
else if (p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED,
("running in guest-mode without IPC!"));
ASSERT_COND(p_FmPcd->p_FmPcdPrs->currLabel < FM_PCD_PRS_NUM_OF_LABELS);
for (i=0; i < p_FmPcd->p_FmPcdPrs->currLabel; i++)
for (i=0; i<p_FmPcd->p_FmPcdPrs->currLabel; i++)
{
p_Label = &p_FmPcd->p_FmPcdPrs->labelsTable[i];
@ -147,248 +324,32 @@ static uint32_t GetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t
return (uint32_t)ILLEGAL_BASE;
}
t_Error PrsInit(t_FmPcd *p_FmPcd)
{
t_FmPcdDriverParam *p_Param = p_FmPcd->p_FmPcdDriverParam;
t_FmPcdPrsRegs *p_Regs = p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
uint32_t tmpReg;
if(p_FmPcd->guestId != NCSW_MASTER_ID)
return E_OK;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
#ifdef FM_PRS_MEM_ERRATA_FMAN_SW003
{
uint32_t i;
uint32_t regsToGlobalOffset = 0x840;
uint32_t firstPortToGlobalOffset = 0x45800;
uint64_t globalAddr = PTR_TO_UINT(p_Regs) - regsToGlobalOffset;
uint32_t firstPortAddr = (uint32_t)(globalAddr - (uint64_t)firstPortToGlobalOffset);
uint32_t portSize = 0x1000;
t_FmRevisionInfo revInfo;
FM_GetRevision(p_FmPcd->h_Fm, &revInfo);
if ((revInfo.majorRev == 1) && (revInfo.minorRev == 0))
{
/* clear all parser memory */
IOMemSet32(UINT_TO_PTR(globalAddr), 0x00000000, 0x800);
for(i = 0;i<16;i++)
IOMemSet32(UINT_TO_PTR(firstPortAddr+i*portSize), (uint8_t)0x00000000, (uint32_t)0x80);
}
}
#endif /* FM_PRS_MEM_ERRATA_FMAN_SW003 */
/**********************RPCLIM******************/
WRITE_UINT32(p_Regs->rpclim, (uint32_t)p_Param->prsMaxParseCycleLimit);
/**********************FMPL_RPCLIM******************/
/* register even if no interrupts enabled, to allow future enablement */
FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR, PcdPrsErrorException, p_FmPcd);
/* register even if no interrupts enabled, to allow future enablement */
FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL, PcdPrsException, p_FmPcd);
/**********************PEVR******************/
WRITE_UINT32(p_Regs->pevr, (FM_PCD_PRS_SINGLE_ECC | FM_PCD_PRS_PORT_IDLE_STS) );
/**********************PEVR******************/
/**********************PEVER******************/
if(p_FmPcd->exceptions & FM_PCD_EX_PRS_SINGLE_ECC)
{
FmEnableRamsEcc(p_FmPcd->h_Fm);
WRITE_UINT32(p_Regs->pever, FM_PCD_PRS_SINGLE_ECC);
}
else
WRITE_UINT32(p_Regs->pever, 0);
/**********************PEVER******************/
/**********************PERR******************/
WRITE_UINT32(p_Regs->perr, FM_PCD_PRS_DOUBLE_ECC);
/**********************PERR******************/
/**********************PERER******************/
tmpReg = 0;
if(p_FmPcd->exceptions & FM_PCD_EX_PRS_DOUBLE_ECC)
{
FmEnableRamsEcc(p_FmPcd->h_Fm);
tmpReg |= FM_PCD_PRS_DOUBLE_ECC;
}
WRITE_UINT32(p_Regs->perer, tmpReg);
/**********************PERER******************/
/**********************PPCS******************/
WRITE_UINT32(p_Regs->ppsc, p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics);
/**********************PPCS******************/
#ifdef FM_PRS_L4_SHELL_ERRATA_FMANb
{
uint32_t i, j;
t_FmRevisionInfo revInfo;
uint8_t swPrsL4Patch[] = SW_PRS_L4_PATCH;
FM_GetRevision(p_FmPcd->h_Fm, &revInfo);
if ((revInfo.majorRev == 1) && (revInfo.minorRev == 0))
{
/* load sw parser L4 patch */
for(i=0;i<sizeof(swPrsL4Patch)/4;i++)
{
tmpReg = 0;
for(j =0;j<4;j++)
{
tmpReg <<= 8;
tmpReg |= swPrsL4Patch[i*4+j];
}
WRITE_UINT32(*(p_FmPcd->p_FmPcdPrs->p_SwPrsCode+ FM_PCD_PRS_SW_OFFSET/4 + i), tmpReg);
}
p_FmPcd->p_FmPcdPrs->p_CurrSwPrs = FM_PCD_PRS_SW_OFFSET/4 + p_FmPcd->p_FmPcdPrs->p_SwPrsCode+sizeof(swPrsL4Patch)/4;
}
}
#endif /* FM_PRS_L4_SHELL_ERRATA_FMANb */
return E_OK;
}
void PrsFree(t_FmPcd *p_FmPcd )
{
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR);
/* register even if no interrupts enabled, to allow future enablement */
FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL);
}
void PrsEnable(t_FmPcd *p_FmPcd )
{
t_FmPcdPrsRegs *p_Regs = p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
WRITE_UINT32(p_Regs->rpimac, GET_UINT32(p_Regs->rpimac) | FM_PCD_PRS_RPIMAC_EN);
}
void PrsDisable(t_FmPcd *p_FmPcd )
{
t_FmPcdPrsRegs *p_Regs = p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
WRITE_UINT32(p_Regs->rpimac, GET_UINT32(p_Regs->rpimac) & ~FM_PCD_PRS_RPIMAC_EN);
}
t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include)
{
uint32_t bitMask = 0;
uint8_t prsPortId;
SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
GET_FM_PCD_PRS_PORT_ID(prsPortId, hardwarePortId);
GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId);
if(include)
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics |= bitMask;
else
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics &= ~bitMask;
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->ppsc, p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics);
return E_OK;
}
t_Error FmPcdPrsIncludePortInStatistics(t_Handle h_FmPcd, uint8_t hardwarePortId, bool include)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
t_FmPcdIpcPrsIncludePort prsIncludePortParams;
t_FmPcdIpcMsg msg;
t_Error err;
SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
if(p_FmPcd->guestId != NCSW_MASTER_ID)
{
prsIncludePortParams.hardwarePortId = hardwarePortId;
prsIncludePortParams.include = include;
memset(&msg, 0, sizeof(msg));
msg.msgId = FM_PCD_PRS_INC_PORT_STATS;
memcpy(msg.msgBody, &prsIncludePortParams, sizeof(prsIncludePortParams));
if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId) +sizeof(prsIncludePortParams),
NULL,
NULL,
NULL,
NULL)) != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
return E_OK;
}
return PrsIncludePortInStatistics(p_FmPcd, hardwarePortId, include);
}
uint32_t FmPcdGetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t indexPerHdr)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
t_Error err = E_OK;
t_FmPcdIpcSwPrsLable labelParams;
t_FmPcdIpcMsg msg;
uint32_t prsOffset = 0;
t_FmPcdIpcReply reply;
uint32_t replyLength;
if(p_FmPcd->guestId != NCSW_MASTER_ID)
{
memset(&reply, 0, sizeof(reply));
memset(&msg, 0, sizeof(msg));
labelParams.enumHdr = (uint32_t)hdr;
labelParams.indexPerHdr = indexPerHdr;
msg.msgId = FM_PCD_GET_SW_PRS_OFFSET;
memcpy(msg.msgBody, &labelParams, sizeof(labelParams));
replyLength = sizeof(uint32_t) + sizeof(uint32_t);
if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId) +sizeof(labelParams),
(uint8_t*)&reply,
&replyLength,
NULL,
NULL)) != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
if(replyLength != sizeof(uint32_t) + sizeof(uint32_t))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch"));
memcpy((uint8_t*)&prsOffset, reply.replyBody, sizeof(uint32_t));
return prsOffset;
}
return GetSwPrsOffset(h_FmPcd, hdr, indexPerHdr);
}
void FM_PCD_SetPrsStatistics(t_Handle h_FmPcd, bool enable)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
struct fman_prs_regs *PrsRegs;
SANITY_CHECK_RETURN(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
if(p_FmPcd->guestId != NCSW_MASTER_ID)
{
REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_SetPrsStatistics - guest mode!"));
return;
}
if(enable)
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->ppsc, FM_PCD_PRS_PPSC_ALL_PORTS);
else
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->ppsc, 0);
fman_prs_set_stst(PrsRegs, enable);
}
t_Error FM_PCD_PrsLoadSw(t_Handle h_FmPcd, t_FmPcdPrsSwParams *p_SwPrs)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
uint32_t *p_LoadTarget, tmpReg;
int i, j;
uint32_t *p_LoadTarget;
uint32_t *p_TmpCode;
int i;
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE);
@ -396,48 +357,53 @@ t_Error FM_PCD_PrsLoadSw(t_Handle h_FmPcd, t_FmPcdPrsSwParams *p_SwPrs)
SANITY_CHECK_RETURN_ERROR(p_SwPrs, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmPcd->enabled, E_INVALID_HANDLE);
if(p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_PrsLoadSw - guest mode!"));
if (p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM in guest-mode!"));
if(!p_SwPrs->override)
if (!p_SwPrs->override)
{
if(p_FmPcd->p_FmPcdPrs->p_CurrSwPrs > p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("SW parser base must be larger than current loaded code"));
}
if(p_SwPrs->size > FM_PCD_SW_PRS_SIZE - FM_PCD_PRS_SW_TAIL_SIZE - p_SwPrs->base*2)
else
p_FmPcd->p_FmPcdPrs->currLabel = 0;
if (p_SwPrs->size > FM_PCD_SW_PRS_SIZE - FM_PCD_PRS_SW_TAIL_SIZE - p_SwPrs->base*2)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_SwPrs->size may not be larger than MAX_SW_PRS_CODE_SIZE"));
if(p_SwPrs->size % 4)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_SwPrs->size must be divisible by 4"));
if (p_FmPcd->p_FmPcdPrs->currLabel + p_SwPrs->numOfLabels > FM_PCD_PRS_NUM_OF_LABELS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceeded number of labels allowed "));
p_TmpCode = (uint32_t *)XX_MallocSmart(ROUND_UP(p_SwPrs->size,4), 0, sizeof(uint32_t));
if (!p_TmpCode)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Tmp Sw-Parser code allocation FAILED"));
memset((uint8_t *)p_TmpCode, 0, ROUND_UP(p_SwPrs->size,4));
memcpy((uint8_t *)p_TmpCode, p_SwPrs->p_Code, p_SwPrs->size);
/* save sw parser labels */
if(p_SwPrs->override)
p_FmPcd->p_FmPcdPrs->currLabel = 0;
if(p_FmPcd->p_FmPcdPrs->currLabel+ p_SwPrs->numOfLabels > FM_PCD_PRS_NUM_OF_LABELS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceeded number of labels allowed "));
memcpy(&p_FmPcd->p_FmPcdPrs->labelsTable[p_FmPcd->p_FmPcdPrs->currLabel], p_SwPrs->labelsTable, p_SwPrs->numOfLabels*sizeof(t_FmPcdPrsLabelParams));
memcpy(&p_FmPcd->p_FmPcdPrs->labelsTable[p_FmPcd->p_FmPcdPrs->currLabel],
p_SwPrs->labelsTable,
p_SwPrs->numOfLabels*sizeof(t_FmPcdPrsLabelParams));
p_FmPcd->p_FmPcdPrs->currLabel += p_SwPrs->numOfLabels;
/* load sw parser code */
p_LoadTarget = p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4;
for(i=0;i<p_SwPrs->size/4;i++)
{
tmpReg = 0;
for(j =0;j<4;j++)
{
tmpReg <<= 8;
tmpReg |= *(p_SwPrs->p_Code+i*4+j);
}
WRITE_UINT32(*(p_LoadTarget + i), tmpReg);
}
p_FmPcd->p_FmPcdPrs->p_CurrSwPrs = p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4 + p_SwPrs->size/4;
for(i=0; i<DIV_CEIL(p_SwPrs->size, 4); i++)
WRITE_UINT32(p_LoadTarget[i], GET_UINT32(p_TmpCode[i]));
p_FmPcd->p_FmPcdPrs->p_CurrSwPrs =
p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4 + ROUND_UP(p_SwPrs->size,4);
/* copy data parameters */
for(i=0;i<FM_PCD_PRS_NUM_OF_HDRS;i++)
for (i=0;i<FM_PCD_PRS_NUM_OF_HDRS;i++)
WRITE_UINT32(*(p_FmPcd->p_FmPcdPrs->p_SwPrsCode+PRS_SW_DATA/4+i), p_SwPrs->swPrsDataParams[i]);
/* Clear last 4 bytes */
WRITE_UINT32(*(p_FmPcd->p_FmPcdPrs->p_SwPrsCode+(PRS_SW_DATA-FM_PCD_PRS_SW_TAIL_SIZE)/4), 0);
XX_FreeSmart(p_TmpCode);
return E_OK;
}
@ -455,63 +421,3 @@ t_Error FM_PCD_ConfigPrsMaxCycleLimit(t_Handle h_FmPcd,uint16_t value)
return E_OK;
}
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
t_Error FM_PCD_PrsDumpRegs(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
t_FmPcdIpcMsg msg;
DECLARE_DUMP;
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE);
if(p_FmPcd->guestId != NCSW_MASTER_ID)
{
memset(&msg, 0, sizeof(msg));
msg.msgId = FM_PCD_PRS_DUMP_REGS;
return XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId),
NULL,
NULL,
NULL,
NULL);
}
DUMP_SUBTITLE(("\n"));
DUMP_TITLE(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs, ("FmPcdPrsRegs Regs"));
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,rpclim);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,rpimac);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pmeec);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pevr);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pever);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pevfr);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,perr);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,perer);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,perfr);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,ppsc);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pds);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l2rrs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l3rrs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l4rrs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,srrs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l2rres);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l3rres);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l4rres);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,srres);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,spcs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,spscs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,hxscs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,mrcs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,mwcs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,mrscs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,mwscs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,fcscs);
return E_OK;
}
#endif /* (defined(DEBUG_ERRORS) && ... */

316
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_prs.h Normal file
View File

@ -0,0 +1,316 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_prs.h
@Description FM Parser private header
*//***************************************************************************/
#ifndef __FM_PRS_H
#define __FM_PRS_H
#include "std_ext.h"
/***********************************************************************/
/* SW parser IP_FRAG patch */
/***********************************************************************/
#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT))
#define SW_PRS_UDP_LITE_PATCH \
{\
0x31,0x52,0x00,0xDA,0xFC,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x50,0x2C,0x40,0x00,0x31,0x92,0x50,0x2C, \
0x00,0x88,0x18,0x2F,0x00,0x01,0x1B,0xFE,0x18,0x71, \
0x02,0x1F,0x00,0x08,0x00,0x83,0x02,0x1F,0x00,0x20, \
0x28,0x1B,0x00,0x05,0x29,0x1F,0x30,0xD0,0x60,0x4F, \
0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F,0x00,0x52, \
0x00,0x01,0x07,0x01,0x60,0x3B,0x00,0x00,0x30,0xD0, \
0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \
0x40,0x4C,0x00,0x00,0x02,0x8F,0x00,0x00,0x30,0xF2, \
0x00,0x06,0x18,0x5D,0x00,0x00,0x9F,0xFF,0x30,0xF2, \
0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0,0x00,0x52, \
0x00,0x08,0x28,0x1A,0x60,0x37,0x00,0x00,0x30,0xF2, \
0x18,0x5D,0x06,0x00,0x29,0x1E,0x30,0xF2,0x2F,0x0E, \
0x30,0x72,0x00,0x00,0x9B,0x8F,0x00,0x06,0x2F,0x0E, \
0x32,0xF1,0x32,0xB0,0x00,0x4F,0x00,0x57,0x00,0x28, \
0x00,0x00,0x97,0x9E,0x00,0x4E,0x30,0x72,0x00,0x06, \
0x2F,0x0E,0x32,0xC1,0x32,0xF0,0x00,0x4A,0x00,0x80, \
0x00,0x02,0x00,0x00,0x97,0x9E,0x40,0x7E,0x00,0x08, \
0x08,0x16,0x00,0x54,0x00,0x01,0x1B,0xFE,0x00,0x00, \
0x9F,0x9E,0x40,0xB3,0x00,0x00,0x02,0x1F,0x00,0x08, \
0x28,0x1B,0x30,0x73,0x29,0x1F,0x30,0xD0,0x60,0x9F, \
0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F,0x00,0x52, \
0x00,0x01,0x07,0x01,0x60,0x8B,0x00,0x00,0x30,0xD0, \
0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \
0x40,0x9C,0x00,0x00,0x02,0x8F,0x00,0x00,0x30,0xF2, \
0x00,0x06,0x18,0xAD,0x00,0x00,0x9F,0xFF,0x30,0xF2, \
0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0,0x00,0x52, \
0x00,0x08,0x28,0x1A,0x60,0x87,0x00,0x00,0x30,0xF2, \
0x18,0xAD,0x06,0x00,0x29,0x1E,0x30,0xF2,0x50,0xB3, \
0xFF,0xFF,0x18,0xB8,0x08,0x16,0x00,0x54,0x00,0x01, \
0x1B,0xFE,0x18,0xC5,0x32,0xF1,0x28,0x5D,0x32,0xF1, \
0x00,0x55,0x00,0x08,0x28,0x5F,0x00,0x00,0x8F,0x9F, \
0x29,0x33,0x08,0x16,0x00,0x49,0x00,0x01,0x1B,0xFF, \
0x00,0x01,0x1B,0xFF \
}
#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */
#if (DPAA_VERSION == 10)
/* Version: 106.1.9 */
#define SW_PRS_OFFLOAD_PATCH \
{ \
0x31,0x52,0x00,0xDA,0x0A,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x43,0x0A,0x00,0x00,0x00,0x01,0x1B,0xFE, \
0x00,0x00,0x99,0x00,0x53,0x13,0x00,0x00,0x00,0x00, \
0x9F,0x98,0x53,0x13,0x00,0x00,0x1B,0x23,0x33,0xF1, \
0x00,0xF9,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \
0x28,0x7F,0x00,0x03,0x00,0x02,0x00,0x00,0x00,0x01, \
0x32,0xC1,0x32,0xF0,0x00,0x4A,0x00,0x80,0x1F,0xFF, \
0x00,0x01,0x1B,0xFE,0x31,0x52,0x00,0xDA,0x06,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x43,0x2F,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x31,0x52,0x00,0xDA,0x00,0x40, \
0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x95,0x00,0x00, \
0x00,0x00,0x9B,0x8F,0x2F,0x0F,0x32,0xC1,0x00,0x55, \
0x00,0x28,0x28,0x43,0x30,0x7E,0x43,0x45,0x00,0x00, \
0x30,0x7E,0x43,0x45,0x00,0x3C,0x1B,0x5D,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00,0x83,0x8F, \
0x2F,0x0F,0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F, \
0x00,0x55,0x00,0x01,0x00,0x81,0x32,0x11,0x00,0x00, \
0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04,0x00,0x4D, \
0x28,0x43,0x06,0x00,0x1B,0x3E,0x30,0x7E,0x53,0x79, \
0x00,0x2B,0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x81, \
0x00,0x00,0x87,0x8F,0x28,0x23,0x06,0x00,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x55,0x00,0x01,0x00,0x81, \
0x32,0x11,0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01, \
0x01,0x04,0x00,0x4D,0x28,0x43,0x06,0x00,0x00,0x01, \
0x1B,0xFE,0x00,0x00,0x9B,0x8E,0x53,0x90,0x00,0x00, \
0x06,0x29,0x00,0x00,0x83,0x8F,0x28,0x23,0x06,0x00, \
0x06,0x29,0x32,0xC1,0x00,0x55,0x00,0x28,0x00,0x00, \
0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04,0x00,0x4D, \
0x28,0x43,0x06,0x00,0x00,0x01,0x1B,0xFE,0x32,0xC1, \
0x00,0x55,0x00,0x28,0x28,0x43,0x1B,0xCF,0x00,0x00, \
0x9B,0x8F,0x2F,0x0F,0x32,0xC1,0x00,0x55,0x00,0x28, \
0x28,0x43,0x30,0x7E,0x43,0xBF,0x00,0x2C,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00,0x87,0x8F, \
0x28,0x23,0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F, \
0x00,0x81,0x00,0x00,0x83,0x8F,0x2F,0x0F,0x06,0x00, \
0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x55,0x00,0x01, \
0x00,0x81,0x32,0x11,0x00,0x00,0x83,0x8E,0x00,0x50, \
0x00,0x01,0x01,0x04,0x00,0x4D,0x28,0x43,0x06,0x00, \
0x1B,0x9C,0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00, \
0x00,0x00,0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02, \
0x00,0x00,0x00,0x01,0x32,0xC1,0x32,0xF0,0x00,0x4A, \
0x00,0x80,0x1F,0xFF,0x00,0x01,0x1B,0xFE, \
}
#else
#define SW_PRS_OFFLOAD_PATCH \
{ \
0x31,0x52,0x00,0xDA,0x0E,0x4F,0x00,0x00,0x00,0x00, \
0x00,0x00,0x51,0x16,0x08,0x4B,0x31,0x53,0x00,0xFB, \
0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x29,0x2B, \
0x33,0xF1,0x00,0xFB,0x00,0xDF,0x00,0x00,0x00,0x00, \
0x00,0x00,0x28,0x7F,0x31,0x52,0x00,0xDA,0x0A,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x20,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x00,0x00,0x99,0x00,0x51,0x29, \
0x00,0x00,0x00,0x00,0x9F,0x98,0x51,0x29,0x00,0x00, \
0x19,0x44,0x09,0x5F,0x00,0x20,0x00,0x00,0x09,0x4F, \
0x00,0x20,0x00,0x00,0x34,0xB7,0x00,0xF9,0x00,0x00, \
0x01,0x00,0x00,0x00,0x00,0x00,0x2B,0x97,0x31,0xB3, \
0x29,0x8F,0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00, \
0x00,0x00,0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02, \
0x00,0x00,0x00,0x01,0x1B,0xFE,0x00,0x01,0x1B,0xFE, \
0x31,0x52,0x00,0xDA,0xFC,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x51,0x52,0x40,0x00,0x31,0x92,0x51,0x52, \
0x00,0x88,0x19,0x55,0x08,0x05,0x00,0x00,0x19,0x99, \
0x02,0x1F,0x00,0x08,0x00,0x83,0x02,0x1F,0x00,0x20, \
0x28,0x1B,0x00,0x05,0x29,0x1F,0x30,0xD0,0x61,0x75, \
0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F,0x00,0x52, \
0x00,0x01,0x07,0x01,0x61,0x61,0x00,0x00,0x30,0xD0, \
0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \
0x41,0x72,0x00,0x00,0x02,0x8F,0x00,0x00,0x30,0xF2, \
0x00,0x06,0x19,0x83,0x00,0x00,0x9F,0xFF,0x30,0xF2, \
0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0,0x00,0x52, \
0x00,0x08,0x28,0x1A,0x61,0x5D,0x00,0x00,0x30,0xF2, \
0x19,0x83,0x06,0x00,0x29,0x1E,0x30,0xF2,0x29,0x0E, \
0x30,0x72,0x00,0x00,0x9B,0x8F,0x00,0x06,0x29,0x0E, \
0x32,0xF1,0x32,0xB0,0x00,0x4F,0x00,0x57,0x00,0x28, \
0x00,0x00,0x97,0x9E,0x00,0x4E,0x30,0x72,0x00,0x06, \
0x29,0x0E,0x08,0x05,0x00,0x01,0x31,0x52,0x00,0xDA, \
0x0E,0x4F,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0xAF, \
0x04,0x4B,0x31,0x53,0x00,0xFB,0xFF,0xF0,0x00,0x00, \
0x00,0x00,0x00,0x00,0x29,0x2B,0x33,0xF1,0x00,0xFB, \
0x00,0xDF,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x7F, \
0x31,0x52,0x00,0xDA,0x06,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x41,0xB9,0x00,0x00,0x00,0x01,0x1B,0xFE, \
0x31,0x52,0x00,0xDA,0x00,0x40,0x00,0x00,0x00,0x00, \
0x00,0x00,0x42,0x06,0x00,0x00,0x00,0x00,0x9B,0x8F, \
0x28,0x01,0x32,0xC1,0x00,0x55,0x00,0x28,0x28,0x43, \
0x30,0x00,0x41,0xEB,0x00,0x2C,0x32,0x11,0x32,0xC0, \
0x00,0x4F,0x00,0x81,0x00,0x00,0x87,0x8F,0x28,0x23, \
0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x81, \
0x00,0x00,0x83,0x8F,0x28,0x01,0x06,0x00,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x55,0x00,0x01,0x00,0x81, \
0x32,0x11,0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01, \
0x01,0x04,0x00,0x4D,0x28,0x43,0x06,0x00,0x19,0xC8, \
0x09,0x5F,0x00,0x20,0x00,0x00,0x09,0x4F,0x00,0x20, \
0x00,0x00,0x34,0xB7,0x00,0xF9,0x00,0x00,0x01,0x00, \
0x00,0x00,0x00,0x00,0x2B,0x97,0x31,0xB3,0x29,0x8F, \
0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00,0x00,0x00, \
0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x30,0x50,0x52,0x0B,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x32,0xF1,0x32,0xC0,0x00,0x4F, \
0x00,0x81,0x00,0x02,0x00,0x00,0x97,0x9E,0x42,0x18, \
0x00,0x08,0x08,0x16,0x00,0x54,0x00,0x01,0x1B,0xFE, \
0x00,0x00,0x9F,0x9E,0x42,0x4D,0x00,0x00,0x02,0x1F, \
0x00,0x08,0x28,0x1B,0x30,0x73,0x29,0x1F,0x30,0xD0, \
0x62,0x39,0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F, \
0x00,0x52,0x00,0x01,0x07,0x01,0x62,0x25,0x00,0x00, \
0x30,0xD0,0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00, \
0x00,0x00,0x42,0x36,0x00,0x00,0x02,0x8F,0x00,0x00, \
0x30,0xF2,0x00,0x06,0x1A,0x47,0x00,0x00,0x9F,0xFF, \
0x30,0xF2,0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0, \
0x00,0x52,0x00,0x08,0x28,0x1A,0x62,0x21,0x00,0x00, \
0x30,0xF2,0x1A,0x47,0x06,0x00,0x29,0x1E,0x30,0xF2, \
0x52,0x4D,0xFF,0xFF,0x1A,0x52,0x08,0x16,0x00,0x54, \
0x00,0x01,0x1B,0xFE,0x1A,0x5F,0x32,0xF1,0x28,0x5D, \
0x32,0xF1,0x00,0x55,0x00,0x08,0x28,0x5F,0x00,0x00, \
0x8F,0x9F,0x29,0x33,0x08,0x16,0x00,0x49,0x00,0x01, \
0x1B,0xFF,0x00,0x01,0x1B,0xFF,0x31,0x52,0x00,0xDA, \
0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x6D, \
0x40,0x00,0x31,0x92,0x52,0x6D,0x00,0x88,0x1A,0x70, \
0x08,0x05,0x00,0x00,0x1A,0xB4,0x02,0x1F,0x00,0x08, \
0x00,0x83,0x02,0x1F,0x00,0x20,0x28,0x1B,0x00,0x05, \
0x29,0x1F,0x30,0xD0,0x62,0x90,0x00,0x07,0x00,0x05, \
0x00,0x00,0xC3,0x8F,0x00,0x52,0x00,0x01,0x07,0x01, \
0x62,0x7C,0x00,0x00,0x30,0xD0,0x00,0xDA,0x00,0x01, \
0x00,0x00,0x00,0x00,0x00,0x00,0x42,0x8D,0x00,0x00, \
0x02,0x8F,0x00,0x00,0x30,0xF2,0x00,0x06,0x1A,0x9E, \
0x00,0x00,0x9F,0xFF,0x30,0xF2,0x00,0x06,0x29,0x1E, \
0x07,0x08,0x30,0xD0,0x00,0x52,0x00,0x08,0x28,0x1A, \
0x62,0x78,0x00,0x00,0x30,0xF2,0x1A,0x9E,0x06,0x00, \
0x29,0x1E,0x30,0xF2,0x29,0x0E,0x30,0x72,0x00,0x00, \
0x9B,0x8F,0x00,0x06,0x29,0x0E,0x32,0xF1,0x32,0xB0, \
0x00,0x4F,0x00,0x57,0x00,0x28,0x00,0x00,0x97,0x9E, \
0x00,0x4E,0x30,0x72,0x00,0x06,0x29,0x0E,0x08,0x05, \
0x00,0x01,0x31,0x52,0x00,0xDA,0x0E,0x4F,0x00,0x00, \
0x00,0x00,0x00,0x00,0x52,0xCA,0x04,0x4B,0x31,0x53, \
0x00,0xFB,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, \
0x29,0x2B,0x33,0xF1,0x00,0xFB,0x00,0xDF,0x00,0x00, \
0x00,0x00,0x00,0x00,0x28,0x7F,0x31,0x52,0x00,0xDA, \
0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x42,0xD4, \
0x00,0x00,0x00,0x01,0x1B,0xFE,0x31,0x52,0x00,0xDA, \
0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x37, \
0x00,0x00,0x00,0x00,0x9B,0x8F,0x28,0x01,0x32,0xC1, \
0x00,0x55,0x00,0x28,0x28,0x43,0x30,0x00,0x42,0xEA, \
0x00,0x00,0x30,0x00,0x42,0xEA,0x00,0x3C,0x1B,0x02, \
0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00, \
0x83,0x8F,0x28,0x01,0x06,0x00,0x32,0x11,0x32,0xC0, \
0x00,0x4F,0x00,0x55,0x00,0x01,0x00,0x81,0x32,0x11, \
0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04, \
0x00,0x4D,0x28,0x43,0x06,0x00,0x1A,0xE3,0x30,0x00, \
0x43,0x20,0x00,0x2B,0x00,0x00,0x9B,0x8E,0x43,0x0E, \
0x00,0x00,0x32,0xC1,0x00,0x55,0x00,0x28,0x28,0x43, \
0x1B,0x1F,0x06,0x29,0x00,0x00,0x83,0x8F,0x28,0x23, \
0x06,0x00,0x06,0x29,0x32,0xC1,0x00,0x55,0x00,0x28, \
0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04, \
0x00,0x4D,0x28,0x43,0x06,0x00,0x1B,0x37,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00,0x87,0x8F, \
0x28,0x23,0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F, \
0x00,0x55,0x00,0x01,0x00,0x81,0x32,0x11,0x00,0x00, \
0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04,0x00,0x4D, \
0x28,0x43,0x06,0x00,0x30,0x50,0x53,0x3C,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x32,0xF1,0x32,0xC0,0x00,0x4F, \
0x00,0x81,0x00,0x02,0x00,0x00,0x97,0x9E,0x43,0x49, \
0x00,0x08,0x08,0x16,0x00,0x54,0x00,0x01,0x1B,0xFE, \
0x00,0x00,0x9F,0x9E,0x43,0x7E,0x00,0x00,0x02,0x1F, \
0x00,0x08,0x28,0x1B,0x30,0x73,0x29,0x1F,0x30,0xD0, \
0x63,0x6A,0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F, \
0x00,0x52,0x00,0x01,0x07,0x01,0x63,0x56,0x00,0x00, \
0x30,0xD0,0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00, \
0x00,0x00,0x43,0x67,0x00,0x00,0x02,0x8F,0x00,0x00, \
0x30,0xF2,0x00,0x06,0x1B,0x78,0x00,0x00,0x9F,0xFF, \
0x30,0xF2,0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0, \
0x00,0x52,0x00,0x08,0x28,0x1A,0x63,0x52,0x00,0x00, \
0x30,0xF2,0x1B,0x78,0x06,0x00,0x29,0x1E,0x30,0xF2, \
0x53,0x7E,0xFF,0xFF,0x1B,0x83,0x08,0x16,0x00,0x54, \
0x00,0x01,0x1B,0xFE,0x1B,0x90,0x32,0xF1,0x28,0x5D, \
0x32,0xF1,0x00,0x55,0x00,0x08,0x28,0x5F,0x00,0x00, \
0x8F,0x9F,0x29,0x33,0x08,0x16,0x00,0x49,0x00,0x01, \
0x1B,0xFF,0x00,0x01,0x1B,0xFF,0x08,0x07,0x00,0x02, \
0x00,0x00,0x8D,0x80,0x53,0x9C,0x00,0x01,0x30,0x71, \
0x00,0x55,0x00,0x01,0x28,0x0F,0x00,0x00,0x8D,0x00, \
0x53,0xA4,0x00,0x01,0x30,0x71,0x00,0x55,0x00,0x01, \
0x28,0x0F,0x00,0x00,0x83,0x8E,0x53,0xB9,0x00,0x00, \
0x00,0x00,0x86,0x08,0x30,0x71,0x00,0x7B,0x03,0xB9, \
0x33,0xB4,0x00,0xDA,0xFF,0xFF,0x00,0x0F,0x00,0x00, \
0x00,0x00,0x00,0x00,0x86,0x09,0x01,0x03,0x00,0x7D, \
0x03,0xB9,0x1B,0xC8,0x33,0xD1,0x00,0xF9,0x00,0x10, \
0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x7B,0x09,0x5F, \
0x00,0x1A,0x00,0x00,0x09,0x4F,0x00,0x1A,0x00,0x00, \
0x00,0x01,0x1B,0xFF,0x00,0x00,0x8C,0x00,0x53,0xF0, \
0x00,0x01,0x34,0xF5,0x00,0xFB,0xFF,0xFF,0x00,0x7F, \
0x00,0x00,0x00,0x00,0x2A,0x9F,0x00,0x00,0x93,0x8F, \
0x28,0x49,0x00,0x00,0x97,0x8F,0x28,0x4B,0x34,0x61, \
0x28,0x4D,0x34,0x71,0x28,0x4F,0x34,0xB7,0x00,0xF9, \
0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x2B,0x97, \
0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00,0x00,0x00, \
0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02,0x00,0x00, \
0x00,0x01,0x1B,0xFF,0x00,0x01,0x1B,0xFF, \
}
#endif /* (DPAA_VERSION == 10) */
/****************************/
/* Parser defines */
/****************************/
#define FM_PCD_PRS_SW_TAIL_SIZE 4 /**< Number of bytes that must be cleared at
the end of the SW parser area */
/* masks */
#define PRS_ERR_CAP 0x80000000
#define PRS_ERR_TYPE_DOUBLE 0x40000000
#define PRS_ERR_SINGLE_ECC_CNT_MASK 0x00FF0000
#define PRS_ERR_ADDR_MASK 0x000001FF
/* others */
#define PRS_MAX_CYCLE_LIMIT 8191
#define PRS_SW_DATA 0x00000800
#define PRS_REGS_OFFSET 0x00000840
#define GET_FM_PCD_PRS_PORT_ID(prsPortId,hardwarePortId) \
prsPortId = (uint8_t)(hardwarePortId & 0x0f)
#define GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId) \
bitMask = 0x80000000>>prsPortId
#endif /* __FM_PRS_H */

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sys/contrib/ncsw/Peripherals/FM/Pcd/fm_replic.c Normal file
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@ -0,0 +1,984 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_replic.c
@Description FM frame replicator
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "string_ext.h"
#include "debug_ext.h"
#include "fm_pcd_ext.h"
#include "fm_muram_ext.h"
#include "fm_common.h"
#include "fm_hc.h"
#include "fm_replic.h"
#include "fm_cc.h"
#include "list_ext.h"
/****************************************/
/* static functions */
/****************************************/
static uint8_t GetMemberPosition(t_FmPcdFrmReplicGroup *p_ReplicGroup,
uint32_t memberIndex,
bool isAddOperation)
{
uint8_t memberPosition;
uint32_t lastMemberIndex;
ASSERT_COND(p_ReplicGroup);
/* the last member index is different between add and remove operation -
in case of remove - this is exactly the last member index
in case of add - this is the last member index + 1 - e.g.
if we have 4 members, the index of the actual last member is 3(because the
index starts from 0) therefore in order to add a new member as the last
member we shall use memberIndex = 4 and not 3
*/
if (isAddOperation)
lastMemberIndex = p_ReplicGroup->numOfEntries;
else
lastMemberIndex = p_ReplicGroup->numOfEntries-1;
/* last */
if (memberIndex == lastMemberIndex)
memberPosition = FRM_REPLIC_LAST_MEMBER_INDEX;
else
{
/* first */
if (memberIndex == 0)
memberPosition = FRM_REPLIC_FIRST_MEMBER_INDEX;
else
{
/* middle */
ASSERT_COND(memberIndex < lastMemberIndex);
memberPosition = FRM_REPLIC_MIDDLE_MEMBER_INDEX;
}
}
return memberPosition;
}
static t_Error MemberCheckParams(t_Handle h_FmPcd,
t_FmPcdCcNextEngineParams *p_MemberParams)
{
t_Error err;
if ((p_MemberParams->nextEngine != e_FM_PCD_DONE) &&
(p_MemberParams->nextEngine != e_FM_PCD_KG) &&
(p_MemberParams->nextEngine != e_FM_PCD_PLCR))
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Next engine of a member should be MatchTable(cc) or Done or Policer"));
/* check the regular parameters of the next engine */
err = ValidateNextEngineParams(h_FmPcd, p_MemberParams, e_FM_PCD_CC_STATS_MODE_NONE);
if (err)
RETURN_ERROR(MAJOR, err, ("member next engine parameters"));
return E_OK;
}
static t_Error CheckParams(t_Handle h_FmPcd,
t_FmPcdFrmReplicGroupParams *p_ReplicGroupParam)
{
int i;
t_Error err;
/* check that max num of entries is at least 2 */
if (!IN_RANGE(2, p_ReplicGroupParam->maxNumOfEntries, FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES))
RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, ("maxNumOfEntries in the frame replicator parameters should be 2-%d",FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES));
/* check that number of entries is greater than zero */
if (!p_ReplicGroupParam->numOfEntries)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOFEntries in the frame replicator group should be greater than zero"));
/* check that max num of entries is equal or greater than number of entries */
if (p_ReplicGroupParam->maxNumOfEntries < p_ReplicGroupParam->numOfEntries)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("maxNumOfEntries should be equal or greater than numOfEntries"));
for (i=0; i<p_ReplicGroupParam->numOfEntries; i++)
{
err = MemberCheckParams(h_FmPcd, &p_ReplicGroupParam->nextEngineParams[i]);
if (err)
RETURN_ERROR(MAJOR, err, ("member check parameters"));
}
return E_OK;
}
static t_FmPcdFrmReplicMember *GetAvailableMember(t_FmPcdFrmReplicGroup *p_ReplicGroup)
{
t_FmPcdFrmReplicMember *p_ReplicMember = NULL;
t_List *p_Next;
if (!LIST_IsEmpty(&p_ReplicGroup->availableMembersList))
{
p_Next = LIST_FIRST(&p_ReplicGroup->availableMembersList);
p_ReplicMember = LIST_OBJECT(p_Next, t_FmPcdFrmReplicMember, node);
ASSERT_COND(p_ReplicMember);
LIST_DelAndInit(p_Next);
}
return p_ReplicMember;
}
static void PutAvailableMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_ReplicMember)
{
LIST_AddToTail(&p_ReplicMember->node, &p_ReplicGroup->availableMembersList);
}
static void AddMemberToList(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_CurrentMember,
t_List *p_ListHead)
{
LIST_Add(&p_CurrentMember->node, p_ListHead);
p_ReplicGroup->numOfEntries++;
}
static void RemoveMemberFromList(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_CurrentMember)
{
ASSERT_COND(p_ReplicGroup->numOfEntries);
LIST_DelAndInit(&p_CurrentMember->node);
p_ReplicGroup->numOfEntries--;
}
static void LinkSourceToMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_AdOfTypeContLookup *p_SourceTd,
t_FmPcdFrmReplicMember *p_ReplicMember)
{
t_FmPcd *p_FmPcd;
ASSERT_COND(p_SourceTd);
ASSERT_COND(p_ReplicMember);
ASSERT_COND(p_ReplicGroup);
ASSERT_COND(p_ReplicGroup->h_FmPcd);
/* Link the first member in the group to the source TD */
p_FmPcd = p_ReplicGroup->h_FmPcd;
WRITE_UINT32(p_SourceTd->matchTblPtr,
(uint32_t)(XX_VirtToPhys(p_ReplicMember->p_MemberAd) -
p_FmPcd->physicalMuramBase));
}
static void LinkMemberToMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_CurrentMember,
t_FmPcdFrmReplicMember *p_NextMember)
{
t_AdOfTypeResult *p_CurrReplicAd = (t_AdOfTypeResult*)p_CurrentMember->p_MemberAd;
t_AdOfTypeResult *p_NextReplicAd = NULL;
t_FmPcd *p_FmPcd;
uint32_t offset = 0;
/* Check if the next member exists or it's NULL (- means that this is the last member) */
if (p_NextMember)
{
p_NextReplicAd = (t_AdOfTypeResult*)p_NextMember->p_MemberAd;
p_FmPcd = p_ReplicGroup->h_FmPcd;
offset = (XX_VirtToPhys(p_NextReplicAd) - (p_FmPcd->physicalMuramBase));
offset = ((offset>>NEXT_FRM_REPLIC_ADDR_SHIFT)<< NEXT_FRM_REPLIC_MEMBER_INDEX_SHIFT);
}
/* link the current AD to point to the AD of the next member */
WRITE_UINT32(p_CurrReplicAd->res, offset);
}
static t_Error ModifyDescriptor(t_FmPcdFrmReplicGroup *p_ReplicGroup,
void *p_OldDescriptor,
void *p_NewDescriptor)
{
t_Handle h_Hc;
t_Error err;
t_FmPcd *p_FmPcd;
ASSERT_COND(p_ReplicGroup);
ASSERT_COND(p_ReplicGroup->h_FmPcd);
ASSERT_COND(p_OldDescriptor);
ASSERT_COND(p_NewDescriptor);
p_FmPcd = p_ReplicGroup->h_FmPcd;
h_Hc = FmPcdGetHcHandle(p_FmPcd);
if (!h_Hc)
RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("Host command"));
err = FmHcPcdCcDoDynamicChange(h_Hc,
(uint32_t)(XX_VirtToPhys(p_OldDescriptor) - p_FmPcd->physicalMuramBase),
(uint32_t)(XX_VirtToPhys(p_NewDescriptor) - p_FmPcd->physicalMuramBase));
if (err)
RETURN_ERROR(MAJOR, err, ("Dynamic change host command"));
return E_OK;
}
static void FillReplicAdOfTypeResult(void *p_ReplicAd, bool last)
{
t_AdOfTypeResult *p_CurrReplicAd = (t_AdOfTypeResult*)p_ReplicAd;
uint32_t tmp;
tmp = GET_UINT32(p_CurrReplicAd->plcrProfile);
if (last)
/* clear the NL bit in case it's the last member in the group*/
WRITE_UINT32(p_CurrReplicAd->plcrProfile,(tmp & ~FRM_REPLIC_NL_BIT));
else
/* set the NL bit in case it's not the last member in the group */
WRITE_UINT32(p_CurrReplicAd->plcrProfile, (tmp |FRM_REPLIC_NL_BIT));
/* set FR bit in the action descriptor */
tmp = GET_UINT32(p_CurrReplicAd->nia);
WRITE_UINT32(p_CurrReplicAd->nia,
(tmp | FRM_REPLIC_FR_BIT | FM_PCD_AD_RESULT_EXTENDED_MODE ));
}
static void BuildSourceTd(void *p_Ad)
{
t_AdOfTypeContLookup *p_SourceTd;
ASSERT_COND(p_Ad);
p_SourceTd = (t_AdOfTypeContLookup *)p_Ad;
IOMemSet32((uint8_t*)p_SourceTd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
/* initialize the source table descriptor */
WRITE_UINT32(p_SourceTd->ccAdBase, FM_PCD_AD_CONT_LOOKUP_TYPE);
WRITE_UINT32(p_SourceTd->pcAndOffsets, FRM_REPLIC_SOURCE_TD_OPCODE);
}
static t_Error BuildShadowAndModifyDescriptor(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_NextMember,
t_FmPcdFrmReplicMember *p_CurrentMember,
bool sourceDescriptor,
bool last)
{
t_FmPcd *p_FmPcd;
t_FmPcdFrmReplicMember shadowMember;
t_Error err;
ASSERT_COND(p_ReplicGroup);
ASSERT_COND(p_ReplicGroup->h_FmPcd);
p_FmPcd = p_ReplicGroup->h_FmPcd;
ASSERT_COND(p_FmPcd->p_CcShadow);
if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock))
return ERROR_CODE(E_BUSY);
if (sourceDescriptor)
{
BuildSourceTd(p_FmPcd->p_CcShadow);
LinkSourceToMember(p_ReplicGroup, p_FmPcd->p_CcShadow, p_NextMember);
/* Modify the source table descriptor according to the prepared shadow descriptor */
err = ModifyDescriptor(p_ReplicGroup,
p_ReplicGroup->p_SourceTd,
p_FmPcd->p_CcShadow/* new prepared source td */);
RELEASE_LOCK(p_FmPcd->shadowLock);
if (err)
RETURN_ERROR(MAJOR, err, ("Modify source Descriptor in BuildShadowAndModifyDescriptor"));
}
else
{
IO2IOCpy32(p_FmPcd->p_CcShadow,
p_CurrentMember->p_MemberAd,
FM_PCD_CC_AD_ENTRY_SIZE);
/* update the last bit in the shadow ad */
FillReplicAdOfTypeResult(p_FmPcd->p_CcShadow, last);
shadowMember.p_MemberAd = p_FmPcd->p_CcShadow;
/* update the next FR member index */
LinkMemberToMember(p_ReplicGroup, &shadowMember, p_NextMember);
/* Modify the next member according to the prepared shadow descriptor */
err = ModifyDescriptor(p_ReplicGroup,
p_CurrentMember->p_MemberAd,
p_FmPcd->p_CcShadow);
RELEASE_LOCK(p_FmPcd->shadowLock);
if (err)
RETURN_ERROR(MAJOR, err, ("Modify Descriptor in BuildShadowAndModifyDescriptor"));
}
return E_OK;
}
static t_FmPcdFrmReplicMember* GetMemberByIndex(t_FmPcdFrmReplicGroup *p_ReplicGroup,
uint16_t memberIndex)
{
int i=0;
t_List *p_Pos;
t_FmPcdFrmReplicMember *p_Member = NULL;
LIST_FOR_EACH(p_Pos, &p_ReplicGroup->membersList)
{
if (i == memberIndex)
{
p_Member = LIST_OBJECT(p_Pos, t_FmPcdFrmReplicMember, node);
return p_Member;
}
i++;
}
return p_Member;
}
static t_Error AllocMember(t_FmPcdFrmReplicGroup *p_ReplicGroup)
{
t_FmPcdFrmReplicMember *p_CurrentMember;
t_Handle h_Muram;
ASSERT_COND(p_ReplicGroup);
h_Muram = FmPcdGetMuramHandle(p_ReplicGroup->h_FmPcd);
ASSERT_COND(h_Muram);
/* Initialize an internal structure of a member to add to the available members list */
p_CurrentMember = (t_FmPcdFrmReplicMember *)XX_Malloc(sizeof(t_FmPcdFrmReplicMember));
if (!p_CurrentMember)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Frame replicator member"));
memset(p_CurrentMember, 0 ,sizeof(t_FmPcdFrmReplicMember));
/* Allocate the member AD */
p_CurrentMember->p_MemberAd =
(t_AdOfTypeResult*)FM_MURAM_AllocMem(h_Muram,
FM_PCD_CC_AD_ENTRY_SIZE,
FM_PCD_CC_AD_TABLE_ALIGN);
if (!p_CurrentMember->p_MemberAd)
{
XX_Free(p_CurrentMember);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("member AD table"));
}
IOMemSet32((uint8_t*)p_CurrentMember->p_MemberAd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
/* Add the new member to the available members list */
LIST_AddToTail(&p_CurrentMember->node, &(p_ReplicGroup->availableMembersList));
return E_OK;
}
static t_FmPcdFrmReplicMember* InitMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdCcNextEngineParams *p_MemberParams,
bool last)
{
t_FmPcdFrmReplicMember *p_CurrentMember = NULL;
ASSERT_COND(p_ReplicGroup);
/* Get an available member from the internal members list */
p_CurrentMember = GetAvailableMember(p_ReplicGroup);
if (!p_CurrentMember)
{
REPORT_ERROR(MAJOR, E_NOT_FOUND, ("Available member"));
return NULL;
}
p_CurrentMember->h_Manip = NULL;
/* clear the Ad of the new member */
IOMemSet32((uint8_t*)p_CurrentMember->p_MemberAd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
INIT_LIST(&p_CurrentMember->node);
/* Initialize the Ad of the member */
NextStepAd(p_CurrentMember->p_MemberAd,
NULL,
p_MemberParams,
p_ReplicGroup->h_FmPcd);
/* save Manip handle (for free needs) */
if (p_MemberParams->h_Manip)
p_CurrentMember->h_Manip = p_MemberParams->h_Manip;
/* Initialize the relevant frame replicator fields in the AD */
FillReplicAdOfTypeResult(p_CurrentMember->p_MemberAd, last);
return p_CurrentMember;
}
static void FreeMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_Member)
{
/* Note: Can't free the member AD just returns the member to the available
member list - therefore only memset the AD */
/* zero the AD */
IOMemSet32(p_Member->p_MemberAd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
/* return the member to the available members list */
PutAvailableMember(p_ReplicGroup, p_Member);
}
static t_Error RemoveMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
uint16_t memberIndex)
{
t_FmPcd *p_FmPcd = NULL;
t_FmPcdFrmReplicMember *p_CurrentMember = NULL, *p_PreviousMember = NULL, *p_NextMember = NULL;
t_Error err;
uint8_t memberPosition;
p_FmPcd = p_ReplicGroup->h_FmPcd;
ASSERT_COND(p_FmPcd);
UNUSED(p_FmPcd);
p_CurrentMember = GetMemberByIndex(p_ReplicGroup, memberIndex);
ASSERT_COND(p_CurrentMember);
/* determine the member position in the group */
memberPosition = GetMemberPosition(p_ReplicGroup,
memberIndex,
FALSE/*remove operation*/);
switch (memberPosition)
{
case FRM_REPLIC_FIRST_MEMBER_INDEX:
p_NextMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex+1));
ASSERT_COND(p_NextMember);
/* update the source td itself by using a host command */
err = BuildShadowAndModifyDescriptor(p_ReplicGroup,
p_NextMember,
NULL,
TRUE/*sourceDescriptor*/,
FALSE/*last*/);
break;
case FRM_REPLIC_MIDDLE_MEMBER_INDEX:
p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1));
ASSERT_COND(p_PreviousMember);
p_NextMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex+1));
ASSERT_COND(p_NextMember);
err = BuildShadowAndModifyDescriptor(p_ReplicGroup,
p_NextMember,
p_PreviousMember,
FALSE/*sourceDescriptor*/,
FALSE/*last*/);
break;
case FRM_REPLIC_LAST_MEMBER_INDEX:
p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1));
ASSERT_COND(p_PreviousMember);
err = BuildShadowAndModifyDescriptor(p_ReplicGroup,
NULL,
p_PreviousMember,
FALSE/*sourceDescriptor*/,
TRUE/*last*/);
break;
default:
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("member position in remove member"));
}
if (err)
RETURN_ERROR(MAJOR, err, NO_MSG);
if (p_CurrentMember->h_Manip)
{
FmPcdManipUpdateOwner(p_CurrentMember->h_Manip, FALSE);
p_CurrentMember->h_Manip = NULL;
}
/* remove the member from the driver internal members list */
RemoveMemberFromList(p_ReplicGroup, p_CurrentMember);
/* return the member to the available members list */
FreeMember(p_ReplicGroup, p_CurrentMember);
return E_OK;
}
static void DeleteGroup(t_FmPcdFrmReplicGroup *p_ReplicGroup)
{
int i, j;
t_Handle h_Muram;
t_FmPcdFrmReplicMember *p_Member, *p_CurrentMember;
if (p_ReplicGroup)
{
ASSERT_COND(p_ReplicGroup->h_FmPcd);
h_Muram = FmPcdGetMuramHandle(p_ReplicGroup->h_FmPcd);
ASSERT_COND(h_Muram);
/* free the source table descriptor */
if (p_ReplicGroup->p_SourceTd)
{
FM_MURAM_FreeMem(h_Muram, p_ReplicGroup->p_SourceTd);
p_ReplicGroup->p_SourceTd = NULL;
}
/* Remove all members from the members linked list (hw and sw) and
return the members to the available members list */
if (p_ReplicGroup->numOfEntries)
{
j = p_ReplicGroup->numOfEntries-1;
/* manually removal of the member because there are no owners of
this group */
for (i=j; i>=0; i--)
{
p_CurrentMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)i/*memberIndex*/);
ASSERT_COND(p_CurrentMember);
if (p_CurrentMember->h_Manip)
{
FmPcdManipUpdateOwner(p_CurrentMember->h_Manip, FALSE);
p_CurrentMember->h_Manip = NULL;
}
/* remove the member from the internal driver members list */
RemoveMemberFromList(p_ReplicGroup, p_CurrentMember);
/* return the member to the available members list */
FreeMember(p_ReplicGroup, p_CurrentMember);
}
}
/* Free members AD */
for (i=0; i<p_ReplicGroup->maxNumOfEntries; i++)
{
p_Member = GetAvailableMember(p_ReplicGroup);
ASSERT_COND(p_Member);
if (p_Member->p_MemberAd)
{
FM_MURAM_FreeMem(h_Muram, p_Member->p_MemberAd);
p_Member->p_MemberAd = NULL;
}
XX_Free(p_Member);
}
/* release the group lock */
if (p_ReplicGroup->p_Lock)
FmPcdReleaseLock(p_ReplicGroup->h_FmPcd, p_ReplicGroup->p_Lock);
/* free the replicator group */
XX_Free(p_ReplicGroup);
}
}
/*****************************************************************************/
/* Inter-module API routines */
/*****************************************************************************/
/* NOTE: the inter-module routines are locked by cc in case of using them */
void * FrmReplicGroupGetSourceTableDescriptor(t_Handle h_ReplicGroup)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
ASSERT_COND(p_ReplicGroup);
return (p_ReplicGroup->p_SourceTd);
}
void FrmReplicGroupUpdateAd(t_Handle h_ReplicGroup,
void *p_Ad,
t_Handle *h_AdNew)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
t_AdOfTypeResult *p_AdResult = (t_AdOfTypeResult*)p_Ad;
t_FmPcd *p_FmPcd;
ASSERT_COND(p_ReplicGroup);
p_FmPcd = p_ReplicGroup->h_FmPcd;
/* build a bypass ad */
WRITE_UINT32(p_AdResult->fqid, FM_PCD_AD_BYPASS_TYPE |
(uint32_t)((XX_VirtToPhys(p_ReplicGroup->p_SourceTd)) - p_FmPcd->physicalMuramBase));
*h_AdNew = NULL;
}
void FrmReplicGroupUpdateOwner(t_Handle h_ReplicGroup,
bool add)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
ASSERT_COND(p_ReplicGroup);
/* update the group owner counter */
if (add)
p_ReplicGroup->owners++;
else
{
ASSERT_COND(p_ReplicGroup->owners);
p_ReplicGroup->owners--;
}
}
t_Error FrmReplicGroupTryLock(t_Handle h_ReplicGroup)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
ASSERT_COND(h_ReplicGroup);
if (FmPcdLockTryLock(p_ReplicGroup->p_Lock))
return E_OK;
return ERROR_CODE(E_BUSY);
}
void FrmReplicGroupUnlock(t_Handle h_ReplicGroup)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
ASSERT_COND(h_ReplicGroup);
FmPcdLockUnlock(p_ReplicGroup->p_Lock);
}
/*********************** End of inter-module routines ************************/
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle FM_PCD_FrmReplicSetGroup(t_Handle h_FmPcd,
t_FmPcdFrmReplicGroupParams *p_ReplicGroupParam)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup;
t_FmPcdFrmReplicMember *p_CurrentMember, *p_NextMember = NULL;
int i;
t_Error err;
bool last = FALSE;
t_Handle h_Muram;
SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_ReplicGroupParam, E_INVALID_HANDLE, NULL);
if (!FmPcdIsAdvancedOffloadSupported(h_FmPcd))
{
REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Advanced-offload must be enabled"));
return NULL;
}
err = CheckParams(h_FmPcd, p_ReplicGroupParam);
if (err)
{
REPORT_ERROR(MAJOR, err, (NO_MSG));
return NULL;
}
p_ReplicGroup = (t_FmPcdFrmReplicGroup*)XX_Malloc(sizeof(t_FmPcdFrmReplicGroup));
if (!p_ReplicGroup)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("No memory"));
return NULL;
}
memset(p_ReplicGroup, 0, sizeof(t_FmPcdFrmReplicGroup));
/* initialize lists for internal driver use */
INIT_LIST(&p_ReplicGroup->availableMembersList);
INIT_LIST(&p_ReplicGroup->membersList);
p_ReplicGroup->h_FmPcd = h_FmPcd;
h_Muram = FmPcdGetMuramHandle(p_ReplicGroup->h_FmPcd);
ASSERT_COND(h_Muram);
/* initialize the group lock */
p_ReplicGroup->p_Lock = FmPcdAcquireLock(p_ReplicGroup->h_FmPcd);
if (!p_ReplicGroup->p_Lock)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Replic group lock"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
/* Allocate the frame replicator source table descriptor */
p_ReplicGroup->p_SourceTd =
(t_Handle)FM_MURAM_AllocMem(h_Muram,
FM_PCD_CC_AD_ENTRY_SIZE,
FM_PCD_CC_AD_TABLE_ALIGN);
if (!p_ReplicGroup->p_SourceTd)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("frame replicator source table descriptor"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
/* update the shadow size - required for the host commands */
err = FmPcdUpdateCcShadow(p_ReplicGroup->h_FmPcd,
FM_PCD_CC_AD_ENTRY_SIZE,
FM_PCD_CC_AD_TABLE_ALIGN);
if (err)
{
REPORT_ERROR(MAJOR, err, ("Update CC shadow"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
p_ReplicGroup->maxNumOfEntries = p_ReplicGroupParam->maxNumOfEntries;
/* Allocate the maximal number of members ADs and Statistics AD for the group
It prevents allocation of Muram in run-time */
for (i=0; i<p_ReplicGroup->maxNumOfEntries; i++)
{
err = AllocMember(p_ReplicGroup);
if (err)
{
REPORT_ERROR(MAJOR, err, ("allocate a new member"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
}
/* Initialize the members linked lists:
(hw - the one that is used by the FMan controller and
sw - the one that is managed by the driver internally) */
for (i=(p_ReplicGroupParam->numOfEntries-1); i>=0; i--)
{
/* check if this is the last member in the group */
if (i == (p_ReplicGroupParam->numOfEntries-1))
last = TRUE;
else
last = FALSE;
/* Initialize a new member */
p_CurrentMember = InitMember(p_ReplicGroup,
&(p_ReplicGroupParam->nextEngineParams[i]),
last);
if (!p_CurrentMember)
{
REPORT_ERROR(MAJOR, E_INVALID_HANDLE, ("No available member"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
/* Build the members group - link two consecutive members in the hw linked list */
LinkMemberToMember(p_ReplicGroup, p_CurrentMember, p_NextMember);
/* update the driver internal members list to be compatible to the hw members linked list */
AddMemberToList(p_ReplicGroup, p_CurrentMember, &p_ReplicGroup->membersList);
p_NextMember = p_CurrentMember;
}
/* initialize the source table descriptor */
BuildSourceTd(p_ReplicGroup->p_SourceTd);
/* link the source table descriptor to point to the first member in the group */
LinkSourceToMember(p_ReplicGroup, p_ReplicGroup->p_SourceTd, p_NextMember);
return p_ReplicGroup;
}
t_Error FM_PCD_FrmReplicDeleteGroup(t_Handle h_ReplicGroup)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
SANITY_CHECK_RETURN_ERROR(p_ReplicGroup, E_INVALID_HANDLE);
if (p_ReplicGroup->owners)
RETURN_ERROR(MAJOR,
E_INVALID_STATE,
("the group has owners and can't be deleted"));
DeleteGroup(p_ReplicGroup);
return E_OK;
}
/*****************************************************************************/
/* API Run-time Frame replicator Control unit functions */
/*****************************************************************************/
t_Error FM_PCD_FrmReplicAddMember(t_Handle h_ReplicGroup,
uint16_t memberIndex,
t_FmPcdCcNextEngineParams *p_MemberParams)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup*) h_ReplicGroup;
t_FmPcdFrmReplicMember *p_NewMember, *p_CurrentMember = NULL, *p_PreviousMember = NULL;
t_Error err;
uint8_t memberPosition;
SANITY_CHECK_RETURN_ERROR(p_ReplicGroup, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_MemberParams, E_INVALID_HANDLE);
/* group lock */
err = FrmReplicGroupTryLock(p_ReplicGroup);
if (GET_ERROR_TYPE(err) == E_BUSY)
return ERROR_CODE(E_BUSY);
if (memberIndex > p_ReplicGroup->numOfEntries)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("memberIndex is greater than the members in the list"));
}
if (memberIndex >= p_ReplicGroup->maxNumOfEntries)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("memberIndex is greater than the allowed number of members in the group"));
}
if ((p_ReplicGroup->numOfEntries + 1) > FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_VALUE,
("numOfEntries with new entry can not be larger than %d\n",
FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES));
}
err = MemberCheckParams(p_ReplicGroup->h_FmPcd, p_MemberParams);
if (err)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, err, ("member check parameters in add operation"));
}
/* determine the member position in the group */
memberPosition = GetMemberPosition(p_ReplicGroup,
memberIndex,
TRUE/* add operation */);
/* Initialize a new member */
p_NewMember = InitMember(p_ReplicGroup,
p_MemberParams,
(memberPosition == FRM_REPLIC_LAST_MEMBER_INDEX ? TRUE : FALSE));
if (!p_NewMember)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("No available member"));
}
switch (memberPosition)
{
case FRM_REPLIC_FIRST_MEMBER_INDEX:
p_CurrentMember = GetMemberByIndex(p_ReplicGroup, memberIndex);
ASSERT_COND(p_CurrentMember);
LinkMemberToMember(p_ReplicGroup, p_NewMember, p_CurrentMember);
/* update the internal group source TD */
LinkSourceToMember(p_ReplicGroup,
p_ReplicGroup->p_SourceTd,
p_NewMember);
/* add member to the internal sw member list */
AddMemberToList(p_ReplicGroup,
p_NewMember,
&p_ReplicGroup->membersList);
break;
case FRM_REPLIC_MIDDLE_MEMBER_INDEX:
p_CurrentMember = GetMemberByIndex(p_ReplicGroup, memberIndex);
ASSERT_COND(p_CurrentMember);
p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1));
ASSERT_COND(p_PreviousMember);
LinkMemberToMember(p_ReplicGroup, p_NewMember, p_CurrentMember);
LinkMemberToMember(p_ReplicGroup, p_PreviousMember, p_NewMember);
AddMemberToList(p_ReplicGroup, p_NewMember, &p_PreviousMember->node);
break;
case FRM_REPLIC_LAST_MEMBER_INDEX:
p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1));
ASSERT_COND(p_PreviousMember);
LinkMemberToMember(p_ReplicGroup, p_PreviousMember, p_NewMember);
FillReplicAdOfTypeResult(p_PreviousMember->p_MemberAd, FALSE/*last*/);
/* add the new member to the internal sw member list */
AddMemberToList(p_ReplicGroup, p_NewMember, &p_PreviousMember->node);
break;
default:
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("member position in add member"));
}
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
return E_OK;
}
t_Error FM_PCD_FrmReplicRemoveMember(t_Handle h_ReplicGroup,
uint16_t memberIndex)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup*) h_ReplicGroup;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_ReplicGroup, E_INVALID_HANDLE);
/* lock */
err = FrmReplicGroupTryLock(p_ReplicGroup);
if (GET_ERROR_TYPE(err) == E_BUSY)
return ERROR_CODE(E_BUSY);
if (memberIndex >= p_ReplicGroup->numOfEntries)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("member index to remove"));
/* Design decision: group must contain at least one member
No possibility to remove the last member from the group */
if (p_ReplicGroup->numOfEntries == 1)
RETURN_ERROR(MAJOR, E_CONFLICT, ("Can't remove the last member. At least one member should be related to a group."));
err = RemoveMember(p_ReplicGroup, memberIndex);
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
switch (GET_ERROR_TYPE(err))
{
case E_OK:
return E_OK;
case E_BUSY:
DBG(TRACE, ("E_BUSY error"));
return ERROR_CODE(E_BUSY);
default:
RETURN_ERROR(MAJOR, err, NO_MSG);
}
}
/*********************** End of API routines ************************/

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_replic.h
@Description FM frame replicator
*//***************************************************************************/
#ifndef __FM_REPLIC_H
#define __FM_REPLIC_H
#include "std_ext.h"
#include "error_ext.h"
#define FRM_REPLIC_SOURCE_TD_OPCODE 0x75
#define NEXT_FRM_REPLIC_ADDR_SHIFT 4
#define NEXT_FRM_REPLIC_MEMBER_INDEX_SHIFT 16
#define FRM_REPLIC_FR_BIT 0x08000000
#define FRM_REPLIC_NL_BIT 0x10000000
#define FRM_REPLIC_INVALID_MEMBER_INDEX 0xffff
#define FRM_REPLIC_FIRST_MEMBER_INDEX 0
#define FRM_REPLIC_MIDDLE_MEMBER_INDEX 1
#define FRM_REPLIC_LAST_MEMBER_INDEX 2
#define SOURCE_TD_ITSELF_OPTION 0x01
#define SOURCE_TD_COPY_OPTION 0x02
#define SOURCE_TD_ITSELF_AND_COPY_OPTION SOURCE_TD_ITSELF_OPTION | SOURCE_TD_COPY_OPTION
#define SOURCE_TD_NONE 0x04
/*typedef enum e_SourceTdOption
{
e_SOURCE_TD_NONE = 0,
e_SOURCE_TD_ITSELF_OPTION = 1,
e_SOURCE_TD_COPY_OPTION = 2,
e_SOURCE_TD_ITSELF_AND_COPY_OPTION = e_SOURCE_TD_ITSELF_OPTION | e_SOURCE_TD_COPY_OPTION
} e_SourceTdOption;
*/
typedef struct
{
volatile uint32_t type;
volatile uint32_t frGroupPointer;
volatile uint32_t operationCode;
volatile uint32_t reserved;
} t_FrmReplicGroupSourceAd;
typedef struct t_FmPcdFrmReplicMember
{
void *p_MemberAd; /**< pointer to the member AD */
void *p_StatisticsAd;/**< pointer to the statistics AD of the member */
t_Handle h_Manip; /**< manip handle - need for free routines */
t_List node;
} t_FmPcdFrmReplicMember;
typedef struct t_FmPcdFrmReplicGroup
{
t_Handle h_FmPcd;
uint8_t maxNumOfEntries;/**< maximal number of members in the group */
uint8_t numOfEntries; /**< actual number of members in the group */
uint16_t owners; /**< how many keys share this frame replicator group */
void *p_SourceTd; /**< pointer to the frame replicator source table descriptor */
t_List membersList; /**< the members list - should reflect the order of the members as in the hw linked list*/
t_List availableMembersList;/**< list of all the available members in the group */
t_FmPcdLock *p_Lock;
} t_FmPcdFrmReplicGroup;
#endif /* __FM_REPLIC_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_kg.h"
/****************************************/
/* static functions */
/****************************************/
static uint32_t build_ar_bind_scheme(uint8_t hwport_id, bool write)
{
uint32_t rw;
rw = write ? (uint32_t)FM_KG_KGAR_WRITE : (uint32_t)FM_KG_KGAR_READ;
return (uint32_t)(FM_KG_KGAR_GO |
rw |
FM_PCD_KG_KGAR_SEL_PORT_ENTRY |
hwport_id |
FM_PCD_KG_KGAR_SEL_PORT_WSEL_SP);
}
static void clear_pe_all_scheme(struct fman_kg_regs *regs, uint8_t hwport_id)
{
uint32_t ar;
fman_kg_write_sp(regs, 0xffffffff, 0);
ar = build_ar_bind_scheme(hwport_id, TRUE);
fman_kg_write_ar_wait(regs, ar);
}
static uint32_t build_ar_bind_cls_plan(uint8_t hwport_id, bool write)
{
uint32_t rw;
rw = write ? (uint32_t)FM_KG_KGAR_WRITE : (uint32_t)FM_KG_KGAR_READ;
return (uint32_t)(FM_KG_KGAR_GO |
rw |
FM_PCD_KG_KGAR_SEL_PORT_ENTRY |
hwport_id |
FM_PCD_KG_KGAR_SEL_PORT_WSEL_CPP);
}
static void clear_pe_all_cls_plan(struct fman_kg_regs *regs, uint8_t hwport_id)
{
uint32_t ar;
fman_kg_write_cpp(regs, 0);
ar = build_ar_bind_cls_plan(hwport_id, TRUE);
fman_kg_write_ar_wait(regs, ar);
}
static uint8_t get_gen_ht_code(enum fman_kg_gen_extract_src src,
bool no_validation,
uint8_t *offset)
{
int code;
switch (src) {
case E_FMAN_KG_GEN_EXTRACT_ETH:
code = no_validation ? 0x73 : 0x3;
break;
case E_FMAN_KG_GEN_EXTRACT_ETYPE:
code = no_validation ? 0x77 : 0x7;
break;
case E_FMAN_KG_GEN_EXTRACT_SNAP:
code = no_validation ? 0x74 : 0x4;
break;
case E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_1:
code = no_validation ? 0x75 : 0x5;
break;
case E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_N:
code = no_validation ? 0x76 : 0x6;
break;
case E_FMAN_KG_GEN_EXTRACT_PPPoE:
code = no_validation ? 0x78 : 0x8;
break;
case E_FMAN_KG_GEN_EXTRACT_MPLS_1:
code = no_validation ? 0x79 : 0x9;
break;
case E_FMAN_KG_GEN_EXTRACT_MPLS_2:
code = no_validation ? FM_KG_SCH_GEN_HT_INVALID : 0x19;
break;
case E_FMAN_KG_GEN_EXTRACT_MPLS_3:
code = no_validation ? FM_KG_SCH_GEN_HT_INVALID : 0x29;
break;
case E_FMAN_KG_GEN_EXTRACT_MPLS_N:
code = no_validation ? 0x7a : 0xa;
break;
case E_FMAN_KG_GEN_EXTRACT_IPv4_1:
code = no_validation ? 0x7b : 0xb;
break;
case E_FMAN_KG_GEN_EXTRACT_IPv6_1:
code = no_validation ? 0x7b : 0x1b;
break;
case E_FMAN_KG_GEN_EXTRACT_IPv4_2:
code = no_validation ? 0x7c : 0xc;
break;
case E_FMAN_KG_GEN_EXTRACT_IPv6_2:
code = no_validation ? 0x7c : 0x1c;
break;
case E_FMAN_KG_GEN_EXTRACT_MINENCAP:
code = no_validation ? 0x7c : 0x2c;
break;
case E_FMAN_KG_GEN_EXTRACT_IP_PID:
code = no_validation ? 0x72 : 0x2;
break;
case E_FMAN_KG_GEN_EXTRACT_GRE:
code = no_validation ? 0x7d : 0xd;
break;
case E_FMAN_KG_GEN_EXTRACT_TCP:
code = no_validation ? 0x7e : 0xe;
break;
case E_FMAN_KG_GEN_EXTRACT_UDP:
code = no_validation ? 0x7e : 0x1e;
break;
case E_FMAN_KG_GEN_EXTRACT_SCTP:
code = no_validation ? 0x7e : 0x3e;
break;
case E_FMAN_KG_GEN_EXTRACT_DCCP:
code = no_validation ? 0x7e : 0x4e;
break;
case E_FMAN_KG_GEN_EXTRACT_IPSEC_AH:
code = no_validation ? 0x7e : 0x2e;
break;
case E_FMAN_KG_GEN_EXTRACT_IPSEC_ESP:
code = no_validation ? 0x7e : 0x6e;
break;
case E_FMAN_KG_GEN_EXTRACT_SHIM_1:
code = 0x70;
break;
case E_FMAN_KG_GEN_EXTRACT_SHIM_2:
code = 0x71;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_DFLT:
code = 0x10;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_FRAME_START:
code = 0x40;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_PARSE_RESULT:
code = 0x20;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_END_OF_PARSE:
code = 0x7f;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_FQID:
code = 0x20;
*offset += 0x20;
break;
default:
code = FM_KG_SCH_GEN_HT_INVALID;
}
return (uint8_t)code;
}
static uint32_t build_ar_scheme(uint8_t scheme,
uint8_t hwport_id,
bool update_counter,
bool write)
{
uint32_t rw;
rw = (uint32_t)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ);
return (uint32_t)(FM_KG_KGAR_GO |
rw |
FM_KG_KGAR_SEL_SCHEME_ENTRY |
hwport_id |
((uint32_t)scheme << FM_KG_KGAR_NUM_SHIFT) |
(update_counter ? FM_KG_KGAR_SCM_WSEL_UPDATE_CNT : 0));
}
static uint32_t build_ar_cls_plan(uint8_t grp,
uint8_t entries_mask,
uint8_t hwport_id,
bool write)
{
uint32_t rw;
rw = (uint32_t)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ);
return (uint32_t)(FM_KG_KGAR_GO |
rw |
FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY |
hwport_id |
((uint32_t)grp << FM_KG_KGAR_NUM_SHIFT) |
((uint32_t)entries_mask << FM_KG_KGAR_WSEL_SHIFT));
}
int fman_kg_write_ar_wait(struct fman_kg_regs *regs, uint32_t fmkg_ar)
{
iowrite32be(fmkg_ar, &regs->fmkg_ar);
/* Wait for GO to be idle and read error */
while ((fmkg_ar = ioread32be(&regs->fmkg_ar)) & FM_KG_KGAR_GO) ;
if (fmkg_ar & FM_PCD_KG_KGAR_ERR)
return -EINVAL;
return 0;
}
void fman_kg_write_sp(struct fman_kg_regs *regs, uint32_t sp, bool add)
{
struct fman_kg_pe_regs *kgpe_regs;
uint32_t tmp;
kgpe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]);
tmp = ioread32be(&kgpe_regs->fmkg_pe_sp);
if (add)
tmp |= sp;
else /* clear */
tmp &= ~sp;
iowrite32be(tmp, &kgpe_regs->fmkg_pe_sp);
}
void fman_kg_write_cpp(struct fman_kg_regs *regs, uint32_t cpp)
{
struct fman_kg_pe_regs *kgpe_regs;
kgpe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]);
iowrite32be(cpp, &kgpe_regs->fmkg_pe_cpp);
}
void fman_kg_get_event(struct fman_kg_regs *regs,
uint32_t *event,
uint32_t *scheme_idx)
{
uint32_t mask, force;
*event = ioread32be(&regs->fmkg_eer);
mask = ioread32be(&regs->fmkg_eeer);
*scheme_idx = ioread32be(&regs->fmkg_seer);
*scheme_idx &= ioread32be(&regs->fmkg_seeer);
*event &= mask;
/* clear the forced events */
force = ioread32be(&regs->fmkg_feer);
if (force & *event)
iowrite32be(force & ~*event ,&regs->fmkg_feer);
iowrite32be(*event, &regs->fmkg_eer);
iowrite32be(*scheme_idx, &regs->fmkg_seer);
}
void fman_kg_init(struct fman_kg_regs *regs,
uint32_t exceptions,
uint32_t dflt_nia)
{
uint32_t tmp;
int i;
iowrite32be(FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW,
&regs->fmkg_eer);
tmp = 0;
if (exceptions & FM_EX_KG_DOUBLE_ECC)
tmp |= FM_EX_KG_DOUBLE_ECC;
if (exceptions & FM_EX_KG_KEYSIZE_OVERFLOW)
tmp |= FM_EX_KG_KEYSIZE_OVERFLOW;
iowrite32be(tmp, &regs->fmkg_eeer);
iowrite32be(0, &regs->fmkg_fdor);
iowrite32be(0, &regs->fmkg_gdv0r);
iowrite32be(0, &regs->fmkg_gdv1r);
iowrite32be(dflt_nia, &regs->fmkg_gcr);
/* Clear binding between ports to schemes and classification plans
* so that all ports are not bound to any scheme/classification plan */
for (i = 0; i < FMAN_MAX_NUM_OF_HW_PORTS; i++) {
clear_pe_all_scheme(regs, (uint8_t)i);
clear_pe_all_cls_plan(regs, (uint8_t)i);
}
}
void fman_kg_enable_scheme_interrupts(struct fman_kg_regs *regs)
{
/* enable and enable all scheme interrupts */
iowrite32be(0xFFFFFFFF, &regs->fmkg_seer);
iowrite32be(0xFFFFFFFF, &regs->fmkg_seeer);
}
void fman_kg_enable(struct fman_kg_regs *regs)
{
iowrite32be(ioread32be(&regs->fmkg_gcr) | FM_KG_KGGCR_EN,
&regs->fmkg_gcr);
}
void fman_kg_disable(struct fman_kg_regs *regs)
{
iowrite32be(ioread32be(&regs->fmkg_gcr) & ~FM_KG_KGGCR_EN,
&regs->fmkg_gcr);
}
void fman_kg_set_data_after_prs(struct fman_kg_regs *regs, uint8_t offset)
{
iowrite32be(offset, &regs->fmkg_fdor);
}
void fman_kg_set_dflt_val(struct fman_kg_regs *regs,
uint8_t def_id,
uint32_t val)
{
if(def_id == 0)
iowrite32be(val, &regs->fmkg_gdv0r);
else
iowrite32be(val, &regs->fmkg_gdv1r);
}
void fman_kg_set_exception(struct fman_kg_regs *regs,
uint32_t exception,
bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->fmkg_eeer);
if (enable) {
tmp |= exception;
} else {
tmp &= ~exception;
}
iowrite32be(tmp, &regs->fmkg_eeer);
}
void fman_kg_get_exception(struct fman_kg_regs *regs,
uint32_t *events,
uint32_t *scheme_ids,
bool clear)
{
uint32_t mask;
*events = ioread32be(&regs->fmkg_eer);
mask = ioread32be(&regs->fmkg_eeer);
*events &= mask;
*scheme_ids = 0;
if (*events & FM_EX_KG_KEYSIZE_OVERFLOW) {
*scheme_ids = ioread32be(&regs->fmkg_seer);
mask = ioread32be(&regs->fmkg_seeer);
*scheme_ids &= mask;
}
if (clear) {
iowrite32be(*scheme_ids, &regs->fmkg_seer);
iowrite32be(*events, &regs->fmkg_eer);
}
}
void fman_kg_get_capture(struct fman_kg_regs *regs,
struct fman_kg_ex_ecc_attr *ecc_attr,
bool clear)
{
uint32_t tmp;
tmp = ioread32be(&regs->fmkg_serc);
if (tmp & KG_FMKG_SERC_CAP) {
/* Captured data is valid */
ecc_attr->valid = TRUE;
ecc_attr->double_ecc =
(bool)((tmp & KG_FMKG_SERC_CET) ? TRUE : FALSE);
ecc_attr->single_ecc_count =
(uint8_t)((tmp & KG_FMKG_SERC_CNT_MSK) >>
KG_FMKG_SERC_CNT_SHIFT);
ecc_attr->addr = (uint16_t)(tmp & KG_FMKG_SERC_ADDR_MSK);
if (clear)
iowrite32be(KG_FMKG_SERC_CAP, &regs->fmkg_serc);
} else {
/* No ECC error is captured */
ecc_attr->valid = FALSE;
}
}
int fman_kg_build_scheme(struct fman_kg_scheme_params *params,
struct fman_kg_scheme_regs *scheme_regs)
{
struct fman_kg_extract_params *extract_params;
struct fman_kg_gen_extract_params *gen_params;
uint32_t tmp_reg, i, select, mask, fqb;
uint8_t offset, shift, ht;
/* Zero out all registers so no need to care about unused ones */
memset(scheme_regs, 0, sizeof(struct fman_kg_scheme_regs));
/* Mode register */
tmp_reg = fm_kg_build_nia(params->next_engine,
params->next_engine_action);
if (tmp_reg == KG_NIA_INVALID) {
return -EINVAL;
}
if (params->next_engine == E_FMAN_PCD_PLCR) {
tmp_reg |= FMAN_KG_SCH_MODE_NIA_PLCR;
}
else if (params->next_engine == E_FMAN_PCD_CC) {
tmp_reg |= (uint32_t)params->cc_params.base_offset <<
FMAN_KG_SCH_MODE_CCOBASE_SHIFT;
}
tmp_reg |= FMAN_KG_SCH_MODE_EN;
scheme_regs->kgse_mode = tmp_reg;
/* Match vector */
scheme_regs->kgse_mv = params->match_vector;
extract_params = &params->extract_params;
/* Scheme default values registers */
scheme_regs->kgse_dv0 = extract_params->def_scheme_0;
scheme_regs->kgse_dv1 = extract_params->def_scheme_1;
/* Extract Known Fields Command register */
scheme_regs->kgse_ekfc = extract_params->known_fields;
/* Entry Extract Known Default Value register */
tmp_reg = 0;
tmp_reg |= extract_params->known_fields_def.mac_addr <<
FMAN_KG_SCH_DEF_MAC_ADDR_SHIFT;
tmp_reg |= extract_params->known_fields_def.vlan_tci <<
FMAN_KG_SCH_DEF_VLAN_TCI_SHIFT;
tmp_reg |= extract_params->known_fields_def.etype <<
FMAN_KG_SCH_DEF_ETYPE_SHIFT;
tmp_reg |= extract_params->known_fields_def.ppp_sid <<
FMAN_KG_SCH_DEF_PPP_SID_SHIFT;
tmp_reg |= extract_params->known_fields_def.ppp_pid <<
FMAN_KG_SCH_DEF_PPP_PID_SHIFT;
tmp_reg |= extract_params->known_fields_def.mpls <<
FMAN_KG_SCH_DEF_MPLS_SHIFT;
tmp_reg |= extract_params->known_fields_def.ip_addr <<
FMAN_KG_SCH_DEF_IP_ADDR_SHIFT;
tmp_reg |= extract_params->known_fields_def.ptype <<
FMAN_KG_SCH_DEF_PTYPE_SHIFT;
tmp_reg |= extract_params->known_fields_def.ip_tos_tc <<
FMAN_KG_SCH_DEF_IP_TOS_TC_SHIFT;
tmp_reg |= extract_params->known_fields_def.ipv6_fl <<
FMAN_KG_SCH_DEF_IPv6_FL_SHIFT;
tmp_reg |= extract_params->known_fields_def.ipsec_spi <<
FMAN_KG_SCH_DEF_IPSEC_SPI_SHIFT;
tmp_reg |= extract_params->known_fields_def.l4_port <<
FMAN_KG_SCH_DEF_L4_PORT_SHIFT;
tmp_reg |= extract_params->known_fields_def.tcp_flg <<
FMAN_KG_SCH_DEF_TCP_FLG_SHIFT;
scheme_regs->kgse_ekdv = tmp_reg;
/* Generic extract registers */
if (extract_params->gen_extract_num > FM_KG_NUM_OF_GENERIC_REGS) {
return -EINVAL;
}
for (i = 0; i < extract_params->gen_extract_num; i++) {
gen_params = extract_params->gen_extract + i;
tmp_reg = FMAN_KG_SCH_GEN_VALID;
tmp_reg |= (uint32_t)gen_params->def_val <<
FMAN_KG_SCH_GEN_DEF_SHIFT;
if (gen_params->type == E_FMAN_KG_HASH_EXTRACT) {
if ((gen_params->extract > FMAN_KG_SCH_GEN_SIZE_MAX) ||
(gen_params->extract == 0)) {
return -EINVAL;
}
} else {
tmp_reg |= FMAN_KG_SCH_GEN_OR;
}
tmp_reg |= (uint32_t)gen_params->extract <<
FMAN_KG_SCH_GEN_SIZE_SHIFT;
tmp_reg |= (uint32_t)gen_params->mask <<
FMAN_KG_SCH_GEN_MASK_SHIFT;
offset = gen_params->offset;
ht = get_gen_ht_code(gen_params->src,
gen_params->no_validation,
&offset);
tmp_reg |= (uint32_t)ht << FMAN_KG_SCH_GEN_HT_SHIFT;
tmp_reg |= offset;
scheme_regs->kgse_gec[i] = tmp_reg;
}
/* Masks registers */
if (extract_params->masks_num > FM_KG_EXTRACT_MASKS_NUM) {
return -EINVAL;
}
select = 0;
mask = 0;
fqb = 0;
for (i = 0; i < extract_params->masks_num; i++) {
/* MCSx fields */
KG_GET_MASK_SEL_SHIFT(shift, i);
if (extract_params->masks[i].is_known) {
/* Mask known field */
select |= extract_params->masks[i].field_or_gen_idx <<
shift;
} else {
/* Mask generic extract */
select |= (extract_params->masks[i].field_or_gen_idx +
FM_KG_MASK_SEL_GEN_BASE) << shift;
}
/* MOx fields - spread between se_bmch and se_fqb registers */
KG_GET_MASK_OFFSET_SHIFT(shift, i);
if (i < 2) {
select |= (uint32_t)extract_params->masks[i].offset <<
shift;
} else {
fqb |= (uint32_t)extract_params->masks[i].offset <<
shift;
}
/* BMx fields */
KG_GET_MASK_SHIFT(shift, i);
mask |= (uint32_t)extract_params->masks[i].mask << shift;
}
/* Finish with rest of BMx fileds -
* don't mask bits for unused masks by setting
* corresponding BMx field = 0xFF */
for (i = extract_params->masks_num; i < FM_KG_EXTRACT_MASKS_NUM; i++) {
KG_GET_MASK_SHIFT(shift, i);
mask |= 0xFF << shift;
}
scheme_regs->kgse_bmch = select;
scheme_regs->kgse_bmcl = mask;
/* Finish with FQB register initialization.
* Check fqid is 24-bit value. */
if (params->base_fqid & ~0x00FFFFFF) {
return -EINVAL;
}
fqb |= params->base_fqid;
scheme_regs->kgse_fqb = fqb;
/* Hash Configuration register */
tmp_reg = 0;
if (params->hash_params.use_hash) {
/* Check hash mask is 24-bit value */
if (params->hash_params.mask & ~0x00FFFFFF) {
return -EINVAL;
}
/* Hash function produces 64-bit value, 24 bits of that
* are used to generate fq_id and policer profile.
* Thus, maximal shift is 40 bits to allow 24 bits out of 64.
*/
if (params->hash_params.shift_r > FMAN_KG_SCH_HASH_HSHIFT_MAX) {
return -EINVAL;
}
tmp_reg |= params->hash_params.mask;
tmp_reg |= (uint32_t)params->hash_params.shift_r <<
FMAN_KG_SCH_HASH_HSHIFT_SHIFT;
if (params->hash_params.sym) {
tmp_reg |= FMAN_KG_SCH_HASH_SYM;
}
}
if (params->bypass_fqid_gen) {
tmp_reg |= FMAN_KG_SCH_HASH_NO_FQID_GEN;
}
scheme_regs->kgse_hc = tmp_reg;
/* Policer Profile register */
if (params->policer_params.bypass_pp_gen) {
tmp_reg = 0;
} else {
/* Lower 8 bits of 24-bits extracted from hash result
* are used for policer profile generation.
* That leaves maximum shift value = 23. */
if (params->policer_params.shift > FMAN_KG_SCH_PP_SHIFT_MAX) {
return -EINVAL;
}
tmp_reg = params->policer_params.base;
tmp_reg |= ((uint32_t)params->policer_params.shift <<
FMAN_KG_SCH_PP_SH_SHIFT) &
FMAN_KG_SCH_PP_SH_MASK;
tmp_reg |= ((uint32_t)params->policer_params.shift <<
FMAN_KG_SCH_PP_SL_SHIFT) &
FMAN_KG_SCH_PP_SL_MASK;
tmp_reg |= (uint32_t)params->policer_params.mask <<
FMAN_KG_SCH_PP_MASK_SHIFT;
}
scheme_regs->kgse_ppc = tmp_reg;
/* Coarse Classification Bit Select register */
if (params->next_engine == E_FMAN_PCD_CC) {
scheme_regs->kgse_ccbs = params->cc_params.qlcv_bits_sel;
}
/* Packets Counter register */
if (params->update_counter) {
scheme_regs->kgse_spc = params->counter_value;
}
return 0;
}
int fman_kg_write_scheme(struct fman_kg_regs *regs,
uint8_t scheme_id,
uint8_t hwport_id,
struct fman_kg_scheme_regs *scheme_regs,
bool update_counter)
{
struct fman_kg_scheme_regs *kgse_regs;
uint32_t tmp_reg;
int err, i;
/* Write indirect scheme registers */
kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]);
iowrite32be(scheme_regs->kgse_mode, &kgse_regs->kgse_mode);
iowrite32be(scheme_regs->kgse_ekfc, &kgse_regs->kgse_ekfc);
iowrite32be(scheme_regs->kgse_ekdv, &kgse_regs->kgse_ekdv);
iowrite32be(scheme_regs->kgse_bmch, &kgse_regs->kgse_bmch);
iowrite32be(scheme_regs->kgse_bmcl, &kgse_regs->kgse_bmcl);
iowrite32be(scheme_regs->kgse_fqb, &kgse_regs->kgse_fqb);
iowrite32be(scheme_regs->kgse_hc, &kgse_regs->kgse_hc);
iowrite32be(scheme_regs->kgse_ppc, &kgse_regs->kgse_ppc);
iowrite32be(scheme_regs->kgse_spc, &kgse_regs->kgse_spc);
iowrite32be(scheme_regs->kgse_dv0, &kgse_regs->kgse_dv0);
iowrite32be(scheme_regs->kgse_dv1, &kgse_regs->kgse_dv1);
iowrite32be(scheme_regs->kgse_ccbs, &kgse_regs->kgse_ccbs);
iowrite32be(scheme_regs->kgse_mv, &kgse_regs->kgse_mv);
for (i = 0 ; i < FM_KG_NUM_OF_GENERIC_REGS ; i++)
iowrite32be(scheme_regs->kgse_gec[i], &kgse_regs->kgse_gec[i]);
/* Write AR (Action register) */
tmp_reg = build_ar_scheme(scheme_id, hwport_id, update_counter, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
int fman_kg_delete_scheme(struct fman_kg_regs *regs,
uint8_t scheme_id,
uint8_t hwport_id)
{
struct fman_kg_scheme_regs *kgse_regs;
uint32_t tmp_reg;
int err, i;
kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]);
/* Clear all registers including enable bit in mode register */
for (i = 0; i < (sizeof(struct fman_kg_scheme_regs)) / 4; ++i) {
iowrite32be(0, ((uint32_t *)kgse_regs + i));
}
/* Write AR (Action register) */
tmp_reg = build_ar_scheme(scheme_id, hwport_id, FALSE, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
int fman_kg_get_scheme_counter(struct fman_kg_regs *regs,
uint8_t scheme_id,
uint8_t hwport_id,
uint32_t *counter)
{
struct fman_kg_scheme_regs *kgse_regs;
uint32_t tmp_reg;
int err;
kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]);
tmp_reg = build_ar_scheme(scheme_id, hwport_id, TRUE, FALSE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
if (err != 0)
return err;
*counter = ioread32be(&kgse_regs->kgse_spc);
return 0;
}
int fman_kg_set_scheme_counter(struct fman_kg_regs *regs,
uint8_t scheme_id,
uint8_t hwport_id,
uint32_t counter)
{
struct fman_kg_scheme_regs *kgse_regs;
uint32_t tmp_reg;
int err;
kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]);
tmp_reg = build_ar_scheme(scheme_id, hwport_id, TRUE, FALSE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
if (err != 0)
return err;
/* Keygen indirect access memory contains all scheme_id registers
* by now. Change only counter value. */
iowrite32be(counter, &kgse_regs->kgse_spc);
/* Write back scheme registers */
tmp_reg = build_ar_scheme(scheme_id, hwport_id, TRUE, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
uint32_t fman_kg_get_schemes_total_counter(struct fman_kg_regs *regs)
{
return ioread32be(&regs->fmkg_tpc);
}
int fman_kg_build_cls_plan(struct fman_kg_cls_plan_params *params,
struct fman_kg_cp_regs *cls_plan_regs)
{
uint8_t entries_set, entry_bit;
int i;
/* Zero out all group's register */
memset(cls_plan_regs, 0, sizeof(struct fman_kg_cp_regs));
/* Go over all classification entries in params->entries_mask and
* configure the corresponding cpe register */
entries_set = params->entries_mask;
for (i = 0; entries_set; i++) {
entry_bit = (uint8_t)(0x80 >> i);
if ((entry_bit & entries_set) == 0)
continue;
entries_set ^= entry_bit;
cls_plan_regs->kgcpe[i] = params->mask_vector[i];
}
return 0;
}
int fman_kg_write_cls_plan(struct fman_kg_regs *regs,
uint8_t grp_id,
uint8_t entries_mask,
uint8_t hwport_id,
struct fman_kg_cp_regs *cls_plan_regs)
{
struct fman_kg_cp_regs *kgcpe_regs;
uint32_t tmp_reg;
int i, err;
/* Check group index is valid and the group isn't empty */
if (grp_id >= FM_KG_CLS_PLAN_GRPS_NUM)
return -EINVAL;
/* Write indirect classification plan registers */
kgcpe_regs = (struct fman_kg_cp_regs *)&(regs->fmkg_indirect[0]);
for (i = 0; i < FM_KG_NUM_CLS_PLAN_ENTR; i++) {
iowrite32be(cls_plan_regs->kgcpe[i], &kgcpe_regs->kgcpe[i]);
}
tmp_reg = build_ar_cls_plan(grp_id, entries_mask, hwport_id, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
int fman_kg_write_bind_schemes(struct fman_kg_regs *regs,
uint8_t hwport_id,
uint32_t schemes)
{
struct fman_kg_pe_regs *kg_pe_regs;
uint32_t tmp_reg;
int err;
kg_pe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]);
iowrite32be(schemes, &kg_pe_regs->fmkg_pe_sp);
tmp_reg = build_ar_bind_scheme(hwport_id, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
int fman_kg_build_bind_cls_plans(uint8_t grp_base,
uint8_t grp_mask,
uint32_t *bind_cls_plans)
{
/* Check grp_base and grp_mask are 5-bits values */
if ((grp_base & ~0x0000001F) || (grp_mask & ~0x0000001F))
return -EINVAL;
*bind_cls_plans = (uint32_t) ((grp_mask << FMAN_KG_PE_CPP_MASK_SHIFT) | grp_base);
return 0;
}
int fman_kg_write_bind_cls_plans(struct fman_kg_regs *regs,
uint8_t hwport_id,
uint32_t bind_cls_plans)
{
struct fman_kg_pe_regs *kg_pe_regs;
uint32_t tmp_reg;
int err;
kg_pe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]);
iowrite32be(bind_cls_plans, &kg_pe_regs->fmkg_pe_cpp);
tmp_reg = build_ar_bind_cls_plan(hwport_id, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}

129
sys/contrib/ncsw/Peripherals/FM/Pcd/fman_prs.c Normal file
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@ -0,0 +1,129 @@
/*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_prs.h"
uint32_t fman_prs_get_err_event(struct fman_prs_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->fmpr_perr) & ev_mask;
}
uint32_t fman_prs_get_err_ev_mask(struct fman_prs_regs *regs)
{
return ioread32be(&regs->fmpr_perer);
}
void fman_prs_ack_err_event(struct fman_prs_regs *regs, uint32_t event)
{
iowrite32be(event, &regs->fmpr_perr);
}
uint32_t fman_prs_get_expt_event(struct fman_prs_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->fmpr_pevr) & ev_mask;
}
uint32_t fman_prs_get_expt_ev_mask(struct fman_prs_regs *regs)
{
return ioread32be(&regs->fmpr_pever);
}
void fman_prs_ack_expt_event(struct fman_prs_regs *regs, uint32_t event)
{
iowrite32be(event, &regs->fmpr_pevr);
}
void fman_prs_defconfig(struct fman_prs_cfg *cfg)
{
cfg->port_id_stat = 0;
cfg->max_prs_cyc_lim = DEFAULT_MAX_PRS_CYC_LIM;
cfg->prs_exceptions = 0x03000000;
}
int fman_prs_init(struct fman_prs_regs *regs, struct fman_prs_cfg *cfg)
{
uint32_t tmp;
iowrite32be(cfg->max_prs_cyc_lim, &regs->fmpr_rpclim);
iowrite32be((FM_PCD_PRS_SINGLE_ECC | FM_PCD_PRS_PORT_IDLE_STS),
&regs->fmpr_pevr);
if (cfg->prs_exceptions & FM_PCD_EX_PRS_SINGLE_ECC)
iowrite32be(FM_PCD_PRS_SINGLE_ECC, &regs->fmpr_pever);
else
iowrite32be(0, &regs->fmpr_pever);
iowrite32be(FM_PCD_PRS_DOUBLE_ECC, &regs->fmpr_perr);
tmp = 0;
if (cfg->prs_exceptions & FM_PCD_EX_PRS_DOUBLE_ECC)
tmp |= FM_PCD_PRS_DOUBLE_ECC;
iowrite32be(tmp, &regs->fmpr_perer);
iowrite32be(cfg->port_id_stat, &regs->fmpr_ppsc);
return 0;
}
void fman_prs_enable(struct fman_prs_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->fmpr_rpimac) | FM_PCD_PRS_RPIMAC_EN;
iowrite32be(tmp, &regs->fmpr_rpimac);
}
void fman_prs_disable(struct fman_prs_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->fmpr_rpimac) & ~FM_PCD_PRS_RPIMAC_EN;
iowrite32be(tmp, &regs->fmpr_rpimac);
}
int fman_prs_is_enabled(struct fman_prs_regs *regs)
{
return ioread32be(&regs->fmpr_rpimac) & FM_PCD_PRS_RPIMAC_EN;
}
void fman_prs_set_stst_port_msk(struct fman_prs_regs *regs, uint32_t pid_msk)
{
iowrite32be(pid_msk, &regs->fmpr_ppsc);
}
void fman_prs_set_stst(struct fman_prs_regs *regs, bool enable)
{
if (enable)
iowrite32be(FM_PCD_PRS_PPSC_ALL_PORTS, &regs->fmpr_ppsc);
else
iowrite32be(0, &regs->fmpr_ppsc);
}

7960
sys/contrib/ncsw/Peripherals/FM/Port/fm_port.c
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511
sys/contrib/ncsw/Peripherals/FM/Port/fm_port.h
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@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_port.h
@ -43,7 +44,10 @@
#include "fm_port_ext.h"
#include "fm_common.h"
#include "fm_sp_common.h"
#include "fsl_fman_sp.h"
#include "fm_port_ext.h"
#include "fsl_fman_port.h"
#define __ERR_MODULE__ MODULE_FM_PORT
@ -51,6 +55,7 @@
#define MIN_EXT_BUF_SIZE 64
#define DATA_ALIGNMENT 64
#define MAX_LIODN_OFFSET 64
#define MAX_PORT_FIFO_SIZE MIN(BMI_MAX_FIFO_SIZE, 1024*BMI_FIFO_UNITS)
/**************************************************************************//**
@Description Memory Map defines
@ -62,36 +67,31 @@
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
#define DEFAULT_PORT_deqHighPriority TRUE
#define DEFAULT_PORT_deqHighPriority_1G FALSE
#define DEFAULT_PORT_deqHighPriority_10G TRUE
#define DEFAULT_PORT_deqType e_FM_PORT_DEQ_TYPE1
#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT
#define DEFAULT_PORT_deqPrefetchOption e_FM_PORT_DEQ_FULL_PREFETCH
#define DEFAULT_PORT_deqPrefetchOption_HC e_FM_PORT_DEQ_NO_PREFETCH
#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */
#define DEFAULT_PORT_deqByteCnt 2000
#define DEFAULT_PORT_bufferPrefixContent_privDataSize 0
#define DEFAULT_PORT_bufferPrefixContent_passPrsResult FALSE
#define DEFAULT_PORT_bufferPrefixContent_passTimeStamp FALSE
#define DEFAULT_PORT_bufferPrefixContent_allOtherPCDInfo FALSE
#ifdef DEBUG
#define DEFAULT_PORT_bufferPrefixContent_debugInfo FALSE
#endif /* DEBUG */
#define DEFAULT_PORT_bufferPrefixContent_dataAlign DATA_ALIGNMENT
#define DEFAULT_PORT_deqByteCnt_10G 0x1400
#define DEFAULT_PORT_deqByteCnt_1G 0x400
#define DEFAULT_PORT_bufferPrefixContent_privDataSize DEFAULT_FM_SP_bufferPrefixContent_privDataSize
#define DEFAULT_PORT_bufferPrefixContent_passPrsResult DEFAULT_FM_SP_bufferPrefixContent_passPrsResult
#define DEFAULT_PORT_bufferPrefixContent_passTimeStamp DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp
#define DEFAULT_PORT_bufferPrefixContent_allOtherPCDInfo DEFAULT_FM_SP_bufferPrefixContent_allOtherPCDInfo
#define DEFAULT_PORT_bufferPrefixContent_dataAlign DEFAULT_FM_SP_bufferPrefixContent_dataAlign
#define DEFAULT_PORT_cheksumLastBytesIgnore 0
#define DEFAULT_PORT_cutBytesFromEnd 4
#define DEFAULT_PORT_txFifoMinFillLevel 0
#define DEFAULT_PORT_txFifoDeqPipelineDepth_IM 2
#define DEFAULT_PORT_txFifoDeqPipelineDepth_1G 2
#define DEFAULT_PORT_txFifoDeqPipelineDepth_10G 8
#define DEFAULT_PORT_txFifoLowComfLevel (5*KILOBYTE)
#define DEFAULT_PORT_rxFifoPriElevationLevel BMI_MAX_FIFO_SIZE
#define DEFAULT_PORT_rxFifoThreshold (BMI_MAX_FIFO_SIZE*3/4)
#define DEFAULT_PORT_fifoDeqPipelineDepth_IM 2
#define DEFAULT_PORT_frmDiscardOverride FALSE
#define DEFAULT_PORT_dmaSwapData e_FM_PORT_DMA_NO_SWP
#define DEFAULT_PORT_dmaIntContextCacheAttr e_FM_PORT_DMA_NO_STASH
#define DEFAULT_PORT_dmaHeaderCacheAttr e_FM_PORT_DMA_NO_STASH
#define DEFAULT_PORT_dmaScatterGatherCacheAttr e_FM_PORT_DMA_NO_STASH
#define DEFAULT_PORT_dmaWriteOptimize TRUE
#define DEFAULT_PORT_dmaSwapData (e_FmDmaSwapOption)DEFAULT_FMAN_SP_DMA_SWAP_DATA
#define DEFAULT_PORT_dmaIntContextCacheAttr (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR
#define DEFAULT_PORT_dmaHeaderCacheAttr (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR
#define DEFAULT_PORT_dmaScatterGatherCacheAttr (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR
#define DEFAULT_PORT_dmaWriteOptimize DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE
#define DEFAULT_PORT_noScatherGather DEFAULT_FMAN_SP_NO_SCATTER_GATHER
#define DEFAULT_PORT_forwardIntContextReuse FALSE
#define DEFAULT_PORT_BufMargins_startMargins 32
#define DEFAULT_PORT_BufMargins_endMargins 0
@ -99,9 +99,23 @@
#define DEFAULT_PORT_syncReqForHc FALSE
#define DEFAULT_PORT_color e_FM_PORT_COLOR_GREEN
#define DEFAULT_PORT_errorsToDiscard FM_PORT_FRM_ERR_CLS_DISCARD
#define DEFAULT_dualRateLimitScaleDown e_FM_PORT_DUAL_RATE_LIMITER_NONE
#define DEFAULT_rateLimitBurstSizeHighGranularity FALSE
#define DEFAULT_exception IM_EV_BSY
/* #define DEFAULT_PORT_dualRateLimitScaleDown e_FM_PORT_DUAL_RATE_LIMITER_NONE */
/* #define DEFAULT_PORT_rateLimitBurstSizeHighGranularity FALSE */
#define DEFAULT_PORT_exception IM_EV_BSY
#define DEFAULT_PORT_maxFrameLength 9600
#define DEFAULT_notSupported 0xff
#if (DPAA_VERSION < 11)
#define DEFAULT_PORT_rxFifoPriElevationLevel MAX_PORT_FIFO_SIZE
#define DEFAULT_PORT_rxFifoThreshold (MAX_PORT_FIFO_SIZE*3/4)
#define DEFAULT_PORT_txFifoMinFillLevel 0
#define DEFAULT_PORT_txFifoLowComfLevel (5*KILOBYTE)
#define DEFAULT_PORT_fifoDeqPipelineDepth_1G 1
#define DEFAULT_PORT_fifoDeqPipelineDepth_10G 4
#define DEFAULT_PORT_fifoDeqPipelineDepth_OH 2
/* Host command port MUST NOT be changed to more than 1 !!! */
#define DEFAULT_PORT_numOfTasks(type) \
@ -112,46 +126,116 @@
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? 3 : 1))
#define DEFAULT_PORT_extraNumOfTasks(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? 8 : \
((((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX) || \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? 2 : 0))
(uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 : \
(((type) == e_FM_PORT_TYPE_RX) ? 2 : 0))
#define DEFAULT_PORT_numOfOpenDmas(type) \
(uint32_t)(((type) == e_FM_PORT_TYPE_TX_10G) ? 8 : \
(((type) == e_FM_PORT_TYPE_RX_10G) ? 4 : 1))
#define DEFAULT_PORT_numOfOpenDmas(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_TX_10G) || \
((type) == e_FM_PORT_TYPE_RX_10G)) ? 8 : 1 )
#define DEFAULT_PORT_extraNumOfOpenDmas(type) \
(uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 : \
(((type) == e_FM_PORT_TYPE_RX) ? 1 : 0))
#define DEFAULT_PORT_numOfFifoBufs(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? 8 : \
((((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX) || \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? 1 : 0))
((type) == e_FM_PORT_TYPE_TX_10G)) ? 48 : \
((type) == e_FM_PORT_TYPE_RX) ? 45 : \
((type) == e_FM_PORT_TYPE_TX) ? 44 : 8)
#if defined(CONFIG_FMAN_RESOURCE_ALLOCATION_ALGORITHM)
/* Let LLD to set minimum fifosize, otherwise fifosize settings will not work */
#define DEFAULT_PORT_sizeOfFifo(type) \
(uint32_t)(KILOBYTE)
#else
#define DEFAULT_PORT_sizeOfFifo(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? (16*KILOBYTE) : \
((((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX) || \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? (4*KILOBYTE) : (1536)))
#endif
#define DEFAULT_PORT_extraNumOfFifoBufs 0
#define DEFAULT_PORT_extraSizeOfFifo(type) \
(uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? (8*KILOBYTE) : \
(((type) == e_FM_PORT_TYPE_RX) ? (4*KILOBYTE) : (0)))
#else /* (DPAA_VERSION < 11) */
/* Defaults are registers' reset values */
#define DEFAULT_PORT_rxFifoPriElevationLevel MAX_PORT_FIFO_SIZE
#define DEFAULT_PORT_rxFifoThreshold MAX_PORT_FIFO_SIZE
#define DEFAULT_PORT_txFifoMinFillLevel 0
#define DEFAULT_PORT_txFifoLowComfLevel (5 * KILOBYTE)
#define DEFAULT_PORT_fifoDeqPipelineDepth_1G 2
#define DEFAULT_PORT_fifoDeqPipelineDepth_10G 4
#define DEFAULT_PORT_fifoDeqPipelineDepth_OH 2
#define DEFAULT_PORT_numOfTasks(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? 14 : \
(((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX)) ? 4 : \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) ? 6 : 1)
#define DEFAULT_PORT_extraNumOfTasks(type) 0
#define DEFAULT_PORT_numOfOpenDmas(type) \
(uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 : \
((type) == e_FM_PORT_TYPE_TX_10G) ? 12 : \
((type) == e_FM_PORT_TYPE_RX) ? 2 : \
((type) == e_FM_PORT_TYPE_TX) ? 3 : \
((type) == e_FM_PORT_TYPE_OH_HOST_COMMAND) ? 2 : 4)
#define DEFAULT_PORT_extraNumOfOpenDmas(type) 0
#define DEFAULT_PORT_numOfFifoBufs(type) \
(uint32_t) (((type) == e_FM_PORT_TYPE_RX_10G) ? 96 : \
((type) == e_FM_PORT_TYPE_TX_10G) ? 64 : \
((type) == e_FM_PORT_TYPE_OH_HOST_COMMAND) ? 10 : 50)
#define DEFAULT_PORT_extraNumOfFifoBufs 0
#endif /* (DPAA_VERSION < 11) */
#define DEFAULT_PORT_txBdRingLength 16
#define DEFAULT_PORT_rxBdRingLength 128
#define DEFAULT_PORT_ImfwExtStructsMemId 0
#define DEFAULT_PORT_ImfwExtStructsMemAttr MEMORY_ATTR_CACHEABLE
#define OH_PIPELINE_DEPTH 2
#define FM_PORT_CG_REG_NUM(_cgId) (((FM_PORT_NUM_OF_CONGESTION_GRPS/32)-1)-_cgId/32)
/**************************************************************************//**
@Collection PCD Engines
*//***************************************************************************/
typedef uint32_t fmPcdEngines_t; /**< options as defined below: */
#define FM_PCD_NONE 0 /**< No PCD Engine indicated */
#define FM_PCD_PRS 0x80000000 /**< Parser indicated */
#define FM_PCD_KG 0x40000000 /**< Keygen indicated */
#define FM_PCD_CC 0x20000000 /**< Coarse classification indicated */
#define FM_PCD_PLCR 0x10000000 /**< Policer indicated */
#define FM_PCD_MANIP 0x08000000 /**< Manipulation indicated */
/* @} */
#define FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS 8
#define FM_PORT_MAX_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS 256
#define FM_PORT_CG_REG_NUM(_cgId) (((FM_PORT_NUM_OF_CONGESTION_GRPS/32)-1)-_cgId/32)
#define FM_OH_PORT_ID 0
/***********************************************************************/
/* SW parser OFFLOAD labels (offsets) */
/***********************************************************************/
#if (DPAA_VERSION == 10)
#define OFFLOAD_SW_PATCH_IPv4_IPR_LABEL 0x300
#define OFFLOAD_SW_PATCH_IPv6_IPR_LABEL 0x325
#define OFFLOAD_SW_PATCH_IPv6_IPF_LABEL 0x325
#else
#define OFFLOAD_SW_PATCH_IPv4_IPR_LABEL 0x100
/* Will be used for:
* 1. identify fragments
* 2. udp-lite
*/
#define OFFLOAD_SW_PATCH_IPv6_IPR_LABEL 0x146
/* Will be used for:
* 1. will identify the fragmentable area
* 2. udp-lite
*/
#define OFFLOAD_SW_PATCH_IPv6_IPF_LABEL 0x261
#define OFFLOAD_SW_PATCH_CAPWAP_LABEL 0x38d
#endif /* (DPAA_VERSION == 10) */
#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT))
#define UDP_LITE_SW_PATCH_LABEL 0x2E0
#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */
/**************************************************************************//**
@Description Memory Mapped Registers
@ -160,12 +244,8 @@
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
#define FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS 8
#define FM_PORT_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS 256
typedef _Packed struct
typedef struct
{
volatile uint32_t fmbm_rcfg; /**< Rx Configuration */
volatile uint32_t fmbm_rst; /**< Rx Status */
@ -182,7 +262,7 @@ typedef _Packed struct
volatile uint32_t fmbm_rpp; /**< Rx Policer Profile */
volatile uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */
volatile uint32_t fmbm_reth; /**< Rx Excessive Threshold */
volatile uint32_t reserved1[1]; /**< (0x03C 0x03F) */
volatile uint32_t reserved1[0x01];/**< (0x03C) */
volatile uint32_t fmbm_rprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS];
/**< Rx Parse Results Array Initialization*/
volatile uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/
@ -190,17 +270,19 @@ typedef _Packed struct
volatile uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/
volatile uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/
volatile uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */
volatile uint32_t reserved2[0x23];/**< (0x074 0x0FF) */
volatile uint32_t reserved2[0x02];/**< (0x074-0x078) */
volatile uint32_t fmbm_rcmne; /**< Rx Frame Continuous Mode Next Engine */
volatile uint32_t reserved3[0x20];/**< (0x080 0x0FF) */
volatile uint32_t fmbm_ebmpi[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS];
/**< Buffer Manager pool Information-*/
volatile uint32_t fmbm_acnt[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS];
/**< Allocate Counter-*/
volatile uint32_t reserved3[8];
volatile uint32_t reserved4[0x08];
/**< 0x130/0x140 - 0x15F reserved -*/
volatile uint32_t fmbm_cgm[FM_PORT_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS/32];
volatile uint32_t fmbm_rcgm[FM_PORT_MAX_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS/32];
/**< Congestion Group Map*/
volatile uint32_t fmbm_mpd; /**< BM Pool Depletion */
volatile uint32_t reserved4[0x1F];/**< (0x184 0x1FF) */
volatile uint32_t fmbm_rmpd; /**< BM Pool Depletion */
volatile uint32_t reserved5[0x1F];/**< (0x184 0x1FF) */
volatile uint32_t fmbm_rstc; /**< Rx Statistics Counters*/
volatile uint32_t fmbm_rfrc; /**< Rx Frame Counter*/
volatile uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/
@ -210,7 +292,8 @@ typedef _Packed struct
volatile uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/
volatile uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard Counter-*/
volatile uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter-*/
volatile uint32_t reserved5[0x17];/**< (0x224 0x27F) */
volatile uint32_t fmbm_rpec; /**< Rx RX Prepare to enqueue Counter-*/
volatile uint32_t reserved6[0x16];/**< (0x228 0x27F) */
volatile uint32_t fmbm_rpc; /**< Rx Performance Counters*/
volatile uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/
volatile uint32_t fmbm_rccn; /**< Rx Cycle Counter*/
@ -219,11 +302,13 @@ typedef _Packed struct
volatile uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/
volatile uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/
volatile uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/
volatile uint32_t reserved6[0x18];/**< (0x2A0 0x2FF) */
volatile uint32_t fmbm_rdbg; /**< Rx Debug-*/
} _PackedType t_FmPortRxBmiRegs;
volatile uint32_t reserved7[0x18];/**< (0x2A0-0x2FF) */
volatile uint32_t fmbm_rdcfg[0x3];/**< Rx Debug-*/
volatile uint32_t fmbm_rgpr; /**< Rx General Purpose Register. */
volatile uint32_t reserved8[0x3a];/**< (0x310-0x3FF) */
} t_FmPortRxBmiRegs;
typedef _Packed struct
typedef struct
{
volatile uint32_t fmbm_tcfg; /**< Tx Configuration */
volatile uint32_t fmbm_tst; /**< Tx Status */
@ -231,21 +316,26 @@ typedef _Packed struct
volatile uint32_t fmbm_tfp; /**< Tx FIFO Parameters */
volatile uint32_t fmbm_tfed; /**< Tx Frame End Data */
volatile uint32_t fmbm_ticp; /**< Tx Internal Context Parameters */
volatile uint32_t fmbm_tfne; /**< Tx Frame Next Engine. */
volatile uint32_t fmbm_tfdne; /**< Tx Frame Dequeue Next Engine. */
volatile uint32_t fmbm_tfca; /**< Tx Frame Command attribute. */
volatile uint32_t fmbm_tcfqid; /**< Tx Confirmation Frame Queue ID. */
volatile uint32_t fmbm_tfeqid; /**< Tx Frame Error Queue ID */
volatile uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine */
volatile uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale */
volatile uint32_t fmbm_trlmt; /**< Tx Rate Limiter */
volatile uint32_t reserved0[0x73];/**< (0x038-0x200) */
volatile uint32_t fmbm_tccb; /**< Tx Coarse Classification Base */
volatile uint32_t reserved0[0x0e];/**< (0x038-0x070) */
volatile uint32_t fmbm_tfne; /**< Tx Frame Next Engine */
volatile uint32_t fmbm_tpfcm[0x02];/**< Tx Priority based Flow Control (PFC) Mapping */
volatile uint32_t fmbm_tcmne; /**< Tx Frame Continuous Mode Next Engine */
volatile uint32_t reserved2[0x60];/**< (0x080-0x200) */
volatile uint32_t fmbm_tstc; /**< Tx Statistics Counters */
volatile uint32_t fmbm_tfrc; /**< Tx Frame Counter */
volatile uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter */
volatile uint32_t fmbm_tfledc; /**< Tx Frame Length error discard counter */
volatile uint32_t fmbm_tfufdc; /**< Tx Frame unsupported format discard Counter */
volatile uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */
volatile uint32_t reserved1[0x1A];/**< (0x218-0x280) */
volatile uint32_t reserved3[0x1A];/**< (0x218-0x280) */
volatile uint32_t fmbm_tpc; /**< Tx Performance Counters*/
volatile uint32_t fmbm_tpcp; /**< Tx Performance Count Parameters*/
volatile uint32_t fmbm_tccn; /**< Tx Cycle Counter*/
@ -253,9 +343,13 @@ typedef _Packed struct
volatile uint32_t fmbm_ttcquc; /**< Tx Transmit Confirm Queue Utilization Counter*/
volatile uint32_t fmbm_tduc; /**< Tx DMA Utilization Counter*/
volatile uint32_t fmbm_tfuc; /**< Tx FIFO Utilization Counter*/
} _PackedType t_FmPortTxBmiRegs;
volatile uint32_t reserved4[16]; /**< (0x29C-0x2FF) */
volatile uint32_t fmbm_tdcfg[0x3];/**< Tx Debug-*/
volatile uint32_t fmbm_tgpr; /**< O/H General Purpose Register */
volatile uint32_t reserved5[0x3a];/**< (0x310-0x3FF) */
} t_FmPortTxBmiRegs;
typedef _Packed struct
typedef struct
{
volatile uint32_t fmbm_ocfg; /**< O/H Configuration */
volatile uint32_t fmbm_ost; /**< O/H Status */
@ -269,7 +363,9 @@ typedef _Packed struct
volatile uint32_t fmbm_opp; /**< O/H Policer Profile */
volatile uint32_t fmbm_occb; /**< O/H Coarse Classification base */
volatile uint32_t fmbm_oim; /**< O/H Internal margins*/
volatile uint32_t reserved0[4]; /**< (0x030 - 0x03F) */
volatile uint32_t fmbm_ofp; /**< O/H Fifo Parameters*/
volatile uint32_t fmbm_ofed; /**< O/H Frame End Data*/
volatile uint32_t reserved0[2]; /**< (0x038 - 0x03F) */
volatile uint32_t fmbm_oprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS];
/**< O/H Parse Results Array Initialization */
volatile uint32_t fmbm_ofqid; /**< O/H Frame Queue ID */
@ -279,19 +375,14 @@ typedef _Packed struct
volatile uint32_t fmbm_ofene; /**< O/H Frame Enqueue Next Engine */
volatile uint32_t fmbm_orlmts; /**< O/H Rate Limiter Scale */
volatile uint32_t fmbm_orlmt; /**< O/H Rate Limiter */
volatile uint32_t reserved0a[0x21];
/**< 0x07C - 0x0FF Reserved */
union
{
volatile uint32_t fmbm_oebmpi[FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS];
/**< Buffer Manager Observed Pool Information */
volatile uint32_t reserved0b[0x18];
}; /**< 0x100 - 0x15F Reserved */
volatile uint32_t fmbm_ocmne; /**< O/H Continuous Mode Next Engine */
volatile uint32_t reserved1[0x20];/**< (0x080 - 0x0FF) */
volatile uint32_t fmbm_oebmpi[2]; /**< Buffer Manager Observed Pool Information */
volatile uint32_t reserved2[0x16];/**< (0x108 - 0x15F) */
volatile uint32_t fmbm_ocgm; /**< Observed Congestion Group Map */
volatile uint32_t reserved0c[0x7];/**< 0x164 - 0x17F Reserved */
volatile uint32_t reserved3[0x7]; /**< (0x164 - 0x17F) */
volatile uint32_t fmbm_ompd; /**< Observed BMan Pool Depletion */
volatile uint32_t reserved0d[0x1F];
/**< 0x184 - 0x1FF Reserved */
volatile uint32_t reserved4[0x1F];/**< (0x184 - 0x1FF) */
volatile uint32_t fmbm_ostc; /**< O/H Statistics Counters */
volatile uint32_t fmbm_ofrc; /**< O/H Frame Counter */
volatile uint32_t fmbm_ofdc; /**< O/H Frames Discard Counter */
@ -301,23 +392,29 @@ typedef _Packed struct
volatile uint32_t fmbm_ofwdc; /**< - Rx Frames WRED Discard Counter */
volatile uint32_t fmbm_ofldec; /**< O/H Frames List DMA Error Counter */
volatile uint32_t fmbm_obdc; /**< O/H Buffers Deallocate Counter */
volatile uint32_t reserved2[0x17];/**< (0x218 - 0x27F) */
volatile uint32_t fmbm_oodc; /**< O/H Out of Buffers Discard Counter */
volatile uint32_t fmbm_opec; /**< O/H Prepare to enqueue Counter */
volatile uint32_t reserved5[0x15];/**< ( - 0x27F) */
volatile uint32_t fmbm_opc; /**< O/H Performance Counters */
volatile uint32_t fmbm_opcp; /**< O/H Performance Count Parameters */
volatile uint32_t fmbm_occn; /**< O/H Cycle Counter */
volatile uint32_t fmbm_otuc; /**< O/H Tasks Utilization Counter */
volatile uint32_t fmbm_oduc; /**< O/H DMA Utilization Counter */
volatile uint32_t fmbm_ofuc; /**< O/H FIFO Utilization Counter */
} _PackedType t_FmPortOhBmiRegs;
volatile uint32_t reserved6[26]; /**< (0x298-0x2FF) */
volatile uint32_t fmbm_odcfg[0x3];/**< O/H Debug (only 1 in P1023) */
volatile uint32_t fmbm_ogpr; /**< O/H General Purpose Register. */
volatile uint32_t reserved7[0x3a];/**< (0x310 0x3FF) */
} t_FmPortOhBmiRegs;
typedef _Packed union
typedef union
{
t_FmPortRxBmiRegs rxPortBmiRegs;
t_FmPortTxBmiRegs txPortBmiRegs;
t_FmPortOhBmiRegs ohPortBmiRegs;
} _PackedType u_FmPortBmiRegs;
} u_FmPortBmiRegs;
typedef _Packed struct
typedef struct
{
volatile uint32_t reserved1[2]; /**< 0xn024 - 0x02B */
volatile uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */
@ -325,9 +422,9 @@ typedef _Packed struct
volatile uint32_t fmqm_pndtfc; /**< PortID n Dequeue Total Frame Counter */
volatile uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID from Default Counter */
volatile uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */
} _PackedType t_FmPortNonRxQmiRegs;
} t_FmPortNonRxQmiRegs;
typedef _Packed struct
typedef struct
{
volatile uint32_t fmqm_pnc; /**< PortID n Configuration Register */
volatile uint32_t fmqm_pns; /**< PortID n Status Register */
@ -335,20 +432,20 @@ typedef _Packed struct
volatile uint32_t reserved0[4]; /**< 0xn00C - 0xn01B */
volatile uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */
volatile uint32_t fmqm_pnetfc; /**< PortID n Enqueue Total Frame Counter */
t_FmPortNonRxQmiRegs nonRxQmiRegs; /**< Registers for Tx Hc & Op ports */
} _PackedType t_FmPortQmiRegs;
t_FmPortNonRxQmiRegs nonRxQmiRegs; /**< Registers for Tx Hc & Op ports */
} t_FmPortQmiRegs;
typedef _Packed struct
typedef struct
{
_Packed struct
struct
{
volatile uint32_t softSeqAttach; /**< Soft Sequence Attachment */
volatile uint32_t lcv; /**< Line-up Enable Confirmation Mask */
} _PackedType hdrs[FM_PCD_PRS_NUM_OF_HDRS];
volatile uint8_t reserved0[0x378];
} hdrs[FM_PCD_PRS_NUM_OF_HDRS];
volatile uint32_t reserved0[0xde];
volatile uint32_t pcac; /**< Parse Internal Memory Configuration Access Control Register */
volatile uint32_t pctpid; /**< Parse Internal Memory Configured TPID Register */
} _PackedType t_FmPortPrsRegs;
} t_FmPortPrsRegs;
/**************************************************************************//*
@Description Basic buffer descriptor (BD) structure
@ -386,7 +483,6 @@ typedef _Packed struct
volatile uint8_t reserved1[0xa0]; /**< 0x60 - 0xff */
} _PackedType t_FmPortImPram;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
@ -399,36 +495,41 @@ typedef _Packed struct
/**************************************************************************//**
@Description BMI defines
*//***************************************************************************/
#if (DPAA_VERSION >= 11)
#define BMI_SP_ID_MASK 0xff000000
#define BMI_SP_ID_SHIFT 24
#define BMI_SP_EN 0x01000000
#endif /* (DPAA_VERSION >= 11) */
#define BMI_PORT_CFG_EN 0x80000000
#define BMI_PORT_CFG_EN_MACSEC 0x00800000
#define BMI_PORT_CFG_FDOVR 0x02000000
#define BMI_PORT_CFG_IM 0x01000000
#define BMI_PORT_CFG_AM 0x00000040
#define BMI_PORT_STATUS_BSY 0x80000000
#define BMI_COUNTERS_EN 0x80000000
#define BMI_DMA_ATTR_WRITE_OPTIMIZE 0x00100000
#define BMI_PORT_RFNE_FRWD_DCL4C 0x10000000
#define BMI_PORT_RFNE_FRWD_RPD 0x40000000
#define BMI_RFNE_FDCS_MASK 0xFF000000
#define BMI_RFNE_HXS_MASK 0x000000FF
#define BMI_CMD_MR_LEAC 0x00200000
#define BMI_CMD_MR_SLEAC 0x00100000
#define BMI_CMD_MR_MA 0x00080000
#define BMI_CMD_MR_DEAS 0x00040000
#define BMI_CMD_TX_MR_DEF (0)
#define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \
BMI_CMD_MR_SLEAC | \
BMI_CMD_MR_MA | \
BMI_CMD_MR_DEAS)
#define BMI_CMD_ATTR_ORDER 0x80000000
#define BMI_CMD_ATTR_SYNC 0x02000000
#define BMI_CMD_ATTR_MODE_MISS_ALLIGN_ADDR_EN 0x00080000
#define BMI_CMD_ATTR_MACCMD_MASK 0x0000ff00
#define BMI_CMD_ATTR_MACCMD_OVERRIDE 0x00008000
#define BMI_CMD_ATTR_MACCMD_SECURED 0x00001000
#define BMI_CMD_ATTR_MACCMD_SC_MASK 0x00000f00
#define BMI_EXT_BUF_POOL_VALID 0x80000000
#define BMI_EXT_BUF_POOL_EN_COUNTER 0x40000000
#define BMI_EXT_BUF_POOL_BACKUP 0x20000000
#define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000
#define BMI_STATUS_RX_MASK_UNUSED (uint32_t)(~(FM_PORT_FRM_ERR_DMA | \
FM_PORT_FRM_ERR_PHYSICAL | \
@ -444,11 +545,13 @@ typedef _Packed struct
FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \
FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \
FM_PORT_FRM_ERR_PRS_HDR_ERR | \
FM_PORT_FRM_ERR_PROCESS_TIMEOUT | \
FM_PORT_FRM_ERR_IPRE | \
FM_PORT_FRM_ERR_IPR_NCSP | \
FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW))
#define BMI_STATUS_OP_MASK_UNUSED (uint32_t)(BMI_STATUS_RX_MASK_UNUSED & \
~(FM_PORT_FRM_ERR_LENGTH | \
FM_PORT_FRM_ERR_NON_FM | \
FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT))
#define BMI_RATE_LIMIT_EN 0x80000000
@ -462,6 +565,7 @@ typedef _Packed struct
#define BMI_PRS_RESULT_HIGH 0x00000000
#define BMI_PRS_RESULT_LOW 0xFFFFFFFF
#define RX_ERRS_TO_ENQ (FM_PORT_FRM_ERR_DMA | \
FM_PORT_FRM_ERR_PHYSICAL | \
FM_PORT_FRM_ERR_SIZE | \
@ -473,27 +577,26 @@ typedef _Packed struct
FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \
FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \
FM_PORT_FRM_ERR_PRS_HDR_ERR | \
FM_PORT_FRM_ERR_PROCESS_TIMEOUT | \
FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW)
FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW | \
FM_PORT_FRM_ERR_IPRE)
#ifdef FM_CAPWAP_SUPPORT
#define OP_ERRS_TO_ENQ (RX_ERRS_TO_ENQ | \
FM_PORT_FRM_ERR_LENGTH | \
FM_PORT_FRM_ERR_NON_FM | \
FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT)
#else
#define OP_ERRS_TO_ENQ (RX_ERRS_TO_ENQ | \
FM_PORT_FRM_ERR_LENGTH | \
FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT)
#endif /* FM_CAPWAP_SUPPORT */
#define BMI_RX_FIFO_PRI_ELEVATION_MASK 0x03FF0000
#define BMI_RX_FIFO_THRESHOLD_MASK 0x000003FF
#define BMI_TX_FIFO_MIN_FILL_MASK 0x03FF0000
#define BMI_FIFO_PIPELINE_DEPTH_MASK 0x0000F000
#define BMI_TX_LOW_COMF_MASK 0x000003FF
/* shifts */
#define BMI_PORT_CFG_MS_SEL_SHIFT 16
#define BMI_DMA_ATTR_SWP_SHIFT 30
#define BMI_DMA_ATTR_IC_CACHE_SHIFT 28
#define BMI_DMA_ATTR_HDR_CACHE_SHIFT 26
#define BMI_DMA_ATTR_SG_CACHE_SHIFT 24
#define BMI_DMA_ATTR_IC_CACHE_SHIFT FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT
#define BMI_DMA_ATTR_HDR_CACHE_SHIFT FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT
#define BMI_DMA_ATTR_SG_CACHE_SHIFT FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT
#define BMI_IM_FOF_SHIFT 28
#define BMI_PR_PORTID_SHIFT 24
@ -504,14 +607,11 @@ typedef _Packed struct
#define BMI_RX_FRAME_END_CS_IGNORE_SHIFT 24
#define BMI_RX_FRAME_END_CUT_SHIFT 16
#define BMI_IC_TO_EXT_SHIFT 16
#define BMI_IC_FROM_INT_SHIFT 8
#define BMI_IC_SIZE_SHIFT 0
#define BMI_IC_SIZE_SHIFT FMAN_SP_IC_SIZE_SHIFT
#define BMI_INT_BUF_MARG_SHIFT 28
#define BMI_EXT_BUF_MARG_START_SHIFT 16
#define BMI_EXT_BUF_MARG_END_SHIFT 0
#define BMI_EXT_BUF_MARG_END_SHIFT FMAN_SP_EXT_BUF_MARG_END_SHIFT
#define BMI_CMD_ATTR_COLOR_SHIFT 26
#define BMI_CMD_ATTR_COM_MODE_SHIFT 16
@ -520,17 +620,11 @@ typedef _Packed struct
#define BMI_CMD_ATTR_MACCMD_SECURED_SHIFT 12
#define BMI_CMD_ATTR_MACCMD_SC_SHIFT 8
#define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16
#define BMI_POOL_DEP_NUM_OF_POOLS_VECTOR_SHIFT 24
#define BMI_EXT_BUF_POOL_ID_SHIFT 16
#define BMI_TX_FIFO_MIN_FILL_SHIFT 16
#define BMI_TX_FIFO_PIPELINE_DEPTH_SHIFT 12
#define BMI_TX_LOW_COMF_SHIFT 0
#define BMI_TX_FRAME_END_CS_IGNORE_SHIFT 24
#define BMI_PERFORMANCE_TASK_COMP_SHIFT 24
#define BMI_PERFORMANCE_PORT_COMP_SHIFT 16
#define BMI_PERFORMANCE_DMA_COMP_SHIFT 12
@ -541,13 +635,8 @@ typedef _Packed struct
/* sizes */
#define FRAME_END_DATA_SIZE 16
#define OFFSET_UNITS 16
#define FRAME_OFFSET_UNITS 16
#define MAX_EXT_OFFSET 496
#define MAX_EXT_BUFFER_OFFSET 511
#define MAX_INT_OFFSET 240
#define MIN_TX_INT_OFFSET 16
#define MAX_IC_SIZE 256
#define MAX_FRAME_OFFSET 64
#define MAX_FIFO_PIPELINE_DEPTH 8
#define MAX_PERFORMANCE_TASK_COMP 64
@ -559,7 +648,8 @@ typedef _Packed struct
#define MAX_NUM_OF_DMAS 16
#define MAX_NUM_OF_EXTRA_DMAS 8
#define MAX_BURST_SIZE 1024
#define FRAG_EXTRA_SPACE 32
#define MIN_NUM_OF_OP_DMAS 2
/**************************************************************************//**
@Description QMI defines
@ -595,7 +685,7 @@ typedef _Packed struct
#define PRS_TPID_DFLT 0x91009100
#define PRS_HDR_MPLS_LBL_INTER_EN 0x00200000
#define PRS_HDR_IPV6_ROUTE_HDR_DIS 0x00008000
#define PRS_HDR_IPV6_ROUTE_HDR_EN 0x00008000
#define PRS_HDR_PPPOE_MTU_CHECK_EN 0x80000000
#define PRS_HDR_UDP_PAD_REMOVAL 0x80000000
#define PRS_HDR_TCP_PAD_REMOVAL 0x80000000
@ -637,10 +727,6 @@ typedef _Packed struct
#define SCTP_SW_PATCH_START 0x4D
#define DCCP_SW_PATCH_START 0x41
#define IP_FRAG_SW_PATCH_IPv4 0x300
#define IP_FRAG_SW_PATCH_IPv6_0 0x320
#define IP_FRAG_SW_PATCH_IPv6_1 0x372
/**************************************************************************//**
@Description IM defines
*//***************************************************************************/
@ -653,7 +739,6 @@ typedef _Packed struct
#define BD_RX_OV 0x00010000
#define BD_RX_ERRORS (BD_RX_CRE | BD_RX_FTL | BD_RX_FTS | BD_RX_OV)
#define BD_ERROR_PASS_FRAME BD_RX_ERRORS
#define FM_IM_SIZEOF_BD sizeof(t_FmImBd)
@ -686,6 +771,11 @@ typedef _Packed struct
#define IM_EV_BSY 0x40000000
#define IM_EV_RX 0x80000000
/**************************************************************************//**
@Description Additional defines
*//***************************************************************************/
typedef struct {
t_Handle h_FmMuram;
t_FmPortImPram *p_FmPortImPram;
@ -710,41 +800,9 @@ typedef struct {
t_FmPortImTxConfCallback *f_TxConf;
} t_FmMacIm;
/**************************************************************************//**
@Description structure for defining internal context copying
*//***************************************************************************/
typedef struct
{
uint16_t extBufOffset; /**< Offset in External buffer to which internal
context is copied to (Rx) or taken from (Tx, Op). */
uint8_t intContextOffset; /**< Offset within internal context to copy from
(Rx) or to copy to (Tx, Op). */
uint16_t size; /**< Internal offset size to be copied */
} t_FmPortIntContextDataCopy;
/**************************************************************************//**
@Description struct for defining external buffer margins
*//***************************************************************************/
typedef struct {
uint16_t startMargins; /**< Number of bytes to be left at the beginning
of the external buffer (must be divisible by 16) */
uint16_t endMargins; /**< number of bytes to be left at the end
of the external buffer(must be divisible by 16) */
} t_FmPortBufMargins;
typedef struct {
uint32_t dataOffset;
uint32_t prsResultOffset;
uint32_t timeStampOffset;
uint32_t hashResultOffset;
uint32_t pcdInfoOffset;
uint32_t manipOffset;
#ifdef DEBUG
uint32_t debugOffset;
#endif /* DEBUG */
} t_FmPortBufferOffsets;
typedef struct {
struct fman_port_cfg dfltCfg;
uint32_t dfltFqid;
uint32_t confFqid;
uint32_t errFqid;
@ -752,13 +810,11 @@ typedef struct {
uint8_t deqSubPortal;
bool deqHighPriority;
e_FmPortDeqType deqType;
#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT
e_FmPortDeqPrefetchOption deqPrefetchOption;
#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */
uint16_t deqByteCnt;
uint8_t cheksumLastBytesIgnore;
uint8_t cutBytesFromEnd;
t_FmPortBufPoolDepletion bufPoolDepletion;
t_FmBufPoolDepletion bufPoolDepletion;
uint8_t pipelineDepth;
uint16_t fifoLowComfLevel;
bool frmDiscardOverride;
@ -768,34 +824,63 @@ typedef struct {
bool enBufPoolDepletion;
uint16_t liodnOffset;
uint16_t liodnBase;
t_FmPortExtPools extBufPools;
e_FmPortDmaSwap dmaSwapData;
e_FmPortDmaCache dmaIntContextCacheAttr;
e_FmPortDmaCache dmaHeaderCacheAttr;
e_FmPortDmaCache dmaScatterGatherCacheAttr;
t_FmExtPools extBufPools;
e_FmDmaSwapOption dmaSwapData;
e_FmDmaCacheOption dmaIntContextCacheAttr;
e_FmDmaCacheOption dmaHeaderCacheAttr;
e_FmDmaCacheOption dmaScatterGatherCacheAttr;
bool dmaReadOptimize;
bool dmaWriteOptimize;
uint32_t txFifoMinFillLevel;
uint32_t txFifoLowComfLevel;
uint32_t rxFifoPriElevationLevel;
uint32_t rxFifoThreshold;
t_FmPortBufMargins bufMargins;
t_FmPortIntContextDataCopy intContext;
t_FmSpBufMargins bufMargins;
t_FmSpIntContextDataCopy intContext;
bool syncReq;
e_FmPortColor color;
fmPortFrameErrSelect_t errorsToDiscard;
fmPortFrameErrSelect_t errorsToEnq;
uint64_t fmMuramPhysBaseAddr;
bool forwardReuseIntContext;
t_FmPortBufferPrefixContent bufferPrefixContent;
uint8_t internalBufferOffset;
t_FmPortBackupBmPools *p_BackupBmPools;
t_FmBufferPrefixContent bufferPrefixContent;
t_FmBackupBmPools *p_BackupBmPools;
bool dontReleaseBuf;
bool setNumOfTasks;
bool setNumOfOpenDmas;
bool setSizeOfFifo;
#if (DPAA_VERSION >= 11)
bool noScatherGather;
#endif /* (DPAA_VERSION >= 11) */
#ifdef FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669
bool bcbWorkaround;
#endif /* FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 */
} t_FmPortDriverParam;
typedef struct t_FmPortRxPoolsParams
{
uint8_t numOfPools;
uint16_t secondLargestBufSize;
uint16_t largestBufSize;
} t_FmPortRxPoolsParams;
typedef struct t_FmPortDsarVars {
t_Handle *autoResOffsets;
t_FmPortDsarTablesSizes *autoResMaxSizes;
uint32_t fmbm_tcfg;
uint32_t fmbm_tcmne;
uint32_t fmbm_rfne;
uint32_t fmbm_rfpne;
uint32_t fmbm_rcfg;
bool dsarEnabledParser;
} t_FmPortDsarVars;
typedef struct {
struct fman_port port;
t_Handle h_Fm;
t_Handle h_FmPcd;
t_Handle h_FmMuram;
t_FmRevisionInfo fmRevInfo;
uint8_t portId;
e_FmPortType portType;
int enabled;
@ -817,11 +902,10 @@ typedef struct {
t_Handle ccTreeId;
t_Handle completeArg;
void (*f_Complete)(t_Handle arg);
t_FmPortBufferOffsets bufferOffsets;
t_FmSpBufferOffsets bufferOffsets;
/* Independent-Mode parameters support */
bool imEn;
t_FmMacIm im;
uint8_t txFifoDeqPipelineDepth;
volatile bool lock;
t_Handle h_Spinlock;
t_FmPortExceptionCallback *f_Exception;
@ -830,23 +914,38 @@ typedef struct {
uint8_t fmanCtrlEventId;
uint32_t exceptions;
bool polling;
uint8_t numOfTasks;
t_FmPortExtPools extBufPools;
t_FmExtPools extBufPools;
uint32_t requiredAction;
uint32_t savedQmiPnen;
uint32_t savedBmiFene;
uint32_t savedBmiFpne;
uint32_t savedBmiCmne;
uint32_t savedBmiOfp;
uint32_t savedNonRxQmiRegsPndn;
uint32_t origNonRxQmiRegsPndn;
int savedPrsStartOffset;
bool includeInPrsStatistics;
uint16_t maxFrameLength;
t_FmFmanCtrl orFmanCtrl;
t_FmPortRsrc openDmas;
t_FmPortRsrc tasks;
t_FmPortRsrc fifoBufs;
t_FmInterModulePortRxPoolsParams rxPoolsParams;
t_FmPortRxPoolsParams rxPoolsParams;
// bool explicitUserSizeOfFifo;
t_Handle h_IpReassemblyManip;
t_Handle h_CapwapReassemblyManip;
t_Handle h_ReassemblyTree;
uint64_t fmMuramPhysBaseAddr;
#if (DPAA_VERSION >= 11)
bool vspe;
uint8_t dfltRelativeId;
e_FmPortGprFuncType gprFunc;
t_FmPcdCtrlParamsPage *p_ParamsPage;
#endif /* (DPAA_VERSION >= 11) */
t_FmPortDsarVars deepSleepVars;
t_FmPortDriverParam *p_FmPortDriverParam;
} t_FmPort;
#define CHECK_FM_CTL_AC_POST_FETCH_PCD(savedBmiNia) \
((((savedBmiNia) & NIA_ENG_MASK) == NIA_ENG_FM_CTL) && \
((((savedBmiNia) & NIA_FM_CTL_AC_MASK) == NIA_FM_CTL_AC_POST_FETCH_PCD) || \
(((savedBmiNia) & NIA_FM_CTL_AC_MASK) == NIA_FM_CTL_AC_POST_FETCH_PCD_UDP_LEN)))
void FmPortConfigIM (t_FmPort *p_FmPort, t_FmPortParams *p_FmPortParams);
t_Error FmPortImCheckInitParameters(t_FmPort *p_FmPort);
@ -862,6 +961,10 @@ void FmPortSetMacsecLcv(t_Handle h_FmPort);
void FmPortSetMacsecCmd(t_Handle h_FmPort, uint8_t dfltSci);
t_Error FM_PORT_SetNumOfOpenDmas(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfOpenDmas);
t_Error FM_PORT_SetNumOfTasks(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfTasks);
t_Error FM_PORT_SetSizeOfFifo(t_Handle h_FmPort, t_FmPortRsrc *p_SizeOfFifo);
static __inline__ uint8_t * BdBufferGet (t_PhysToVirt *f_PhysToVirt, t_FmImBd *p_Bd)
{
uint64_t physAddr = (uint64_t)((uint64_t)GET_UINT8(p_Bd->buff.high) << 32);
@ -890,5 +993,7 @@ static __inline__ uint16_t GetNextBdId(t_FmPort *p_FmPort, uint16_t id)
return 0;
}
void FM_PORT_Dsar_DumpRegs(void);
#endif /* __FM_PORT_H */

494
sys/contrib/ncsw/Peripherals/FM/Port/fm_port_dsar.h Executable file
View File

@ -0,0 +1,494 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_port_dsar.h
@Description Deep Sleep Auto Response project - common module header file.
Author - Eyal Harari
@Cautions See the FMan Controller spec and design document for more information.
*//***************************************************************************/
#ifndef __FM_PORT_DSAR_H_
#define __FM_PORT_DSAR_H_
#define DSAR_GETSER_MASK 0xFF0000FF
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description Deep Sleep Auto Response VLAN-IPv4 Binding Table (for ARP/ICMPv4)
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
typedef _Packed struct
{
uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */
uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */
/*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} _PackedType t_DsarArpBindingEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response Address Resolution Protocol Statistics Descriptor
Refer to the FMan Controller spec for more details.
0x00 INVAL_CNT Invalid ARP IPv4-Ethernet counter
0x04 ECHO_CNT Echo counter
0x08 CD_CNT Conflict Detection counter
0x0C AR_CNT Auto-Response counter
0x10 RATM_CNT Replies Addressed To Me counter
0x14 UKOP_CNT Unknown Operation counter
0x18 NMTP_CNT Not my TPA counter
0x1C NMVLAN_CNT Not My VLAN counter
*//***************************************************************************/
typedef _Packed struct
{
uint32_t invalCnt; /**< Invalid ARP IPv4-Ethernet counter. */
uint32_t echoCnt; /**< Echo counter. */
uint32_t cdCnt; /**< Conflict Detection counter. */
uint32_t arCnt; /**< Auto-Response counter. */
uint32_t ratmCnt; /**< Replies Addressed To Me counter. */
uint32_t ukopCnt; /**< Unknown Operation counter. */
uint32_t nmtpCnt; /**< Not my TPA counter. */
uint32_t nmVlanCnt; /**< Not My VLAN counter */
} _PackedType t_DsarArpStatistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response Address Resolution Protocol Descriptor
0x0 0-15 Control bits [0-15]. Bit 15 = CDEN.
0x2 0-15 NumOfBindings Number of entries in the binding list.
0x4 0-15 BindingsPointer Bindings Pointer. This points to an IPv4-MAC Addresses Bindings list.
0x6 0-15
0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ARP Descriptors statistics data structure.
0xA 0-15
0xC 0-15 Reserved Reserved. Must be cleared.
0xE 015
*//***************************************************************************/
typedef _Packed struct
{
uint16_t control; /** Control bits [0-15]. Bit 15 = CDEN */
uint16_t numOfBindings; /**< Number of VLAN-IPv4 */
uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */
uint32_t p_Statistics; /**< Statistics Data Structure pointer. */
uint32_t reserved1; /**< Reserved. */
} _PackedType t_DsarArpDescriptor;
/**************************************************************************//**
@Description Deep Sleep Auto Response VLAN-IPv4 Binding Table (for ARP/ICMPv4)
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
typedef _Packed struct
{
uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */
uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */
/*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} _PackedType t_DsarIcmpV4BindingEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv4 Statistics Descriptor
Refer to the FMan Controller spec for more details.
0x00 INVAL_CNT Invalid ICMPv4 header counter
0x04 NMVLAN_CNT Not My VLAN counter
0x08 NMIP_CNT Not My IP counter
0x0C AR_CNT Auto-Response counter
0x10 CSERR_CNT Checksum Error counter
0x14 Reserved Reserved
0x18 Reserved Reserved
0x1C Reserved Reserved
*//***************************************************************************/
typedef _Packed struct
{
uint32_t invalCnt; /**< Invalid ICMPv4 Echo counter. */
uint32_t nmVlanCnt; /**< Not My VLAN counter */
uint32_t nmIpCnt; /**< Not My IP counter */
uint32_t arCnt; /**< Auto-Response counter */
uint32_t cserrCnt; /**< Checksum Error counter */
uint32_t reserved0; /**< Reserved */
uint32_t reserved1; /**< Reserved */
uint32_t reserved2; /**< Reserved */
} _PackedType t_DsarIcmpV4Statistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv4 Descriptor
0x0 0-15 Control bits [0-15]
0x2 0-15 NumOfBindings Number of entries in the binding list.
0x4 0-15 BindingsPointer Bindings Pointer. This points to an VLAN-IPv4 Addresses Bindings list.
0x6 0-15
0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ICMPv4 statistics data structure.
0xA 0-15
0xC 0-15 Reserved Reserved. Must be cleared.
0xE 015
*//***************************************************************************/
typedef _Packed struct
{
uint16_t control; /** Control bits [0-15]. */
uint16_t numOfBindings; /**< Number of VLAN-IPv4 */
uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */
uint32_t p_Statistics; /**< Statistics Data Structure pointer. */
uint32_t reserved1; /**< Reserved. */
} _PackedType t_DsarIcmpV4Descriptor;
/**************************************************************************//**
@Description Deep Sleep Auto Response VLAN-IPv4 Binding Table (for ARP/ICMPv4)
The 4 left-most bits (15:12) of the VlanId parameter are control flags.
Flags[3:1] (VlanId[15:13]): Reserved, should be cleared.
Flags[0] (VlanId[12]): Temporary address.
• 0 - Assigned IP address.
• 1- Temporary (tentative) IP address.
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
typedef _Packed struct
{
uint32_t ipv6Addr[4]; /*!< 3 * 32 bit IPv4 Address. */
uint16_t resFlags:4; /*!< reserved flags. should be cleared */
uint16_t vlanId:12; /*!< 12 bits VLAN ID. */
/*!< This field should be 0x000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} _PackedType t_DsarIcmpV6BindingEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv4 Statistics Descriptor
Refer to the FMan Controller spec for more details.
0x00 INVAL_CNT Invalid ICMPv4 header counter
0x04 NMVLAN_CNT Not My VLAN counter
0x08 NMIP_CNT Not My IP counter
0x0C AR_CNT Auto-Response counter
0x10 CSERR_CNT Checksum Error counter
0x14 MCAST_CNT Multicast counter
0x18 Reserved Reserved
0x1C Reserved Reserved
*//***************************************************************************/
typedef _Packed struct
{
uint32_t invalCnt; /**< Invalid ICMPv4 Echo counter. */
uint32_t nmVlanCnt; /**< Not My VLAN counter */
uint32_t nmIpCnt; /**< Not My IP counter */
uint32_t arCnt; /**< Auto-Response counter */
uint32_t reserved1; /**< Reserved */
uint32_t reserved2; /**< Reserved */
uint32_t reserved3; /**< Reserved */
uint32_t reserved4; /**< Reserved */
} _PackedType t_DsarIcmpV6Statistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response Neighbor Discovery Statistics Descriptor
0x00 INVAL_CNT Invalid Neighbor Discovery message counter
0x04 NMVLAN_CNT Not My VLAN counter
0x08 NMIP_CNT Not My IP counter
0x0C AR_CNT Auto-Response counter
0x10 CSERR_CNT Checksum Error counter
0x14 USADVERT_CNT Unsolicited Neighbor Advertisements counter
0x18 NMMCAST_CNT Not My Multicast group counter
0x1C NSLLA_CNT No Source Link-Layer Address counter. Indicates that there was a match on a Target
Address of a packet that its source IP address is a unicast address, but the ICMPv6
Source Link-layer Address option is omitted
*//***************************************************************************/
typedef _Packed struct
{
uint32_t invalCnt; /**< Invalid ICMPv4 Echo counter. */
uint32_t nmVlanCnt; /**< Not My VLAN counter */
uint32_t nmIpCnt; /**< Not My IP counter */
uint32_t arCnt; /**< Auto-Response counter */
uint32_t reserved1; /**< Reserved */
uint32_t usadvertCnt; /**< Unsolicited Neighbor Advertisements counter */
uint32_t nmmcastCnt; /**< Not My Multicast group counter */
uint32_t nsllaCnt; /**< No Source Link-Layer Address counter */
} _PackedType t_NdStatistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv6 Descriptor
0x0 0-15 Control bits [0-15]
0x2 0-15 NumOfBindings Number of entries in the binding list.
0x4 0-15 BindingsPointer Bindings Pointer. This points to an VLAN-IPv4 Addresses Bindings list.
0x6 0-15
0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ICMPv4 statistics data structure.
0xA 0-15
0xC 0-15 Reserved Reserved. Must be cleared.
0xE 015
*//***************************************************************************/
typedef _Packed struct
{
uint16_t control; /** Control bits [0-15]. */
uint16_t numOfBindings; /**< Number of VLAN-IPv6 */
uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */
uint32_t p_Statistics; /**< Statistics Data Structure pointer. */
uint32_t reserved1; /**< Reserved. */
} _PackedType t_DsarIcmpV6Descriptor;
/**************************************************************************//**
@Description Internet Control Message Protocol (ICMPv6) Echo message header
The fields names are taken from RFC 4443.
*//***************************************************************************/
/* 0 1 2 3 */
/* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 */
/* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */
/* | Type | Code | Checksum | */
/* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */
/* | Identifier | Sequence Number | */
/* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */
/* | Data ... */
/* +-+-+-+-+- */
typedef _Packed struct
{
uint8_t type;
uint8_t code;
uint16_t checksum;
uint16_t identifier;
uint16_t sequenceNumber;
} _PackedType t_IcmpV6EchoHdr;
/**************************************************************************//**
@Description Internet Control Message Protocol (ICMPv6)
Neighbor Solicitation/Advertisement header
The fields names are taken from RFC 4861.
The R/S/O fields are valid for Neighbor Advertisement only
*//***************************************************************************/
/* 0 1 2 3
* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Type | Code | Checksum |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |R|S|O| Reserved |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | |
* + +
* | |
* + Target Address +
* | |
* + +
* | |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Options ...
* +-+-+-+-+-+-+-+-+-+-+-+-
*
* Options Format:
* 0 1 2 3
* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Type | Length | Link-Layer Address ... |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Link-Layer Address |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
typedef _Packed struct
{
uint8_t type;
uint8_t code;
uint16_t checksum;
uint32_t router:1;
uint32_t solicited:1;
uint32_t override:1;
uint32_t reserved:29;
uint32_t targetAddr[4];
uint8_t optionType;
uint8_t optionLength;
uint8_t linkLayerAddr[6];
} _PackedType t_IcmpV6NdHdr;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv6 Descriptor
0x0 0-15 Control bits [0-15]
0x2 0-15 NumOfBindings Number of entries in the binding list.
0x4 0-15 BindingsPointer Bindings Pointer. This points to an VLAN-IPv4 Addresses Bindings list.
0x6 0-15
0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ICMPv4 statistics data structure.
0xA 0-15
0xC 0-15 Reserved Reserved. Must be cleared.
0xE 015
*//***************************************************************************/
typedef _Packed struct
{
uint16_t control; /** Control bits [0-15]. */
uint16_t numOfBindings; /**< Number of VLAN-IPv6 */
uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */
uint32_t p_Statistics; /**< Statistics Data Structure pointer. */
uint32_t solicitedAddr; /**< Solicited Node Multicast Group Address */
} _PackedType t_DsarNdDescriptor;
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP OIDs table entry
*//***************************************************************************/
typedef struct {
uint16_t oidSize; /**< Size in octets of the OID. */
uint16_t resSize; /**< Size in octets of the value that is attached to the OID. */
uint32_t p_Oid; /**< Pointer to the OID. OID is encoded in BER but type and length are excluded. */
uint32_t resValOrPtr; /**< Value (for up to 4 octets) or pointer to the Value. Encoded in BER. */
uint32_t reserved;
} t_OidsTblEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP IPv4 Addresses Table Entry
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
typedef struct
{
uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */
uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */
/*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} t_DsarSnmpIpv4AddrTblEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP IPv6 Addresses Table Entry
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
#pragma pack(push,1)
typedef struct
{
uint32_t ipv6Addr[4]; /*!< 4 * 32 bit IPv6 Address. */
uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */
/*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} t_DsarSnmpIpv6AddrTblEntry;
#pragma pack(pop)
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP statistics table
*//***************************************************************************/
typedef struct {
uint32_t snmpErrCnt; /**< Counts SNMP errors (wrong version, BER encoding, format). */
uint32_t snmpCommunityErrCnt; /**< Counts messages that were dropped due to insufficient permission. */
uint32_t snmpTotalDiscardCnt; /**< Counts any message that was dropped. */
uint32_t snmpGetReqCnt; /**< Counts the number of get-request messages */
uint32_t snmpGetNextReqCnt; /**< Counts the number of get-next-request messages */
} t_DsarSnmpStatistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP Descriptor
*//***************************************************************************/
typedef struct
{
uint16_t control; /**< Control bits [0-15]. */
uint16_t maxSnmpMsgLength; /**< Maximal allowed SNMP message length. */
uint16_t numOfIpv4Addresses; /**< Number of entries in IPv4 addresses table. */
uint16_t numOfIpv6Addresses; /**< Number of entries in IPv6 addresses table. */
uint32_t p_Ipv4AddrTbl; /**< Pointer to IPv4 addresses table. */
uint32_t p_Ipv6AddrTbl; /**< Pointer to IPv6 addresses table. */
uint32_t p_RdOnlyCommunityStr; /**< Pointer to the Read Only Community String. */
uint32_t p_RdWrCommunityStr; /**< Pointer to the Read Write Community String. */
uint32_t p_OidsTbl; /**< Pointer to OIDs table. */
uint32_t oidsTblSize; /**< Number of entries in OIDs table. */
uint32_t p_Statistics; /**< Pointer to SNMP statistics table. */
} t_DsarSnmpDescriptor;
/**************************************************************************//**
@Description Deep Sleep Auto Response (Common) Statistics
*//***************************************************************************/
typedef _Packed struct {
uint32_t dsarDiscarded;
uint32_t dsarErrDiscarded;
uint32_t dsarFragDiscarded;
uint32_t dsarTunnelDiscarded;
uint32_t dsarArpDiscarded;
uint32_t dsarIpDiscarded;
uint32_t dsarTcpDiscarded;
uint32_t dsarUdpDiscarded;
uint32_t dsarIcmpV6ChecksumErr; /* ICMPv6 Checksum Error counter */
uint32_t dsarIcmpV6OtherType; /* ICMPv6 'Other' type (not Echo or Neighbor Solicitaion/Advertisement counter */
uint32_t dsarIcmpV4OtherType; /* ICMPv4 'Other' type (not Echo) counter */
} _PackedType t_ArStatistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response TCP/UDP port filter table entry
*//***************************************************************************/
typedef _Packed struct {
uint32_t Ports;
uint32_t PortsMask;
} _PackedType t_PortTblEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response Common Parameters Descriptor
*//***************************************************************************/
typedef _Packed struct {
uint8_t arTxPort; /* 0x00 0-7 Auto Response Transmit Port number */
uint8_t controlBits; /* 0x00 8-15 Auto Response control bits */
uint16_t res1; /* 0x00 16-31 Reserved */
uint32_t activeHPNIA; /* 0x04 0-31 Active mode Hardware Parser NIA */
uint16_t snmpPort; /* 0x08 0-15 SNMP Port. */
uint8_t macStationAddr[6]; /* 0x08 16-31 and 0x0C 0-31 MAC Station Address */
uint8_t res2; /* 0x10 0-7 Reserved */
uint8_t filterControl; /* 0x10 8-15 Filtering Control Bits. */
uint16_t tcpControlPass; /* 0x10 16-31 TCP control pass flags */
uint8_t ipProtocolTblSize; /* 0x14 0-7 IP Protocol Table Size. */
uint8_t udpPortTblSize; /* 0x14 8-15 UDP Port Table Size. */
uint8_t tcpPortTblSize; /* 0x14 16-23 TCP Port Table Size. */
uint8_t res3; /* 0x14 24-31 Reserved */
uint32_t p_IpProtocolFiltTbl; /* 0x18 0-31 Pointer to IP Protocol Filter Table */
uint32_t p_UdpPortFiltTbl; /* 0x1C 0-31 Pointer to UDP Port Filter Table */
uint32_t p_TcpPortFiltTbl; /* 0x20 0-31 Pointer to TCP Port Filter Table */
uint32_t res4; /* 0x24 Reserved */
uint32_t p_ArpDescriptor; /* 0x28 0-31 ARP Descriptor Pointer. */
uint32_t p_NdDescriptor; /* 0x2C 0-31 Neighbor Discovery Descriptor. */
uint32_t p_IcmpV4Descriptor; /* 0x30 0-31 ICMPv4 Descriptor pointer. */
uint32_t p_IcmpV6Descriptor; /* 0x34 0-31 ICMPv6 Descriptor pointer. */
uint32_t p_SnmpDescriptor; /* 0x38 0-31 SNMP Descriptor pointer. */
uint32_t p_ArStats; /* 0x3C 0-31 Pointer to Auto Response Statistics */
} _PackedType t_ArCommonDesc;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/* t_ArCommonDesc.filterControl bits */
#define IP_PROT_TBL_PASS_MASK 0x08
#define UDP_PORT_TBL_PASS_MASK 0x04
#define TCP_PORT_TBL_PASS_MASK 0x02
/* Offset of TCF flags within TCP packet */
#define TCP_FLAGS_OFFSET 12
#endif /* __FM_PORT_DSAR_H_ */

88
sys/contrib/ncsw/Peripherals/FM/Port/fm_port_im.c
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_port_im.c
@ -38,6 +39,7 @@
#include "std_ext.h"
#include "string_ext.h"
#include "error_ext.h"
#include "memcpy_ext.h"
#include "fm_muram_ext.h"
#include "fm_port.h"
@ -45,25 +47,6 @@
#define TX_CONF_STATUS_UNSENT 0x1
#ifdef CORE_8BIT_ACCESS_ERRATA
#undef WRITE_UINT16
#undef GET_UINT16
#define WRITE_UINT16(addr, val) \
do{ \
if((int)&(addr) % 4) \
WRITE_UINT32(*(uint32_t*)(uint32_t)((uint32_t)&addr & ~0x3L), \
((GET_UINT32(*(uint32_t*)(uint32_t)((uint32_t)&addr & ~0x3L)) & 0xffff0000) | (uint32_t)val)); \
else \
WRITE_UINT32(*(uint32_t*)&addr, \
((GET_UINT32(*(uint32_t*)&addr) & 0x0000ffff) | (uint32_t)val<<16)); \
}while(0);
#define GET_UINT16(addr) (((uint32_t)&addr%4) ? \
((uint16_t)GET_UINT32(*(uint32_t*)(uint32_t)((uint32_t)&addr & ~0x3L))): \
((uint16_t)(GET_UINT32(*(uint32_t*)(uint32_t)&addr) >> 16)))
#endif /* CORE_8BIT_ACCESS_ERRATA */
typedef enum e_TxConfType
{
@ -77,7 +60,7 @@ static void ImException(t_Handle h_FmPort, uint32_t event)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
ASSERT_COND(((event & IM_EV_RX) && FmIsMaster(p_FmPort->h_Fm)) ||
ASSERT_COND(((event & (IM_EV_RX | IM_EV_BSY)) && FmIsMaster(p_FmPort->h_Fm)) ||
!FmIsMaster(p_FmPort->h_Fm));
if (event & IM_EV_RX)
@ -158,7 +141,7 @@ t_Error FmPortImRx(t_FmPort *p_FmPort)
uint32_t bdStatus;
volatile uint8_t buffPos;
uint16_t length;
uint16_t errors/*, reportErrors*/;
uint16_t errors;
uint8_t *p_CurData, *p_Data;
uint32_t flags;
@ -186,7 +169,6 @@ t_Error FmPortImRx(t_FmPort *p_FmPort)
if (p_FmPort->im.firstBdOfFrameId == IM_ILEGAL_BD_ID)
p_FmPort->im.firstBdOfFrameId = p_FmPort->im.currBdId;
errors = 0;
p_CurData = BdBufferGet(p_FmPort->im.rxPool.f_PhysToVirt, BD_GET(p_FmPort->im.currBdId));
h_CurrUserPriv = p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId];
length = (uint16_t)((bdStatus & BD_L) ?
@ -217,9 +199,8 @@ t_Error FmPortImRx(t_FmPort *p_FmPort)
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.offsetOut, (uint16_t)(p_FmPort->im.currBdId<<4));
/* Pass the buffer if one of the conditions is true:
- There are no errors
- This is a part of a larger frame ( the application has already received some buffers )
- There is an error, but it was defined to be passed anyway. */
if ((buffPos != SINGLE_BUF) || !errors || (errors & (uint16_t)(BD_ERROR_PASS_FRAME>>16)))
- This is a part of a larger frame ( the application has already received some buffers ) */
if ((buffPos != SINGLE_BUF) || !errors)
{
if (p_FmPort->im.f_RxStore(p_FmPort->h_App,
p_CurData,
@ -282,7 +263,7 @@ void FmPortConfigIM (t_FmPort *p_FmPort, t_FmPortParams *p_FmPortParams)
if (p_FmPort->im.mrblr != p_FmPort->im.rxPool.bufferSize)
DBG(WARNING, ("Max-Rx-Buffer-Length set to %d", p_FmPort->im.mrblr));
p_FmPort->im.bdRingSize = DEFAULT_PORT_rxBdRingLength;
p_FmPort->exceptions = DEFAULT_exception;
p_FmPort->exceptions = DEFAULT_PORT_exception;
if (FmIsMaster(p_FmPort->h_Fm))
p_FmPort->polling = FALSE;
else
@ -312,28 +293,8 @@ t_Error FmPortImCheckInitParameters(t_FmPort *p_FmPort)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("max Rx buffer length must be power of 2!!!"));
if (p_FmPort->im.mrblr < 256)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("max Rx buffer length must at least 256!!!"));
if(p_FmPort->p_FmPortDriverParam->liodnOffset & ~FM_LIODN_OFFSET_MASK)
if (p_FmPort->p_FmPortDriverParam->liodnOffset & ~FM_LIODN_OFFSET_MASK)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("liodnOffset is larger than %d", FM_LIODN_OFFSET_MASK+1));
#ifdef FM_PARTITION_ARRAY
{
t_FmRevisionInfo revInfo;
FM_GetRevision(p_FmPort->h_Fm, &revInfo);
if ((revInfo.majorRev == 1) && (revInfo.minorRev == 0))
{
if(p_FmPort->p_FmPortDriverParam->liodnOffset >= MAX_LIODN_OFFSET)
{
p_FmPort->p_FmPortDriverParam->liodnOffset =
(uint16_t)(p_FmPort->p_FmPortDriverParam->liodnOffset & (MAX_LIODN_OFFSET-1));
DBG(WARNING, ("liodnOffset number is out of rev1 range - MSB bits cleard."));
}
}
}
#endif /* FM_PARTITION_ARRAY */
/* TODO - add checks */
}
else
{
/* TODO - add checks */
}
return E_OK;
@ -362,7 +323,10 @@ t_Error FmPortImInit(t_FmPort *p_FmPort)
if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) ||
(p_FmPort->portType == e_FM_PORT_TYPE_RX_10G))
{
p_FmPort->im.p_BdRing = (t_FmImBd *)XX_MallocSmart((uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize), p_FmPort->im.fwExtStructsMemId, 4);
p_FmPort->im.p_BdRing =
(t_FmImBd *)XX_MallocSmart((uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize),
p_FmPort->im.fwExtStructsMemId,
4);
if (!p_FmPort->im.p_BdRing)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD ring!!!"));
IOMemSet32(p_FmPort->im.p_BdRing, 0, (uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize));
@ -392,7 +356,7 @@ t_Error FmPortImInit(t_FmPort *p_FmPort)
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->rxQdPtr,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->p_FmPortDriverParam->fmMuramPhysBaseAddr + 0x20));
p_FmPort->fmMuramPhysBaseAddr + 0x20));
LOG2((uint64_t)p_FmPort->im.mrblr, log2Num);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->mrblr, log2Num);
@ -405,24 +369,24 @@ t_Error FmPortImInit(t_FmPort *p_FmPort)
/* Update the IM PRAM address in the BMI */
WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfqid,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->p_FmPortDriverParam->fmMuramPhysBaseAddr));
p_FmPort->fmMuramPhysBaseAddr));
if (!p_FmPort->polling || p_FmPort->exceptions)
{
/* Allocate, configure and register interrupts */
err = FmAllocFmanCtrlEventReg(p_FmPort->h_Fm, &p_FmPort->fmanCtrlEventId);
if(err)
if (err)
RETURN_ERROR(MAJOR, err, NO_MSG);
ASSERT_COND(!(p_FmPort->fmanCtrlEventId & ~IM_RXQD_FPMEVT_SEL_MASK));
tmpReg16 = (uint16_t)(p_FmPort->fmanCtrlEventId & IM_RXQD_FPMEVT_SEL_MASK);
tmpReg32 = 0;
if(p_FmPort->exceptions & IM_EV_BSY)
if (p_FmPort->exceptions & IM_EV_BSY)
{
tmpReg16 |= IM_RXQD_BSYINTM;
tmpReg32 |= IM_EV_BSY;
}
if(!p_FmPort->polling)
if (!p_FmPort->polling)
{
tmpReg16 |= IM_RXQD_RXFINTM;
tmpReg32 |= IM_EV_RX;
@ -457,7 +421,7 @@ t_Error FmPortImInit(t_FmPort *p_FmPort)
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->txQdPtr,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->p_FmPortDriverParam->fmMuramPhysBaseAddr + 0x40));
p_FmPort->fmMuramPhysBaseAddr + 0x40));
/* Initialize Tx QD */
tmpPhysBase = (uint64_t)(XX_VirtToPhys(p_FmPort->im.p_BdRing));
@ -467,7 +431,7 @@ t_Error FmPortImInit(t_FmPort *p_FmPort)
/* Update the IM PRAM address in the BMI */
WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcfqid,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->p_FmPortDriverParam->fmMuramPhysBaseAddr));
p_FmPort->fmMuramPhysBaseAddr));
}
@ -593,7 +557,7 @@ t_Error FM_PORT_ConfigIMPolling(t_Handle h_FmPort)
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
if((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) && (p_FmPort->portType != e_FM_PORT_TYPE_RX))
if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) && (p_FmPort->portType != e_FM_PORT_TYPE_RX))
RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("Available for Rx ports only"));
if (!FmIsMaster(p_FmPort->h_Fm))
@ -616,16 +580,16 @@ t_Error FM_PORT_SetIMExceptions(t_Handle h_FmPort, e_FmPortExceptions exception,
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
if(exception == e_FM_PORT_EXCEPTION_IM_BUSY)
if (exception == e_FM_PORT_EXCEPTION_IM_BUSY)
{
if(enable)
if (enable)
{
p_FmPort->exceptions |= IM_EV_BSY;
if(p_FmPort->fmanCtrlEventId == (uint8_t)NO_IRQ)
if (p_FmPort->fmanCtrlEventId == (uint8_t)NO_IRQ)
{
/* Allocate, configure and register interrupts */
err = FmAllocFmanCtrlEventReg(p_FmPort->h_Fm, &p_FmPort->fmanCtrlEventId);
if(err)
if (err)
RETURN_ERROR(MAJOR, err, NO_MSG);
ASSERT_COND(!(p_FmPort->fmanCtrlEventId & ~IM_RXQD_FPMEVT_SEL_MASK));

1568
sys/contrib/ncsw/Peripherals/FM/Port/fman_port.c Executable file
View File

File diff suppressed because it is too large Load Diff

469
sys/contrib/ncsw/Peripherals/FM/Rtc/fm_rtc.c
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_rtc.c
@ -37,7 +38,7 @@
@Cautions None
*//***************************************************************************/
#include <linux/math64.h>
#include "error_ext.h"
#include "debug_ext.h"
#include "string_ext.h"
@ -49,38 +50,16 @@
#include "fm_common.h"
/*****************************************************************************/
static void SetDefaultParam(t_FmRtc *p_Rtc)
{
t_FmRtcDriverParam *p_RtcDriverParam = p_Rtc->p_RtcDriverParam;
int i;
p_Rtc->outputClockDivisor = DEFAULT_outputClockDivisor;
p_Rtc->p_RtcDriverParam->bypass = DEFAULT_bypass;
p_RtcDriverParam->srcClk = DEFAULT_srcClock;
p_RtcDriverParam->invertInputClkPhase = DEFAULT_invertInputClkPhase;
p_RtcDriverParam->invertOutputClkPhase = DEFAULT_invertOutputClkPhase;
p_RtcDriverParam->pulseRealign = DEFAULT_pulseRealign;
for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++)
{
p_RtcDriverParam->alarmPolarity[i] = DEFAULT_alarmPolarity;
}
for (i=0; i < FM_RTC_NUM_OF_EXT_TRIGGERS; i++)
{
p_RtcDriverParam->triggerPolarity[i] = DEFAULT_triggerPolarity;
}
p_Rtc->clockPeriodNanoSec = DEFAULT_clockPeriod; /* 1 usec */
}
/*****************************************************************************/
static t_Error CheckInitParameters(t_FmRtc *p_Rtc)
{
t_FmRtcDriverParam *p_RtcDriverParam = p_Rtc->p_RtcDriverParam;
struct rtc_cfg *p_RtcDriverParam = p_Rtc->p_RtcDriverParam;
int i;
if ((p_RtcDriverParam->srcClk != e_FM_RTC_SOURCE_CLOCK_EXTERNAL) &&
(p_RtcDriverParam->srcClk != e_FM_RTC_SOURCE_CLOCK_SYSTEM) &&
(p_RtcDriverParam->srcClk != e_FM_RTC_SOURCE_CLOCK_OSCILATOR))
if ((p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_EXTERNAL) &&
(p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_SYSTEM) &&
(p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR))
RETURN_ERROR(MAJOR, E_INVALID_CLOCK, ("Source clock undefined"));
if (p_Rtc->outputClockDivisor == 0)
@ -91,31 +70,21 @@ static t_Error CheckInitParameters(t_FmRtc *p_Rtc)
for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++)
{
if ((p_RtcDriverParam->alarmPolarity[i] != e_FM_RTC_ALARM_POLARITY_ACTIVE_LOW) &&
(p_RtcDriverParam->alarmPolarity[i] != e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH))
if ((p_RtcDriverParam->alarm_polarity[i] != E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW) &&
(p_RtcDriverParam->alarm_polarity[i] != E_FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH))
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm %d signal polarity", i));
}
}
for (i=0; i < FM_RTC_NUM_OF_EXT_TRIGGERS; i++)
{
if ((p_RtcDriverParam->triggerPolarity[i] != e_FM_RTC_TRIGGER_ON_FALLING_EDGE) &&
(p_RtcDriverParam->triggerPolarity[i] != e_FM_RTC_TRIGGER_ON_RISING_EDGE))
if ((p_RtcDriverParam->trigger_polarity[i] != E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE) &&
(p_RtcDriverParam->trigger_polarity[i] != E_FMAN_RTC_TRIGGER_ON_RISING_EDGE))
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Trigger %d signal polarity", i));
}
}
#ifdef FM_1588_SRC_CLK_ERRATA_FMAN1
{
t_FmRevisionInfo revInfo;
FM_GetRevision(p_Rtc->h_Fm, &revInfo);
if ((revInfo.majorRev == 1) && (revInfo.minorRev == 0)&&
((p_RtcDriverParam->srcClk==e_FM_RTC_SOURCE_CLOCK_SYSTEM) && p_RtcDriverParam->invertInputClkPhase))
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Can not use invertInputClkPhase when source clock is e_FM_RTC_SOURCE_CLOCK_SYSTEM"));
}
#endif /* FM_1588_SRC_CLK_ERRATA_FMAN1 */
return E_OK;
}
@ -123,55 +92,49 @@ static t_Error CheckInitParameters(t_FmRtc *p_Rtc)
static void RtcExceptions(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcMemMap *p_MemMap;
struct rtc_regs *p_MemMap;
register uint32_t events;
ASSERT_COND(p_Rtc);
p_MemMap = p_Rtc->p_MemMap;
/* Get valid events */
events = GET_UINT32(p_MemMap->tmr_tevent);
events &= GET_UINT32(p_MemMap->tmr_temask);
/* Clear event bits */
WRITE_UINT32(p_MemMap->tmr_tevent, events);
if (events & TMR_TEVENT_ALM1)
events = fman_rtc_check_and_clear_event(p_MemMap);
if (events & FMAN_RTC_TMR_TEVENT_ALM1)
{
if(p_Rtc->alarmParams[0].clearOnExpiration)
if (p_Rtc->alarmParams[0].clearOnExpiration)
{
WRITE_UINT32(p_MemMap->tmr_alarm[0].tmr_alarm_l, 0);
WRITE_UINT32(p_MemMap->tmr_temask, GET_UINT32(p_MemMap->tmr_temask) & ~TMR_TEVENT_ALM1);
fman_rtc_set_timer_alarm_l(p_MemMap, 0, 0);
fman_rtc_disable_interupt(p_MemMap, FMAN_RTC_TMR_TEVENT_ALM1);
}
ASSERT_COND(p_Rtc->alarmParams[0].f_AlarmCallback);
p_Rtc->alarmParams[0].f_AlarmCallback(p_Rtc->h_App, 0);
}
if (events & TMR_TEVENT_ALM2)
if (events & FMAN_RTC_TMR_TEVENT_ALM2)
{
if(p_Rtc->alarmParams[1].clearOnExpiration)
if (p_Rtc->alarmParams[1].clearOnExpiration)
{
WRITE_UINT32(p_MemMap->tmr_alarm[1].tmr_alarm_l, 0);
WRITE_UINT32(p_MemMap->tmr_temask, GET_UINT32(p_MemMap->tmr_temask) & ~TMR_TEVENT_ALM2);
fman_rtc_set_timer_alarm_l(p_MemMap, 1, 0);
fman_rtc_disable_interupt(p_MemMap, FMAN_RTC_TMR_TEVENT_ALM2);
}
ASSERT_COND(p_Rtc->alarmParams[1].f_AlarmCallback);
p_Rtc->alarmParams[1].f_AlarmCallback(p_Rtc->h_App, 1);
}
if (events & TMR_TEVENT_PP1)
if (events & FMAN_RTC_TMR_TEVENT_PP1)
{
ASSERT_COND(p_Rtc->periodicPulseParams[0].f_PeriodicPulseCallback);
p_Rtc->periodicPulseParams[0].f_PeriodicPulseCallback(p_Rtc->h_App, 0);
}
if (events & TMR_TEVENT_PP2)
if (events & FMAN_RTC_TMR_TEVENT_PP2)
{
ASSERT_COND(p_Rtc->periodicPulseParams[1].f_PeriodicPulseCallback);
p_Rtc->periodicPulseParams[1].f_PeriodicPulseCallback(p_Rtc->h_App, 1);
}
if (events & TMR_TEVENT_ETS1)
if (events & FMAN_RTC_TMR_TEVENT_ETS1)
{
ASSERT_COND(p_Rtc->externalTriggerParams[0].f_ExternalTriggerCallback);
p_Rtc->externalTriggerParams[0].f_ExternalTriggerCallback(p_Rtc->h_App, 0);
}
if (events & TMR_TEVENT_ETS2)
if (events & FMAN_RTC_TMR_TEVENT_ETS2)
{
ASSERT_COND(p_Rtc->externalTriggerParams[1].f_ExternalTriggerCallback);
p_Rtc->externalTriggerParams[1].f_ExternalTriggerCallback(p_Rtc->h_App, 1);
@ -197,7 +160,7 @@ t_Handle FM_RTC_Config(t_FmRtcParams *p_FmRtcParam)
memset(p_Rtc, 0, sizeof(t_FmRtc));
/* Allocate memory for the FM RTC driver parameters */
p_Rtc->p_RtcDriverParam = (t_FmRtcDriverParam *)XX_Malloc(sizeof(t_FmRtcDriverParam));
p_Rtc->p_RtcDriverParam = (struct rtc_cfg *)XX_Malloc(sizeof(struct rtc_cfg));
if (!p_Rtc->p_RtcDriverParam)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM RTC driver parameters"));
@ -205,16 +168,21 @@ t_Handle FM_RTC_Config(t_FmRtcParams *p_FmRtcParam)
return NULL;
}
memset(p_Rtc->p_RtcDriverParam, 0, sizeof(t_FmRtcDriverParam));
memset(p_Rtc->p_RtcDriverParam, 0, sizeof(struct rtc_cfg));
/* Store RTC configuration parameters */
p_Rtc->h_Fm = p_FmRtcParam->h_Fm;
/* Set default RTC configuration parameters */
SetDefaultParam(p_Rtc);
fman_rtc_defconfig(p_Rtc->p_RtcDriverParam);
p_Rtc->outputClockDivisor = DEFAULT_OUTPUT_CLOCK_DIVISOR;
p_Rtc->p_RtcDriverParam->bypass = DEFAULT_BYPASS;
p_Rtc->clockPeriodNanoSec = DEFAULT_CLOCK_PERIOD; /* 1 usec */
/* Store RTC parameters in the RTC control structure */
p_Rtc->p_MemMap = (t_FmRtcMemMap *)UINT_TO_PTR(p_FmRtcParam->baseAddress);
p_Rtc->p_MemMap = (struct rtc_regs *)UINT_TO_PTR(p_FmRtcParam->baseAddress);
p_Rtc->h_App = p_FmRtcParam->h_App;
return p_Rtc;
@ -224,119 +192,57 @@ t_Handle FM_RTC_Config(t_FmRtcParams *p_FmRtcParam)
t_Error FM_RTC_Init(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcDriverParam *p_RtcDriverParam;
t_FmRtcMemMap *p_MemMap;
uint32_t freqCompensation;
uint32_t tmrCtrl;
int i;
struct rtc_cfg *p_RtcDriverParam;
struct rtc_regs *p_MemMap;
uint32_t freqCompensation = 0;
uint64_t tmpDouble;
bool init_freq_comp = FALSE;
p_RtcDriverParam = p_Rtc->p_RtcDriverParam;
p_MemMap = p_Rtc->p_MemMap;
if(CheckInitParameters(p_Rtc)!=E_OK)
if (CheckInitParameters(p_Rtc)!=E_OK)
RETURN_ERROR(MAJOR, E_CONFLICT,
("Init Parameters are not Valid"));
/* TODO A check must be added here, that no timestamping MAC's
* are working in this stage. */
WRITE_UINT32(p_MemMap->tmr_ctrl, TMR_CTRL_TMSR);
XX_UDelay(10);
WRITE_UINT32(p_MemMap->tmr_ctrl, 0);
/* Set the source clock */
switch (p_RtcDriverParam->srcClk)
{
case e_FM_RTC_SOURCE_CLOCK_SYSTEM:
tmrCtrl = TMR_CTRL_CKSEL_MAC_CLK;
break;
case e_FM_RTC_SOURCE_CLOCK_OSCILATOR:
tmrCtrl = TMR_CTRL_CKSEL_OSC_CLK;
break;
default:
/* Use a clock from the External TMR reference clock.*/
tmrCtrl = TMR_CTRL_CKSEL_EXT_CLK;
break;
}
/* whatever period the user picked, the timestamp will advance in '1' every time
* the period passed. */
tmrCtrl |= ((1 << TMR_CTRL_TCLK_PERIOD_SHIFT) & TMR_CTRL_TCLK_PERIOD_MASK);
if (p_RtcDriverParam->invertInputClkPhase)
tmrCtrl |= TMR_CTRL_CIPH;
if (p_RtcDriverParam->invertOutputClkPhase)
tmrCtrl |= TMR_CTRL_COPH;
for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++)
{
if (p_RtcDriverParam->alarmPolarity[i] == e_FM_RTC_ALARM_POLARITY_ACTIVE_LOW)
tmrCtrl |= (TMR_CTRL_ALMP1 >> i);
}
for (i=0; i < FM_RTC_NUM_OF_EXT_TRIGGERS; i++)
if (p_RtcDriverParam->triggerPolarity[i] == e_FM_RTC_TRIGGER_ON_FALLING_EDGE)
tmrCtrl |= (TMR_CTRL_ETEP1 << i);
if (!p_RtcDriverParam->timerSlaveMode && p_Rtc->p_RtcDriverParam->bypass)
tmrCtrl |= TMR_CTRL_BYP;
WRITE_UINT32(p_MemMap->tmr_ctrl, tmrCtrl);
for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++)
{
/* Clear TMR_ALARM registers */
WRITE_UINT32(p_MemMap->tmr_alarm[i].tmr_alarm_l, 0xFFFFFFFF);
WRITE_UINT32(p_MemMap->tmr_alarm[i].tmr_alarm_h, 0xFFFFFFFF);
}
/* Clear TMR_TEVENT */
WRITE_UINT32(p_MemMap->tmr_tevent, TMR_TEVENT_ALL);
/* Initialize TMR_TEMASK */
WRITE_UINT32(p_MemMap->tmr_temask, 0);
/* TODO check that no timestamping MACs are working in this stage. */
/* find source clock frequency in Mhz */
if (p_Rtc->p_RtcDriverParam->srcClk != e_FM_RTC_SOURCE_CLOCK_SYSTEM)
p_Rtc->srcClkFreqMhz = p_Rtc->p_RtcDriverParam->extSrcClkFreq;
if (p_Rtc->p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_SYSTEM)
p_Rtc->srcClkFreqMhz = p_Rtc->p_RtcDriverParam->ext_src_clk_freq;
else
p_Rtc->srcClkFreqMhz = (uint32_t)(FmGetClockFreq(p_Rtc->h_Fm)/2);
p_Rtc->srcClkFreqMhz = (uint32_t)(FmGetMacClockFreq(p_Rtc->h_Fm));
/* if timer in Master mode Initialize TMR_CTRL */
/* We want the counter (TMR_CNT) to count in nano-seconds */
if (!p_RtcDriverParam->timerSlaveMode && p_Rtc->p_RtcDriverParam->bypass)
{
if (!p_RtcDriverParam->timer_slave_mode && p_Rtc->p_RtcDriverParam->bypass)
p_Rtc->clockPeriodNanoSec = (1000 / p_Rtc->srcClkFreqMhz);
}
else
{
/* Initialize TMR_ADD with the initial frequency compensation value:
freqCompensation = (2^32 / frequency ratio) */
/* frequency ratio = sorce clock/rtc clock =
* (p_Rtc->srcClkFreqMhz*1000000))/ 1/(p_Rtc->clockPeriodNanoSec * 1000000000) */
init_freq_comp = TRUE;
freqCompensation = (uint32_t)DIV_CEIL(ACCUMULATOR_OVERFLOW * 1000,
p_Rtc->clockPeriodNanoSec * p_Rtc->srcClkFreqMhz);
WRITE_UINT32(p_MemMap->tmr_add, freqCompensation);
p_Rtc->clockPeriodNanoSec * p_Rtc->srcClkFreqMhz);
}
/* check the legality of the relation between source and destination clocks */
/* should be larger than 1.0001 */
tmpDouble = 10000 * (uint64_t)p_Rtc->clockPeriodNanoSec * (uint64_t)p_Rtc->srcClkFreqMhz;
if((tmpDouble) <= 10001)
if ((tmpDouble) <= 10001)
RETURN_ERROR(MAJOR, E_CONFLICT,
("Invalid relation between source and destination clocks. Should be larger than 1.0001"));
for (i=0; i < 2; i++)
/* Clear TMR_FIPER registers */
WRITE_UINT32(p_MemMap->tmr_fiper[i], 0xFFFFFFFF);
/* Initialize TMR_PRSC */
WRITE_UINT32(p_MemMap->tmr_prsc, p_Rtc->outputClockDivisor);
/* Clear TMR_OFF */
WRITE_UINT32(p_MemMap->tmr_off_l, 0);
WRITE_UINT32(p_MemMap->tmr_off_h, 0);
fman_rtc_init(p_RtcDriverParam,
p_MemMap,
FM_RTC_NUM_OF_ALARMS,
FM_RTC_NUM_OF_PERIODIC_PULSES,
FM_RTC_NUM_OF_EXT_TRIGGERS,
init_freq_comp,
freqCompensation,
p_Rtc->outputClockDivisor);
/* Register the FM RTC interrupt */
FmRegisterIntr(p_Rtc->h_Fm, e_FM_MOD_TMR, 0, e_FM_INTR_TYPE_NORMAL, RtcExceptions , p_Rtc);
@ -381,9 +287,9 @@ t_Error FM_RTC_ConfigSourceClock(t_Handle h_FmRtc,
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->srcClk = srcClk;
if(srcClk != e_FM_RTC_SOURCE_CLOCK_SYSTEM)
p_Rtc->p_RtcDriverParam->extSrcClkFreq = freqInMhz;
p_Rtc->p_RtcDriverParam->src_clk = (enum fman_src_clock)srcClk;
if (srcClk != e_FM_RTC_SOURCE_CLOCK_SYSTEM)
p_Rtc->p_RtcDriverParam->ext_src_clk_freq = freqInMhz;
return E_OK;
}
@ -422,7 +328,7 @@ t_Error FM_RTC_ConfigInvertedInputClockPhase(t_Handle h_FmRtc, bool inverted)
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->invertInputClkPhase = inverted;
p_Rtc->p_RtcDriverParam->invert_input_clk_phase = inverted;
return E_OK;
}
@ -435,7 +341,7 @@ t_Error FM_RTC_ConfigInvertedOutputClockPhase(t_Handle h_FmRtc, bool inverted)
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->invertOutputClkPhase = inverted;
p_Rtc->p_RtcDriverParam->invert_output_clk_phase = inverted;
return E_OK;
}
@ -461,7 +367,7 @@ t_Error FM_RTC_ConfigPulseRealignment(t_Handle h_FmRtc, bool enable)
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->pulseRealign = enable;
p_Rtc->p_RtcDriverParam->pulse_realign = enable;
return E_OK;
}
@ -477,11 +383,10 @@ t_Error FM_RTC_ConfigAlarmPolarity(t_Handle h_FmRtc,
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (alarmId >= FM_RTC_NUM_OF_ALARMS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm ID"));
}
p_Rtc->p_RtcDriverParam->alarmPolarity[alarmId] = alarmPolarity;
p_Rtc->p_RtcDriverParam->alarm_polarity[alarmId] =
(enum fman_rtc_alarm_polarity)alarmPolarity;
return E_OK;
}
@ -501,7 +406,8 @@ t_Error FM_RTC_ConfigExternalTriggerPolarity(t_Handle h_FmRtc,
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External trigger ID"));
}
p_Rtc->p_RtcDriverParam->triggerPolarity[triggerId] = triggerPolarity;
p_Rtc->p_RtcDriverParam->trigger_polarity[triggerId] =
(enum fman_rtc_trigger_polarity)triggerPolarity;
return E_OK;
}
@ -510,27 +416,11 @@ t_Error FM_RTC_ConfigExternalTriggerPolarity(t_Handle h_FmRtc,
t_Error FM_RTC_Enable(t_Handle h_FmRtc, bool resetClock)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmrCtrl;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
tmrCtrl = GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl);
/* TODO A check must be added here, that no timestamping MAC's
* are working in this stage. */
if (resetClock)
{
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, (tmrCtrl | TMR_CTRL_TMSR));
XX_UDelay(10);
/* Clear TMR_OFF */
WRITE_UINT32(p_Rtc->p_MemMap->tmr_off_l, 0);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_off_h, 0);
}
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, (tmrCtrl | TMR_CTRL_TE));
fman_rtc_enable(p_Rtc->p_MemMap, resetClock);
return E_OK;
}
@ -538,15 +428,13 @@ t_Error FM_RTC_Enable(t_Handle h_FmRtc, bool resetClock)
t_Error FM_RTC_Disable(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmrCtrl;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* TODO A check must be added here, that no timestamping MAC's
* are working in this stage. */
tmrCtrl = GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, (tmrCtrl & ~(TMR_CTRL_TE)));
fman_rtc_disable(p_Rtc->p_MemMap);
return E_OK;
}
@ -559,10 +447,7 @@ t_Error FM_RTC_SetClockOffset(t_Handle h_FmRtc, int64_t offset)
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* TMR_OFF_L must be written first */
WRITE_UINT32(p_Rtc->p_MemMap->tmr_off_l, (uint32_t)offset);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_off_h, (uint32_t)(offset >> 32));
fman_rtc_set_timer_offset(p_Rtc->p_MemMap, offset);
return E_OK;
}
@ -570,43 +455,36 @@ t_Error FM_RTC_SetClockOffset(t_Handle h_FmRtc, int64_t offset)
t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc, t_FmRtcAlarmParams *p_FmRtcAlarmParams)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcMemMap *p_MemMap;
uint32_t tmpReg;
uint64_t tmpAlarm;
bool enable = FALSE;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_MemMap = p_Rtc->p_MemMap;
if (p_FmRtcAlarmParams->alarmId >= FM_RTC_NUM_OF_ALARMS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm ID"));
}
if(p_FmRtcAlarmParams->alarmTime < p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm time must be equal or larger than RTC period - %d nanoseconds", p_Rtc->clockPeriodNanoSec));
if(p_FmRtcAlarmParams->alarmTime % (uint64_t)p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm time must be a multiple of RTC period - %d nanoseconds", p_Rtc->clockPeriodNanoSec));
tmpAlarm = p_FmRtcAlarmParams->alarmTime/(uint64_t)p_Rtc->clockPeriodNanoSec;
/* TMR_ALARM_L must be written first */
WRITE_UINT32(p_MemMap->tmr_alarm[p_FmRtcAlarmParams->alarmId].tmr_alarm_l, (uint32_t)tmpAlarm);
WRITE_UINT32(p_MemMap->tmr_alarm[p_FmRtcAlarmParams->alarmId].tmr_alarm_h,
(uint32_t)(tmpAlarm >> 32));
if (p_FmRtcAlarmParams->alarmTime < p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Alarm time must be equal or larger than RTC period - %d nanoseconds",
p_Rtc->clockPeriodNanoSec));
tmpAlarm = p_FmRtcAlarmParams->alarmTime;
if (do_div(tmpAlarm, p_Rtc->clockPeriodNanoSec))
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Alarm time must be a multiple of RTC period - %d nanoseconds",
p_Rtc->clockPeriodNanoSec));
if (p_FmRtcAlarmParams->f_AlarmCallback)
{
p_Rtc->alarmParams[p_FmRtcAlarmParams->alarmId].f_AlarmCallback = p_FmRtcAlarmParams->f_AlarmCallback;
p_Rtc->alarmParams[p_FmRtcAlarmParams->alarmId].clearOnExpiration = p_FmRtcAlarmParams->clearOnExpiration;
if(p_FmRtcAlarmParams->alarmId == 0)
tmpReg = TMR_TEVENT_ALM1;
else
tmpReg = TMR_TEVENT_ALM2;
WRITE_UINT32(p_MemMap->tmr_temask, GET_UINT32(p_MemMap->tmr_temask) | tmpReg);
enable = TRUE;
}
fman_rtc_set_alarm(p_Rtc->p_MemMap, p_FmRtcAlarmParams->alarmId, (unsigned long)tmpAlarm, enable);
return E_OK;
}
@ -614,43 +492,39 @@ t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc, t_FmRtcAlarmParams *p_FmRtcAlarmParams
t_Error FM_RTC_SetPeriodicPulse(t_Handle h_FmRtc, t_FmRtcPeriodicPulseParams *p_FmRtcPeriodicPulseParams)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcMemMap *p_MemMap;
uint32_t tmpReg;
bool enable = FALSE;
uint64_t tmpFiper;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_MemMap = p_Rtc->p_MemMap;
if (p_FmRtcPeriodicPulseParams->periodicPulseId >= FM_RTC_NUM_OF_PERIODIC_PULSES)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse ID"));
}
if(GET_UINT32(p_MemMap->tmr_ctrl) & TMR_CTRL_TE)
if (fman_rtc_is_enabled(p_Rtc->p_MemMap))
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Can't set Periodic pulse when RTC is enabled."));
if(p_FmRtcPeriodicPulseParams->periodicPulsePeriod < p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse must be equal or larger than RTC period - %d nanoseconds", p_Rtc->clockPeriodNanoSec));
if(p_FmRtcPeriodicPulseParams->periodicPulsePeriod % (uint64_t)p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse must be a multiple of RTC period - %d nanoseconds", p_Rtc->clockPeriodNanoSec));
tmpFiper = p_FmRtcPeriodicPulseParams->periodicPulsePeriod/(uint64_t)p_Rtc->clockPeriodNanoSec;
if(tmpFiper & 0xffffffff00000000LL)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse/RTC Period must be smaller than 4294967296", p_Rtc->clockPeriodNanoSec));
WRITE_UINT32(p_MemMap->tmr_fiper[p_FmRtcPeriodicPulseParams->periodicPulseId], (uint32_t)tmpFiper);
if (p_FmRtcPeriodicPulseParams->periodicPulsePeriod < p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Periodic pulse must be equal or larger than RTC period - %d nanoseconds",
p_Rtc->clockPeriodNanoSec));
tmpFiper = p_FmRtcPeriodicPulseParams->periodicPulsePeriod;
if (do_div(tmpFiper, p_Rtc->clockPeriodNanoSec))
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Periodic pulse must be a multiple of RTC period - %d nanoseconds",
p_Rtc->clockPeriodNanoSec));
if (tmpFiper & 0xffffffff00000000LL)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Periodic pulse/RTC Period must be smaller than 4294967296",
p_Rtc->clockPeriodNanoSec));
if (p_FmRtcPeriodicPulseParams->f_PeriodicPulseCallback)
{
p_Rtc->periodicPulseParams[p_FmRtcPeriodicPulseParams->periodicPulseId].f_PeriodicPulseCallback =
p_FmRtcPeriodicPulseParams->f_PeriodicPulseCallback;
if(p_FmRtcPeriodicPulseParams->periodicPulseId == 0)
tmpReg = TMR_TEVENT_PP1;
else
tmpReg = TMR_TEVENT_PP2;
WRITE_UINT32(p_MemMap->tmr_temask, GET_UINT32(p_MemMap->tmr_temask) | tmpReg);
p_FmRtcPeriodicPulseParams->f_PeriodicPulseCallback;
enable = TRUE;
}
fman_rtc_set_periodic_pulse(p_Rtc->p_MemMap, p_FmRtcPeriodicPulseParams->periodicPulseId, (uint32_t)tmpFiper, enable);
return E_OK;
}
@ -658,7 +532,6 @@ t_Error FM_RTC_SetPeriodicPulse(t_Handle h_FmRtc, t_FmRtcPeriodicPulseParams *p_
t_Error FM_RTC_ClearPeriodicPulse(t_Handle h_FmRtc, uint8_t periodicPulseId)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmpReg;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
@ -669,17 +542,7 @@ t_Error FM_RTC_ClearPeriodicPulse(t_Handle h_FmRtc, uint8_t periodicPulseId)
}
p_Rtc->periodicPulseParams[periodicPulseId].f_PeriodicPulseCallback = NULL;
if(periodicPulseId == 0)
tmpReg = TMR_TEVENT_PP1;
else
tmpReg = TMR_TEVENT_PP2;
WRITE_UINT32(p_Rtc->p_MemMap->tmr_temask, GET_UINT32(p_Rtc->p_MemMap->tmr_temask) & ~tmpReg);
if (GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) & TMR_CTRL_FS)
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) & ~TMR_CTRL_FS);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_fiper[periodicPulseId], 0xFFFFFFFF);
fman_rtc_clear_periodic_pulse(p_Rtc->p_MemMap, periodicPulseId);
return E_OK;
}
@ -688,7 +551,7 @@ t_Error FM_RTC_ClearPeriodicPulse(t_Handle h_FmRtc, uint8_t periodicPulseId)
t_Error FM_RTC_SetExternalTrigger(t_Handle h_FmRtc, t_FmRtcExternalTriggerParams *p_FmRtcExternalTriggerParams)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmpReg;
bool enable = FALSE;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
@ -701,22 +564,10 @@ t_Error FM_RTC_SetExternalTrigger(t_Handle h_FmRtc, t_FmRtcExternalTriggerParams
if (p_FmRtcExternalTriggerParams->f_ExternalTriggerCallback)
{
p_Rtc->externalTriggerParams[p_FmRtcExternalTriggerParams->externalTriggerId].f_ExternalTriggerCallback = p_FmRtcExternalTriggerParams->f_ExternalTriggerCallback;
if(p_FmRtcExternalTriggerParams->externalTriggerId == 0)
tmpReg = TMR_TEVENT_ETS1;
else
tmpReg = TMR_TEVENT_ETS2;
WRITE_UINT32(p_Rtc->p_MemMap->tmr_temask, GET_UINT32(p_Rtc->p_MemMap->tmr_temask) | tmpReg);
}
if(p_FmRtcExternalTriggerParams->usePulseAsInput)
{
if(p_FmRtcExternalTriggerParams->externalTriggerId == 0)
tmpReg = TMR_CTRL_PP1L;
else
tmpReg = TMR_CTRL_PP2L;
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) | tmpReg);
enable = TRUE;
}
fman_rtc_set_ext_trigger(p_Rtc->p_MemMap, p_FmRtcExternalTriggerParams->externalTriggerId, enable, p_FmRtcExternalTriggerParams->usePulseAsInput);
return E_OK;
}
@ -724,7 +575,6 @@ t_Error FM_RTC_SetExternalTrigger(t_Handle h_FmRtc, t_FmRtcExternalTriggerParams
t_Error FM_RTC_ClearExternalTrigger(t_Handle h_FmRtc, uint8_t externalTriggerId)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmpReg;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
@ -734,19 +584,7 @@ t_Error FM_RTC_ClearExternalTrigger(t_Handle h_FmRtc, uint8_t externalTriggerId)
p_Rtc->externalTriggerParams[externalTriggerId].f_ExternalTriggerCallback = NULL;
if(externalTriggerId == 0)
tmpReg = TMR_TEVENT_ETS1;
else
tmpReg = TMR_TEVENT_ETS2;
WRITE_UINT32(p_Rtc->p_MemMap->tmr_temask, GET_UINT32(p_Rtc->p_MemMap->tmr_temask) & ~tmpReg);
if(externalTriggerId == 0)
tmpReg = TMR_CTRL_PP1L;
else
tmpReg = TMR_CTRL_PP2L;
if (GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) & tmpReg)
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) & ~tmpReg);
fman_rtc_clear_external_trigger(p_Rtc->p_MemMap, externalTriggerId);
return E_OK;
}
@ -757,21 +595,14 @@ t_Error FM_RTC_GetExternalTriggerTimeStamp(t_Handle h_FmRtc,
uint64_t *p_TimeStamp)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint64_t timeStamp;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (triggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External trigger ID"));
}
timeStamp = (uint64_t)GET_UINT32(p_Rtc->p_MemMap->tmr_etts[triggerId].tmr_etts_l);
timeStamp |= ((uint64_t)GET_UINT32(p_Rtc->p_MemMap->tmr_etts[triggerId].tmr_etts_h) << 32);
timeStamp = timeStamp*p_Rtc->clockPeriodNanoSec;
*p_TimeStamp = timeStamp;
*p_TimeStamp = fman_rtc_get_trigger_stamp(p_Rtc->p_MemMap, triggerId)*p_Rtc->clockPeriodNanoSec;
return E_OK;
}
@ -780,18 +611,11 @@ t_Error FM_RTC_GetExternalTriggerTimeStamp(t_Handle h_FmRtc,
t_Error FM_RTC_GetCurrentTime(t_Handle h_FmRtc, uint64_t *p_Ts)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint64_t time;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* TMR_CNT_L must be read first to get an accurate value */
time = (uint64_t)GET_UINT32(p_Rtc->p_MemMap->tmr_cnt_l);
time |= ((uint64_t)GET_UINT32(p_Rtc->p_MemMap->tmr_cnt_h) << 32);
time = time*p_Rtc->clockPeriodNanoSec;
*p_Ts = time;
*p_Ts = fman_rtc_get_timer(p_Rtc->p_MemMap)*p_Rtc->clockPeriodNanoSec;
return E_OK;
}
@ -804,10 +628,8 @@ t_Error FM_RTC_SetCurrentTime(t_Handle h_FmRtc, uint64_t ts)
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
ts = ts/p_Rtc->clockPeriodNanoSec;
/* TMR_CNT_L must be written first to get an accurate value */
WRITE_UINT32(p_Rtc->p_MemMap->tmr_cnt_l, (uint32_t)ts);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_cnt_h, (uint32_t)(ts >> 32));
do_div(ts, p_Rtc->clockPeriodNanoSec);
fman_rtc_set_timer(p_Rtc->p_MemMap, (int64_t)ts);
return E_OK;
}
@ -820,9 +642,7 @@ t_Error FM_RTC_GetFreqCompensation(t_Handle h_FmRtc, uint32_t *p_Compensation)
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
*p_Compensation = (uint32_t)
DIV_CEIL(ACCUMULATOR_OVERFLOW * 1000,
p_Rtc->clockPeriodNanoSec * p_Rtc->srcClkFreqMhz);
*p_Compensation = fman_rtc_get_frequency_compensation(p_Rtc->p_MemMap);
return E_OK;
}
@ -836,56 +656,37 @@ t_Error FM_RTC_SetFreqCompensation(t_Handle h_FmRtc, uint32_t freqCompensation)
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* set the new freqCompensation */
WRITE_UINT32(p_Rtc->p_MemMap->tmr_add, freqCompensation);
fman_rtc_set_frequency_compensation(p_Rtc->p_MemMap, freqCompensation);
return E_OK;
}
#ifdef CONFIG_PTP_1588_CLOCK_DPAA
/*****************************************************************************/
t_Error FM_RTC_EnableInterrupt(t_Handle h_FmRtc, uint32_t events)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* enable interrupt */
fman_rtc_enable_interupt(p_Rtc->p_MemMap, events);
return E_OK;
}
/*****************************************************************************/
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
t_Error FM_RTC_DumpRegs(t_Handle h_FmRtc)
t_Error FM_RTC_DisableInterrupt(t_Handle h_FmRtc, uint32_t events)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcMemMap *p_MemMap = p_Rtc->p_MemMap;
int i = 0;
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
DECLARE_DUMP;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (p_MemMap)
{
/* disable interrupt */
fman_rtc_disable_interupt(p_Rtc->p_MemMap, events);
DUMP_TITLE(p_MemMap, ("RTC:"));
DUMP_VAR(p_MemMap, tmr_id);
DUMP_VAR(p_MemMap, tmr_id2);
DUMP_VAR(p_MemMap, tmr_ctrl);
DUMP_VAR(p_MemMap, tmr_tevent);
DUMP_VAR(p_MemMap, tmr_temask);
DUMP_VAR(p_MemMap, tmr_cnt_h);
DUMP_VAR(p_MemMap, tmr_cnt_l);
DUMP_VAR(p_MemMap, tmr_ctrl);
DUMP_VAR(p_MemMap, tmr_add);
DUMP_VAR(p_MemMap, tmr_acc);
DUMP_VAR(p_MemMap, tmr_prsc);
DUMP_VAR(p_MemMap, tmr_off_h);
DUMP_VAR(p_MemMap, tmr_off_l);
DUMP_SUBSTRUCT_ARRAY(i, 2)
{
DUMP_VAR(p_MemMap, tmr_alarm[i].tmr_alarm_h);
DUMP_VAR(p_MemMap, tmr_alarm[i].tmr_alarm_l);
}
DUMP_SUBSTRUCT_ARRAY(i, 2)
{
DUMP_VAR(p_MemMap, tmr_fiper[i]);
DUMP_VAR(p_MemMap, tmr_fiper[i]);
}
DUMP_SUBSTRUCT_ARRAY(i, 2)
{
DUMP_VAR(p_MemMap, tmr_etts[i].tmr_etts_l);
DUMP_VAR(p_MemMap, tmr_etts[i].tmr_etts_l);
}
}
return E_OK;
return E_OK;
}
#endif /* (defined(DEBUG_ERRORS) && ... */
#endif

137
sys/contrib/ncsw/Peripherals/FM/Rtc/fm_rtc.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_rtc.h
@ -49,134 +50,12 @@
/* General definitions */
#define NANOSEC_PER_ONE_HZ_TICK 1000000000
#define MIN_RTC_CLK_FREQ_HZ 1000
#define MHz 1000000
#define ACCUMULATOR_OVERFLOW ((uint64_t)(1LL << 32))
/* RTC default values */
#define DEFAULT_srcClock e_FM_RTC_SOURCE_CLOCK_SYSTEM
#define DEFAULT_bypass FALSE
#define DEFAULT_invertInputClkPhase FALSE
#define DEFAULT_invertOutputClkPhase FALSE
#define DEFAULT_outputClockDivisor 0x00000002
#define DEFAULT_alarmPolarity e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH
#define DEFAULT_triggerPolarity e_FM_RTC_TRIGGER_ON_FALLING_EDGE
#define DEFAULT_pulseRealign FALSE
#define DEFAULT_clockPeriod 1000
/* FM RTC Registers definitions */
#define TMR_CTRL_ALMP1 0x80000000
#define TMR_CTRL_ALMP2 0x40000000
#define TMR_CTRL_FS 0x10000000
#define TMR_CTRL_PP1L 0x08000000
#define TMR_CTRL_PP2L 0x04000000
#define TMR_CTRL_TCLK_PERIOD_MASK 0x03FF0000
#define TMR_CTRL_FRD 0x00004000
#define TMR_CTRL_SLV 0x00002000
#define TMR_CTRL_ETEP1 0x00000100
#define TMR_CTRL_COPH 0x00000080
#define TMR_CTRL_CIPH 0x00000040
#define TMR_CTRL_TMSR 0x00000020
#define TMR_CTRL_DBG 0x00000010
#define TMR_CTRL_BYP 0x00000008
#define TMR_CTRL_TE 0x00000004
#define TMR_CTRL_CKSEL_OSC_CLK 0x00000003
#define TMR_CTRL_CKSEL_MAC_CLK 0x00000001
#define TMR_CTRL_CKSEL_EXT_CLK 0x00000000
#define TMR_CTRL_TCLK_PERIOD_SHIFT 16
#define TMR_TEVENT_ETS2 0x02000000
#define TMR_TEVENT_ETS1 0x01000000
#define TMR_TEVENT_ALM2 0x00020000
#define TMR_TEVENT_ALM1 0x00010000
#define TMR_TEVENT_PP1 0x00000080
#define TMR_TEVENT_PP2 0x00000040
#define TMR_TEVENT_PP3 0x00000020
#define TMR_TEVENT_ALL (TMR_TEVENT_ETS2 | TMR_TEVENT_ETS1 | \
TMR_TEVENT_ALM2 | TMR_TEVENT_ALM1 | \
TMR_TEVENT_PP1 | TMR_TEVENT_PP2 | TMR_TEVENT_PP3)
#define TMR_PRSC_OCK_MASK 0x0000FFFF
#define DEFAULT_OUTPUT_CLOCK_DIVISOR 0x00000002
#define DEFAULT_BYPASS FALSE
#define DEFAULT_CLOCK_PERIOD 1000
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/**************************************************************************//**
@Description FM RTC timer alarm
*//***************************************************************************/
typedef _Packed struct t_TmrAlaram
{
volatile uint32_t tmr_alarm_h; /**< */
volatile uint32_t tmr_alarm_l; /**< */
} _PackedType t_TmrAlaram;
/**************************************************************************//**
@Description FM RTC timer Ex trigger
*//***************************************************************************/
typedef _Packed struct t_TmrExtTrigger
{
volatile uint32_t tmr_etts_h; /**< */
volatile uint32_t tmr_etts_l; /**< */
} _PackedType t_TmrExtTrigger;
typedef _Packed struct
{
volatile uint32_t tmr_id; /* Module ID and version register */
volatile uint32_t tmr_id2; /* Module ID and configuration register */
volatile uint32_t PTP_RESERVED1[30];
volatile uint32_t tmr_ctrl; /* timer control register */
volatile uint32_t tmr_tevent; /* timer event register */
volatile uint32_t tmr_temask; /* timer event mask register */
volatile uint32_t PTP_RESERVED2[3];
volatile uint32_t tmr_cnt_h; /* timer counter high register */
volatile uint32_t tmr_cnt_l; /* timer counter low register */
volatile uint32_t tmr_add; /* timer drift compensation addend register */
volatile uint32_t tmr_acc; /* timer accumulator register */
volatile uint32_t tmr_prsc; /* timer prescale */
volatile uint32_t PTP_RESERVED3;
volatile uint32_t tmr_off_h; /* timer offset high */
volatile uint32_t tmr_off_l; /* timer offset low */
volatile t_TmrAlaram tmr_alarm[FM_RTC_NUM_OF_ALARMS]; /* timer alarm */
volatile uint32_t PTP_RESERVED4[2];
volatile uint32_t tmr_fiper[FM_RTC_NUM_OF_PERIODIC_PULSES]; /* timer fixed period interval */
volatile uint32_t PTP_RESERVED5[2];
volatile t_TmrExtTrigger tmr_etts[FM_RTC_NUM_OF_EXT_TRIGGERS]; /*time stamp general purpose external */
volatile uint32_t PTP_RESERVED6[3];
} _PackedType t_FmRtcMemMap;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description RTC FM driver parameters structure.
*//***************************************************************************/
typedef struct t_FmRtcDriverParam
{
t_Handle h_Fm; /**< */
e_FmSrcClk srcClk; /**< */
uint32_t extSrcClkFreq; /**< */
uint32_t rtcFreqHz; /**< */
bool timerSlaveMode; /*Slave/Master Mode*/
bool invertInputClkPhase;
bool invertOutputClkPhase;
uint32_t eventsMask;
bool bypass; /**< Indicates if frequency compensation is bypassed */
bool pulseRealign;
e_FmRtcAlarmPolarity alarmPolarity[FM_RTC_NUM_OF_ALARMS];
e_FmRtcTriggerPolarity triggerPolarity[FM_RTC_NUM_OF_EXT_TRIGGERS];
} t_FmRtcDriverParam;
typedef struct t_FmRtcAlarm
{
@ -203,14 +82,14 @@ typedef struct t_FmRtc
t_Part *p_Part; /**< Pointer to the integration device */
t_Handle h_Fm;
t_Handle h_App; /**< Application handle */
t_FmRtcMemMap *p_MemMap; /**< Pointer to RTC memory map */
struct rtc_regs *p_MemMap;
uint32_t clockPeriodNanoSec; /**< RTC clock period in nano-seconds (for FS mode) */
uint32_t srcClkFreqMhz;
uint16_t outputClockDivisor; /**< Output clock divisor (for FS mode) */
t_FmRtcAlarm alarmParams[FM_RTC_NUM_OF_ALARMS];
t_FmRtcPeriodicPulse periodicPulseParams[FM_RTC_NUM_OF_PERIODIC_PULSES];
t_FmRtcExternalTrigger externalTriggerParams[FM_RTC_NUM_OF_EXT_TRIGGERS];
t_FmRtcDriverParam *p_RtcDriverParam; /**< RTC Driver parameters (for Init phase) */
struct rtc_cfg *p_RtcDriverParam; /**< RTC Driver parameters (for Init phase) */
} t_FmRtc;

334
sys/contrib/ncsw/Peripherals/FM/Rtc/fman_rtc.c Executable file
View File

@ -0,0 +1,334 @@
/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_rtc.h"
void fman_rtc_defconfig(struct rtc_cfg *cfg)
{
int i;
cfg->src_clk = DEFAULT_SRC_CLOCK;
cfg->invert_input_clk_phase = DEFAULT_INVERT_INPUT_CLK_PHASE;
cfg->invert_output_clk_phase = DEFAULT_INVERT_OUTPUT_CLK_PHASE;
cfg->pulse_realign = DEFAULT_PULSE_REALIGN;
for (i = 0; i < FMAN_RTC_MAX_NUM_OF_ALARMS; i++)
cfg->alarm_polarity[i] = DEFAULT_ALARM_POLARITY;
for (i = 0; i < FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS; i++)
cfg->trigger_polarity[i] = DEFAULT_TRIGGER_POLARITY;
}
uint32_t fman_rtc_get_events(struct rtc_regs *regs)
{
return ioread32be(&regs->tmr_tevent);
}
uint32_t fman_rtc_get_event(struct rtc_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->tmr_tevent) & ev_mask;
}
uint32_t fman_rtc_get_interrupt_mask(struct rtc_regs *regs)
{
return ioread32be(&regs->tmr_temask);
}
void fman_rtc_set_interrupt_mask(struct rtc_regs *regs, uint32_t mask)
{
iowrite32be(mask, &regs->tmr_temask);
}
void fman_rtc_ack_event(struct rtc_regs *regs, uint32_t events)
{
iowrite32be(events, &regs->tmr_tevent);
}
uint32_t fman_rtc_check_and_clear_event(struct rtc_regs *regs)
{
uint32_t event;
event = ioread32be(&regs->tmr_tevent);
event &= ioread32be(&regs->tmr_temask);
if (event)
iowrite32be(event, &regs->tmr_tevent);
return event;
}
uint32_t fman_rtc_get_frequency_compensation(struct rtc_regs *regs)
{
return ioread32be(&regs->tmr_add);
}
void fman_rtc_set_frequency_compensation(struct rtc_regs *regs, uint32_t val)
{
iowrite32be(val, &regs->tmr_add);
}
void fman_rtc_enable_interupt(struct rtc_regs *regs, uint32_t events)
{
fman_rtc_set_interrupt_mask(regs, fman_rtc_get_interrupt_mask(regs) | events);
}
void fman_rtc_disable_interupt(struct rtc_regs *regs, uint32_t events)
{
fman_rtc_set_interrupt_mask(regs, fman_rtc_get_interrupt_mask(regs) & ~events);
}
void fman_rtc_set_timer_alarm_l(struct rtc_regs *regs, int index, uint32_t val)
{
iowrite32be(val, &regs->tmr_alarm[index].tmr_alarm_l);
}
void fman_rtc_set_timer_fiper(struct rtc_regs *regs, int index, uint32_t val)
{
iowrite32be(val, &regs->tmr_fiper[index]);
}
void fman_rtc_set_timer_alarm(struct rtc_regs *regs, int index, int64_t val)
{
iowrite32be((uint32_t)val, &regs->tmr_alarm[index].tmr_alarm_l);
iowrite32be((uint32_t)(val >> 32), &regs->tmr_alarm[index].tmr_alarm_h);
}
void fman_rtc_set_timer_offset(struct rtc_regs *regs, int64_t val)
{
iowrite32be((uint32_t)val, &regs->tmr_off_l);
iowrite32be((uint32_t)(val >> 32), &regs->tmr_off_h);
}
uint64_t fman_rtc_get_trigger_stamp(struct rtc_regs *regs, int id)
{
uint64_t time;
/* TMR_CNT_L must be read first to get an accurate value */
time = (uint64_t)ioread32be(&regs->tmr_etts[id].tmr_etts_l);
time |= ((uint64_t)ioread32be(&regs->tmr_etts[id].tmr_etts_h)
<< 32);
return time;
}
uint32_t fman_rtc_get_timer_ctrl(struct rtc_regs *regs)
{
return ioread32be(&regs->tmr_ctrl);
}
void fman_rtc_set_timer_ctrl(struct rtc_regs *regs, uint32_t val)
{
iowrite32be(val, &regs->tmr_ctrl);
}
void fman_rtc_timers_soft_reset(struct rtc_regs *regs)
{
fman_rtc_set_timer_ctrl(regs, FMAN_RTC_TMR_CTRL_TMSR);
DELAY(10);
fman_rtc_set_timer_ctrl(regs, 0);
}
void fman_rtc_init(struct rtc_cfg *cfg, struct rtc_regs *regs, int num_alarms,
int num_fipers, int num_ext_triggers, bool init_freq_comp,
uint32_t freq_compensation, uint32_t output_clock_divisor)
{
uint32_t tmr_ctrl;
int i;
fman_rtc_timers_soft_reset(regs);
/* Set the source clock */
switch (cfg->src_clk) {
case E_FMAN_RTC_SOURCE_CLOCK_SYSTEM:
tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_MAC_CLK;
break;
case E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR:
tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_OSC_CLK;
break;
default:
/* Use a clock from the External TMR reference clock.*/
tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_EXT_CLK;
break;
}
/* whatever period the user picked, the timestamp will advance in '1'
* every time the period passed. */
tmr_ctrl |= ((1 << FMAN_RTC_TMR_CTRL_TCLK_PERIOD_SHIFT) &
FMAN_RTC_TMR_CTRL_TCLK_PERIOD_MASK);
if (cfg->invert_input_clk_phase)
tmr_ctrl |= FMAN_RTC_TMR_CTRL_CIPH;
if (cfg->invert_output_clk_phase)
tmr_ctrl |= FMAN_RTC_TMR_CTRL_COPH;
for (i = 0; i < num_alarms; i++) {
if (cfg->alarm_polarity[i] ==
E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW)
tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ALMP1 >> i);
}
for (i = 0; i < num_ext_triggers; i++)
if (cfg->trigger_polarity[i] ==
E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE)
tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ETEP1 << i);
if (!cfg->timer_slave_mode && cfg->bypass)
tmr_ctrl |= FMAN_RTC_TMR_CTRL_BYP;
fman_rtc_set_timer_ctrl(regs, tmr_ctrl);
if (init_freq_comp)
fman_rtc_set_frequency_compensation(regs, freq_compensation);
/* Clear TMR_ALARM registers */
for (i = 0; i < num_alarms; i++)
fman_rtc_set_timer_alarm(regs, i, 0xFFFFFFFFFFFFFFFFLL);
/* Clear TMR_TEVENT */
fman_rtc_ack_event(regs, FMAN_RTC_TMR_TEVENT_ALL);
/* Initialize TMR_TEMASK */
fman_rtc_set_interrupt_mask(regs, 0);
/* Clear TMR_FIPER registers */
for (i = 0; i < num_fipers; i++)
fman_rtc_set_timer_fiper(regs, i, 0xFFFFFFFF);
/* Initialize TMR_PRSC */
iowrite32be(output_clock_divisor, &regs->tmr_prsc);
/* Clear TMR_OFF */
fman_rtc_set_timer_offset(regs, 0);
}
bool fman_rtc_is_enabled(struct rtc_regs *regs)
{
return (bool)(fman_rtc_get_timer_ctrl(regs) & FMAN_RTC_TMR_CTRL_TE);
}
void fman_rtc_enable(struct rtc_regs *regs, bool reset_clock)
{
uint32_t tmr_ctrl = fman_rtc_get_timer_ctrl(regs);
/* TODO check that no timestamping MACs are working in this stage. */
if (reset_clock) {
fman_rtc_set_timer_ctrl(regs, (tmr_ctrl | FMAN_RTC_TMR_CTRL_TMSR));
DELAY(10);
/* Clear TMR_OFF */
fman_rtc_set_timer_offset(regs, 0);
}
fman_rtc_set_timer_ctrl(regs, (tmr_ctrl | FMAN_RTC_TMR_CTRL_TE));
}
void fman_rtc_disable(struct rtc_regs *regs)
{
fman_rtc_set_timer_ctrl(regs, (fman_rtc_get_timer_ctrl(regs)
& ~(FMAN_RTC_TMR_CTRL_TE)));
}
void fman_rtc_clear_periodic_pulse(struct rtc_regs *regs, int id)
{
uint32_t tmp_reg;
if (id == 0)
tmp_reg = FMAN_RTC_TMR_TEVENT_PP1;
else
tmp_reg = FMAN_RTC_TMR_TEVENT_PP2;
fman_rtc_disable_interupt(regs, tmp_reg);
tmp_reg = fman_rtc_get_timer_ctrl(regs);
if (tmp_reg & FMAN_RTC_TMR_CTRL_FS)
fman_rtc_set_timer_ctrl(regs, tmp_reg & ~FMAN_RTC_TMR_CTRL_FS);
fman_rtc_set_timer_fiper(regs, id, 0xFFFFFFFF);
}
void fman_rtc_clear_external_trigger(struct rtc_regs *regs, int id)
{
uint32_t tmpReg, tmp_ctrl;
if (id == 0)
tmpReg = FMAN_RTC_TMR_TEVENT_ETS1;
else
tmpReg = FMAN_RTC_TMR_TEVENT_ETS2;
fman_rtc_disable_interupt(regs, tmpReg);
if (id == 0)
tmpReg = FMAN_RTC_TMR_CTRL_PP1L;
else
tmpReg = FMAN_RTC_TMR_CTRL_PP2L;
tmp_ctrl = fman_rtc_get_timer_ctrl(regs);
if (tmp_ctrl & tmpReg)
fman_rtc_set_timer_ctrl(regs, tmp_ctrl & ~tmpReg);
}
void fman_rtc_set_alarm(struct rtc_regs *regs, int id, uint32_t val, bool enable)
{
uint32_t tmpReg;
fman_rtc_set_timer_alarm(regs, id, val);
if (enable) {
if (id == 0)
tmpReg = FMAN_RTC_TMR_TEVENT_ALM1;
else
tmpReg = FMAN_RTC_TMR_TEVENT_ALM2;
fman_rtc_enable_interupt(regs, tmpReg);
}
}
void fman_rtc_set_periodic_pulse(struct rtc_regs *regs, int id, uint32_t val,
bool enable)
{
uint32_t tmpReg;
fman_rtc_set_timer_fiper(regs, id, val);
if (enable) {
if (id == 0)
tmpReg = FMAN_RTC_TMR_TEVENT_PP1;
else
tmpReg = FMAN_RTC_TMR_TEVENT_PP2;
fman_rtc_enable_interupt(regs, tmpReg);
}
}
void fman_rtc_set_ext_trigger(struct rtc_regs *regs, int id, bool enable,
bool use_pulse_as_input)
{
uint32_t tmpReg;
if (enable) {
if (id == 0)
tmpReg = FMAN_RTC_TMR_TEVENT_ETS1;
else
tmpReg = FMAN_RTC_TMR_TEVENT_ETS2;
fman_rtc_enable_interupt(regs, tmpReg);
}
if (use_pulse_as_input) {
if (id == 0)
tmpReg = FMAN_RTC_TMR_CTRL_PP1L;
else
tmpReg = FMAN_RTC_TMR_CTRL_PP2L;
fman_rtc_set_timer_ctrl(regs, fman_rtc_get_timer_ctrl(regs) | tmpReg);
}
}

757
sys/contrib/ncsw/Peripherals/FM/SP/fm_sp.c Normal file
View File

@ -0,0 +1,757 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_sp.c
@Description FM PCD Storage profile ...
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "string_ext.h"
#include "debug_ext.h"
#include "net_ext.h"
#include "fm_vsp_ext.h"
#include "fm_sp.h"
#include "fm_common.h"
#include "fsl_fman_sp.h"
#if (DPAA_VERSION >= 11)
static t_Error CheckParamsGeneratedInternally(t_FmVspEntry *p_FmVspEntry)
{
t_Error err = E_OK;
if ((err = FmSpCheckIntContextParams(&p_FmVspEntry->intContext))!= E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
if ((err = FmSpCheckBufMargins(&p_FmVspEntry->bufMargins)) != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
return err;
}
static t_Error CheckParams(t_FmVspEntry *p_FmVspEntry)
{
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->h_Fm, E_INVALID_HANDLE);
if ((err = FmSpCheckBufPoolsParams(&p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools,
p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools,
p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion)) != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
if (p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset & ~FM_LIODN_OFFSET_MASK)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("liodnOffset is larger than %d", FM_LIODN_OFFSET_MASK+1));
err = FmVSPCheckRelativeProfile(p_FmVspEntry->h_Fm,
p_FmVspEntry->portType,
p_FmVspEntry->portId,
p_FmVspEntry->relativeProfileId);
return err;
}
#endif /* (DPAA_VERSION >= 11) */
/*****************************************************************************/
/* Inter-module API routines */
/*****************************************************************************/
void FmSpSetBufPoolsInAscOrderOfBufSizes(t_FmExtPools *p_FmExtPools,
uint8_t *orderedArray,
uint16_t *sizesArray)
{
uint16_t bufSize = 0;
int i=0, j=0, k=0;
/* First we copy the external buffers pools information to an ordered local array */
for (i=0;i<p_FmExtPools->numOfPoolsUsed;i++)
{
/* get pool size */
bufSize = p_FmExtPools->extBufPool[i].size;
/* keep sizes in an array according to poolId for direct access */
sizesArray[p_FmExtPools->extBufPool[i].id] = bufSize;
/* save poolId in an ordered array according to size */
for (j=0;j<=i;j++)
{
/* this is the next free place in the array */
if (j==i)
orderedArray[i] = p_FmExtPools->extBufPool[i].id;
else
{
/* find the right place for this poolId */
if (bufSize < sizesArray[orderedArray[j]])
{
/* move the poolIds one place ahead to make room for this poolId */
for (k=i;k>j;k--)
orderedArray[k] = orderedArray[k-1];
/* now k==j, this is the place for the new size */
orderedArray[k] = p_FmExtPools->extBufPool[i].id;
break;
}
}
}
}
}
t_Error FmSpCheckBufPoolsParams(t_FmExtPools *p_FmExtPools,
t_FmBackupBmPools *p_FmBackupBmPools,
t_FmBufPoolDepletion *p_FmBufPoolDepletion)
{
int i = 0, j = 0;
bool found;
uint8_t count = 0;
if (p_FmExtPools)
{
if (p_FmExtPools->numOfPoolsUsed > FM_PORT_MAX_NUM_OF_EXT_POOLS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOfPoolsUsed can't be larger than %d", FM_PORT_MAX_NUM_OF_EXT_POOLS));
for (i=0;i<p_FmExtPools->numOfPoolsUsed;i++)
{
if (p_FmExtPools->extBufPool[i].id >= BM_MAX_NUM_OF_POOLS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("extBufPools.extBufPool[%d].id can't be larger than %d", i, BM_MAX_NUM_OF_POOLS));
if (!p_FmExtPools->extBufPool[i].size)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("extBufPools.extBufPool[%d].size is 0", i));
}
}
if (!p_FmExtPools && (p_FmBackupBmPools || p_FmBufPoolDepletion))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("backupBmPools ot bufPoolDepletion can not be defined without external pools"));
/* backup BM pools indication is valid only for some chip derivatives
(limited by the config routine) */
if (p_FmBackupBmPools)
{
if (p_FmBackupBmPools->numOfBackupPools >= p_FmExtPools->numOfPoolsUsed)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_BackupBmPools must be smaller than extBufPools.numOfPoolsUsed"));
found = FALSE;
for (i = 0;i<p_FmBackupBmPools->numOfBackupPools;i++)
{
for (j=0;j<p_FmExtPools->numOfPoolsUsed;j++)
{
if (p_FmBackupBmPools->poolIds[i] == p_FmExtPools->extBufPool[j].id)
{
found = TRUE;
break;
}
}
if (!found)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("All p_BackupBmPools.poolIds must be included in extBufPools.extBufPool[n].id"));
else
found = FALSE;
}
}
/* up to extBufPools.numOfPoolsUsed pools may be defined */
if (p_FmBufPoolDepletion && p_FmBufPoolDepletion->poolsGrpModeEnable)
{
if ((p_FmBufPoolDepletion->numOfPools > p_FmExtPools->numOfPoolsUsed))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufPoolDepletion.numOfPools can't be larger than %d and can't be larger than numOfPoolsUsed", FM_PORT_MAX_NUM_OF_EXT_POOLS));
if (!p_FmBufPoolDepletion->numOfPools)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufPoolDepletion.numOfPoolsToConsider can not be 0 when poolsGrpModeEnable=TRUE"));
found = FALSE;
count = 0;
/* for each pool that is in poolsToConsider, check if it is defined
in extBufPool */
for (i=0;i<BM_MAX_NUM_OF_POOLS;i++)
{
if (p_FmBufPoolDepletion->poolsToConsider[i])
{
for (j=0;j<p_FmExtPools->numOfPoolsUsed;j++)
{
if (i == p_FmExtPools->extBufPool[j].id)
{
found = TRUE;
count++;
break;
}
}
if (!found)
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Pools selected for depletion are not used."));
else
found = FALSE;
}
}
/* check that the number of pools that we have checked is equal to the number announced by the user */
if (count != p_FmBufPoolDepletion->numOfPools)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufPoolDepletion.numOfPools is larger than the number of pools defined."));
}
if (p_FmBufPoolDepletion && p_FmBufPoolDepletion->singlePoolModeEnable)
{
/* calculate vector for number of pools depletion */
found = FALSE;
count = 0;
for (i=0;i<BM_MAX_NUM_OF_POOLS;i++)
{
if (p_FmBufPoolDepletion->poolsToConsiderForSingleMode[i])
{
for (j=0;j<p_FmExtPools->numOfPoolsUsed;j++)
{
if (i == p_FmExtPools->extBufPool[j].id)
{
found = TRUE;
count++;
break;
}
}
if (!found)
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Pools selected for depletion are not used."));
else
found = FALSE;
}
}
if (!count)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("No pools defined for single buffer mode pool depletion."));
}
return E_OK;
}
t_Error FmSpCheckIntContextParams(t_FmSpIntContextDataCopy *p_FmSpIntContextDataCopy)
{
/* Check that divisible by 16 and not larger than 240 */
if (p_FmSpIntContextDataCopy->intContextOffset >MAX_INT_OFFSET)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.intContextOffset can't be larger than %d", MAX_INT_OFFSET));
if (p_FmSpIntContextDataCopy->intContextOffset % OFFSET_UNITS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.intContextOffset has to be divisible by %d", OFFSET_UNITS));
/* check that ic size+ic internal offset, does not exceed ic block size */
if (p_FmSpIntContextDataCopy->size + p_FmSpIntContextDataCopy->intContextOffset > MAX_IC_SIZE)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.size + intContext.intContextOffset has to be smaller than %d", MAX_IC_SIZE));
/* Check that divisible by 16 and not larger than 256 */
if (p_FmSpIntContextDataCopy->size % OFFSET_UNITS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.size has to be divisible by %d", OFFSET_UNITS));
/* Check that divisible by 16 and not larger than 4K */
if (p_FmSpIntContextDataCopy->extBufOffset > MAX_EXT_OFFSET)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.extBufOffset can't be larger than %d", MAX_EXT_OFFSET));
if (p_FmSpIntContextDataCopy->extBufOffset % OFFSET_UNITS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.extBufOffset has to be divisible by %d", OFFSET_UNITS));
return E_OK;
}
t_Error FmSpCheckBufMargins(t_FmSpBufMargins *p_FmSpBufMargins)
{
/* Check the margin definition */
if (p_FmSpBufMargins->startMargins > MAX_EXT_BUFFER_OFFSET)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufMargins.startMargins can't be larger than %d", MAX_EXT_BUFFER_OFFSET));
if (p_FmSpBufMargins->endMargins > MAX_EXT_BUFFER_OFFSET)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufMargins.endMargins can't be larger than %d", MAX_EXT_BUFFER_OFFSET));
return E_OK;
}
t_Error FmSpBuildBufferStructure(t_FmSpIntContextDataCopy *p_FmSpIntContextDataCopy,
t_FmBufferPrefixContent *p_BufferPrefixContent,
t_FmSpBufMargins *p_FmSpBufMargins,
t_FmSpBufferOffsets *p_FmSpBufferOffsets,
uint8_t *internalBufferOffset)
{
uint32_t tmp;
SANITY_CHECK_RETURN_ERROR(p_FmSpIntContextDataCopy, E_INVALID_VALUE);
ASSERT_COND(p_FmSpIntContextDataCopy);
ASSERT_COND(p_BufferPrefixContent);
ASSERT_COND(p_FmSpBufMargins);
ASSERT_COND(p_FmSpBufferOffsets);
/* Align start of internal context data to 16 byte */
p_FmSpIntContextDataCopy->extBufOffset =
(uint16_t)((p_BufferPrefixContent->privDataSize & (OFFSET_UNITS-1)) ?
((p_BufferPrefixContent->privDataSize + OFFSET_UNITS) & ~(uint16_t)(OFFSET_UNITS-1)) :
p_BufferPrefixContent->privDataSize);
/* Translate margin and intContext params to FM parameters */
/* Initialize with illegal value. Later we'll set legal values. */
p_FmSpBufferOffsets->prsResultOffset = (uint32_t)ILLEGAL_BASE;
p_FmSpBufferOffsets->timeStampOffset = (uint32_t)ILLEGAL_BASE;
p_FmSpBufferOffsets->hashResultOffset= (uint32_t)ILLEGAL_BASE;
p_FmSpBufferOffsets->pcdInfoOffset = (uint32_t)ILLEGAL_BASE;
/* Internally the driver supports 4 options
1. prsResult/timestamp/hashResult selection (in fact 8 options, but for simplicity we'll
relate to it as 1).
2. All IC context (from AD) not including debug.*/
/* This 'if' covers option 2. We copy from beginning of context. */
if (p_BufferPrefixContent->passAllOtherPCDInfo)
{
p_FmSpIntContextDataCopy->size = 128; /* must be aligned to 16 */
/* Start copying data after 16 bytes (FD) from the beginning of the internal context */
p_FmSpIntContextDataCopy->intContextOffset = 16;
if (p_BufferPrefixContent->passAllOtherPCDInfo)
p_FmSpBufferOffsets->pcdInfoOffset = p_FmSpIntContextDataCopy->extBufOffset;
if (p_BufferPrefixContent->passPrsResult)
p_FmSpBufferOffsets->prsResultOffset =
(uint32_t)(p_FmSpIntContextDataCopy->extBufOffset + 16);
if (p_BufferPrefixContent->passTimeStamp)
p_FmSpBufferOffsets->timeStampOffset =
(uint32_t)(p_FmSpIntContextDataCopy->extBufOffset + 48);
if (p_BufferPrefixContent->passHashResult)
p_FmSpBufferOffsets->hashResultOffset =
(uint32_t)(p_FmSpIntContextDataCopy->extBufOffset + 56);
}
else
{
/* This case covers the options under 1 */
/* Copy size must be in 16-byte granularity. */
p_FmSpIntContextDataCopy->size =
(uint16_t)((p_BufferPrefixContent->passPrsResult ? 32 : 0) +
((p_BufferPrefixContent->passTimeStamp ||
p_BufferPrefixContent->passHashResult) ? 16 : 0));
/* Align start of internal context data to 16 byte */
p_FmSpIntContextDataCopy->intContextOffset =
(uint8_t)(p_BufferPrefixContent->passPrsResult ? 32 :
((p_BufferPrefixContent->passTimeStamp ||
p_BufferPrefixContent->passHashResult) ? 64 : 0));
if (p_BufferPrefixContent->passPrsResult)
p_FmSpBufferOffsets->prsResultOffset = p_FmSpIntContextDataCopy->extBufOffset;
if (p_BufferPrefixContent->passTimeStamp)
p_FmSpBufferOffsets->timeStampOffset = p_BufferPrefixContent->passPrsResult ?
(p_FmSpIntContextDataCopy->extBufOffset + sizeof(t_FmPrsResult)) :
p_FmSpIntContextDataCopy->extBufOffset;
if (p_BufferPrefixContent->passHashResult)
/* If PR is not requested, whether TS is requested or not, IC will be copied from TS */
p_FmSpBufferOffsets->hashResultOffset = p_BufferPrefixContent->passPrsResult ?
(p_FmSpIntContextDataCopy->extBufOffset + sizeof(t_FmPrsResult) + 8) :
p_FmSpIntContextDataCopy->extBufOffset + 8;
}
if (p_FmSpIntContextDataCopy->size)
p_FmSpBufMargins->startMargins =
(uint16_t)(p_FmSpIntContextDataCopy->extBufOffset +
p_FmSpIntContextDataCopy->size);
else
/* No Internal Context passing, STartMargin is immediately after privateInfo */
p_FmSpBufMargins->startMargins = p_BufferPrefixContent->privDataSize;
/* save extra space for manip in both external and internal buffers */
if (p_BufferPrefixContent->manipExtraSpace)
{
uint8_t extraSpace;
#ifdef FM_CAPWAP_SUPPORT
if ((p_BufferPrefixContent->manipExtraSpace + CAPWAP_FRAG_EXTRA_SPACE) >= 256)
RETURN_ERROR(MAJOR, E_INVALID_VALUE,
("p_BufferPrefixContent->manipExtraSpace should be less than %d",
256-CAPWAP_FRAG_EXTRA_SPACE));
extraSpace = (uint8_t)(p_BufferPrefixContent->manipExtraSpace + CAPWAP_FRAG_EXTRA_SPACE);
#else
extraSpace = p_BufferPrefixContent->manipExtraSpace;
#endif /* FM_CAPWAP_SUPPORT */
p_FmSpBufferOffsets->manipOffset = p_FmSpBufMargins->startMargins;
p_FmSpBufMargins->startMargins += extraSpace;
*internalBufferOffset = extraSpace;
}
/* align data start */
tmp = (uint32_t)(p_FmSpBufMargins->startMargins % p_BufferPrefixContent->dataAlign);
if (tmp)
p_FmSpBufMargins->startMargins += (p_BufferPrefixContent->dataAlign-tmp);
p_FmSpBufferOffsets->dataOffset = p_FmSpBufMargins->startMargins;
return E_OK;
}
/*********************** End of inter-module routines ************************/
#if (DPAA_VERSION >= 11)
/*****************************************************************************/
/* API routines */
/*****************************************************************************/
t_Handle FM_VSP_Config(t_FmVspParams *p_FmVspParams)
{
t_FmVspEntry *p_FmVspEntry = NULL;
struct fm_storage_profile_params fm_vsp_params;
p_FmVspEntry = (t_FmVspEntry *)XX_Malloc(sizeof(t_FmVspEntry));
if (!p_FmVspEntry)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_StorageProfile allocation failed"));
return NULL;
}
memset(p_FmVspEntry, 0, sizeof(t_FmVspEntry));
p_FmVspEntry->p_FmVspEntryDriverParams = (t_FmVspEntryDriverParams *)XX_Malloc(sizeof(t_FmVspEntryDriverParams));
if (!p_FmVspEntry->p_FmVspEntryDriverParams)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_StorageProfile allocation failed"));
XX_Free(p_FmVspEntry);
return NULL;
}
memset(p_FmVspEntry->p_FmVspEntryDriverParams, 0, sizeof(t_FmVspEntryDriverParams));
fman_vsp_defconfig(&fm_vsp_params);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaHeaderCacheAttr = fm_vsp_params.header_cache_attr;
p_FmVspEntry->p_FmVspEntryDriverParams->dmaIntContextCacheAttr = fm_vsp_params.int_context_cache_attr;
p_FmVspEntry->p_FmVspEntryDriverParams->dmaScatterGatherCacheAttr = fm_vsp_params.scatter_gather_cache_attr;
p_FmVspEntry->p_FmVspEntryDriverParams->dmaSwapData = fm_vsp_params.dma_swap_data;
p_FmVspEntry->p_FmVspEntryDriverParams->dmaWriteOptimize = fm_vsp_params.dma_write_optimize;
p_FmVspEntry->p_FmVspEntryDriverParams->noScatherGather = fm_vsp_params.no_scather_gather;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.privDataSize = DEFAULT_FM_SP_bufferPrefixContent_privDataSize;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.passPrsResult= DEFAULT_FM_SP_bufferPrefixContent_passPrsResult;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.passTimeStamp= DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.passAllOtherPCDInfo
= DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.dataAlign = DEFAULT_FM_SP_bufferPrefixContent_dataAlign;
p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset = p_FmVspParams->liodnOffset;
memcpy(&p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools, &p_FmVspParams->extBufPools, sizeof(t_FmExtPools));
p_FmVspEntry->h_Fm = p_FmVspParams->h_Fm;
p_FmVspEntry->portType = p_FmVspParams->portParams.portType;
p_FmVspEntry->portId = p_FmVspParams->portParams.portId;
p_FmVspEntry->relativeProfileId = p_FmVspParams->relativeProfileId;
return p_FmVspEntry;
}
t_Error FM_VSP_Init(t_Handle h_FmVsp)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry *)h_FmVsp;
struct fm_storage_profile_params fm_vsp_params;
uint8_t orderedArray[FM_PORT_MAX_NUM_OF_EXT_POOLS];
uint16_t sizesArray[BM_MAX_NUM_OF_POOLS];
t_Error err;
uint16_t absoluteProfileId = 0;
int i = 0;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams,E_INVALID_HANDLE);
CHECK_INIT_PARAMETERS(p_FmVspEntry, CheckParams);
memset(&orderedArray, 0, sizeof(uint8_t) * FM_PORT_MAX_NUM_OF_EXT_POOLS);
memset(&sizesArray, 0, sizeof(uint16_t) * BM_MAX_NUM_OF_POOLS);
err = FmSpBuildBufferStructure(&p_FmVspEntry->intContext,
&p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent,
&p_FmVspEntry->bufMargins,
&p_FmVspEntry->bufferOffsets,
&p_FmVspEntry->internalBufferOffset);
if (err != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
err = CheckParamsGeneratedInternally(p_FmVspEntry);
if (err != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
p_FmVspEntry->p_FmSpRegsBase =
(struct fm_pcd_storage_profile_regs *)FmGetVSPBaseAddr(p_FmVspEntry->h_Fm);
if (!p_FmVspEntry->p_FmSpRegsBase)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("impossible to initialize SpRegsBase"));
/* order external buffer pools in ascending order of buffer pools sizes */
FmSpSetBufPoolsInAscOrderOfBufSizes(&(p_FmVspEntry->p_FmVspEntryDriverParams)->extBufPools,
orderedArray,
sizesArray);
p_FmVspEntry->extBufPools.numOfPoolsUsed =
p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools.numOfPoolsUsed;
for (i = 0; i < p_FmVspEntry->extBufPools.numOfPoolsUsed; i++)
{
p_FmVspEntry->extBufPools.extBufPool[i].id = orderedArray[i];
p_FmVspEntry->extBufPools.extBufPool[i].size = sizesArray[orderedArray[i]];
}
/* on user responsibility to fill it according requirement */
memset(&fm_vsp_params, 0, sizeof(struct fm_storage_profile_params));
fm_vsp_params.dma_swap_data = p_FmVspEntry->p_FmVspEntryDriverParams->dmaSwapData;
fm_vsp_params.int_context_cache_attr = p_FmVspEntry->p_FmVspEntryDriverParams->dmaIntContextCacheAttr;
fm_vsp_params.header_cache_attr = p_FmVspEntry->p_FmVspEntryDriverParams->dmaHeaderCacheAttr;
fm_vsp_params.scatter_gather_cache_attr = p_FmVspEntry->p_FmVspEntryDriverParams->dmaScatterGatherCacheAttr;
fm_vsp_params.dma_write_optimize = p_FmVspEntry->p_FmVspEntryDriverParams->dmaWriteOptimize;
fm_vsp_params.liodn_offset = p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset;
fm_vsp_params.no_scather_gather = p_FmVspEntry->p_FmVspEntryDriverParams->noScatherGather;
if (p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion)
{
fm_vsp_params.buf_pool_depletion.buf_pool_depletion_enabled = TRUE;
fm_vsp_params.buf_pool_depletion.pools_grp_mode_enable = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->poolsGrpModeEnable;
fm_vsp_params.buf_pool_depletion.num_pools = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->numOfPools;
fm_vsp_params.buf_pool_depletion.pools_to_consider = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->poolsToConsider;
fm_vsp_params.buf_pool_depletion.single_pool_mode_enable = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->singlePoolModeEnable;
fm_vsp_params.buf_pool_depletion.pools_to_consider_for_single_mode = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->poolsToConsiderForSingleMode;
fm_vsp_params.buf_pool_depletion.has_pfc_priorities = TRUE;
fm_vsp_params.buf_pool_depletion.pfc_priorities_en = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->pfcPrioritiesEn;
}
else
fm_vsp_params.buf_pool_depletion.buf_pool_depletion_enabled = FALSE;
if (p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools)
{
fm_vsp_params.backup_pools.num_backup_pools = p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools->numOfBackupPools;
fm_vsp_params.backup_pools.pool_ids = p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools->poolIds;
}
else
fm_vsp_params.backup_pools.num_backup_pools = 0;
fm_vsp_params.fm_ext_pools.num_pools_used = p_FmVspEntry->extBufPools.numOfPoolsUsed;
fm_vsp_params.fm_ext_pools.ext_buf_pool = (struct fman_ext_pool_params*)&p_FmVspEntry->extBufPools.extBufPool;
fm_vsp_params.buf_margins = (struct fman_sp_buf_margins*)&p_FmVspEntry->bufMargins;
fm_vsp_params.int_context = (struct fman_sp_int_context_data_copy*)&p_FmVspEntry->intContext;
/* no check on err - it was checked earlier */
FmVSPGetAbsoluteProfileId(p_FmVspEntry->h_Fm,
p_FmVspEntry->portType,
p_FmVspEntry->portId,
p_FmVspEntry->relativeProfileId,
&absoluteProfileId);
ASSERT_COND(p_FmVspEntry->p_FmSpRegsBase);
ASSERT_COND(fm_vsp_params.int_context);
ASSERT_COND(fm_vsp_params.buf_margins);
ASSERT_COND((absoluteProfileId <= FM_VSP_MAX_NUM_OF_ENTRIES));
/* Set all registers related to VSP */
fman_vsp_init(p_FmVspEntry->p_FmSpRegsBase, absoluteProfileId, &fm_vsp_params,FM_PORT_MAX_NUM_OF_EXT_POOLS, BM_MAX_NUM_OF_POOLS, FM_MAX_NUM_OF_PFC_PRIORITIES);
p_FmVspEntry->absoluteSpId = absoluteProfileId;
if (p_FmVspEntry->p_FmVspEntryDriverParams)
XX_Free(p_FmVspEntry->p_FmVspEntryDriverParams);
p_FmVspEntry->p_FmVspEntryDriverParams = NULL;
return E_OK;
}
t_Error FM_VSP_Free(t_Handle h_FmVsp)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry *)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(h_FmVsp, E_INVALID_HANDLE);
XX_Free(p_FmVspEntry);
return E_OK;
}
t_Error FM_VSP_ConfigBufferPrefixContent(t_Handle h_FmVsp, t_FmBufferPrefixContent *p_FmBufferPrefixContent)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
memcpy(&p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent, p_FmBufferPrefixContent, sizeof(t_FmBufferPrefixContent));
/* if dataAlign was not initialized by user, we return to driver's default */
if (!p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.dataAlign)
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.dataAlign = DEFAULT_FM_SP_bufferPrefixContent_dataAlign;
return E_OK;
}
t_Error FM_VSP_ConfigDmaSwapData(t_Handle h_FmVsp, e_FmDmaSwapOption swapData)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaSwapData = swapData;
return E_OK;
}
t_Error FM_VSP_ConfigDmaIcCacheAttr(t_Handle h_FmVsp, e_FmDmaCacheOption intContextCacheAttr)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaIntContextCacheAttr = intContextCacheAttr;
return E_OK;
}
t_Error FM_VSP_ConfigDmaHdrAttr(t_Handle h_FmVsp, e_FmDmaCacheOption headerCacheAttr)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaHeaderCacheAttr = headerCacheAttr;
return E_OK;
}
t_Error FM_VSP_ConfigDmaScatterGatherAttr(t_Handle h_FmVsp, e_FmDmaCacheOption scatterGatherCacheAttr)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaScatterGatherCacheAttr = scatterGatherCacheAttr;
return E_OK;
}
t_Error FM_VSP_ConfigDmaWriteOptimize(t_Handle h_FmVsp, bool optimize)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaWriteOptimize = optimize;
return E_OK;
}
t_Error FM_VSP_ConfigNoScatherGather(t_Handle h_FmVsp, bool noScatherGather)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->noScatherGather = noScatherGather;
return E_OK;
}
t_Error FM_VSP_ConfigPoolDepletion(t_Handle h_FmVsp, t_FmBufPoolDepletion *p_BufPoolDepletion)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(h_FmVsp, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BufPoolDepletion, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion = (t_FmBufPoolDepletion *)XX_Malloc(sizeof(t_FmBufPoolDepletion));
if (!p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("p_BufPoolDepletion allocation failed"));
memcpy(p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion, p_BufPoolDepletion, sizeof(t_FmBufPoolDepletion));
return E_OK;
}
t_Error FM_VSP_ConfigBackupPools(t_Handle h_FmVsp, t_FmBackupBmPools *p_BackupBmPools)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(h_FmVsp, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BackupBmPools, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools = (t_FmBackupBmPools *)XX_Malloc(sizeof(t_FmBackupBmPools));
if (!p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("p_BackupBmPools allocation failed"));
memcpy(p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools, p_BackupBmPools, sizeof(t_FmBackupBmPools));
return E_OK;
}
uint32_t FM_VSP_GetBufferDataOffset(t_Handle h_FmVsp)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, 0);
return p_FmVspEntry->bufferOffsets.dataOffset;
}
uint8_t * FM_VSP_GetBufferICInfo(t_Handle h_FmVsp, char *p_Data)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL);
if (p_FmVspEntry->bufferOffsets.pcdInfoOffset == ILLEGAL_BASE)
return NULL;
return (uint8_t *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.pcdInfoOffset);
}
t_FmPrsResult * FM_VSP_GetBufferPrsResult(t_Handle h_FmVsp, char *p_Data)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL);
if (p_FmVspEntry->bufferOffsets.prsResultOffset == ILLEGAL_BASE)
return NULL;
return (t_FmPrsResult *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.prsResultOffset);
}
uint64_t * FM_VSP_GetBufferTimeStamp(t_Handle h_FmVsp, char *p_Data)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL);
if (p_FmVspEntry->bufferOffsets.timeStampOffset == ILLEGAL_BASE)
return NULL;
return (uint64_t *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.timeStampOffset);
}
uint8_t * FM_VSP_GetBufferHashResult(t_Handle h_FmVsp, char *p_Data)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL);
if (p_FmVspEntry->bufferOffsets.hashResultOffset == ILLEGAL_BASE)
return NULL;
return (uint8_t *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.hashResultOffset);
}
#endif /* (DPAA_VERSION >= 11) */

85
sys/contrib/ncsw/Peripherals/FM/SP/fm_sp.h Normal file
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@ -0,0 +1,85 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_sp.h
@Description FM SP ...
*//***************************************************************************/
#ifndef __FM_SP_H
#define __FM_SP_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_sp_common.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_SP
typedef struct {
t_FmBufferPrefixContent bufferPrefixContent;
e_FmDmaSwapOption dmaSwapData;
e_FmDmaCacheOption dmaIntContextCacheAttr;
e_FmDmaCacheOption dmaHeaderCacheAttr;
e_FmDmaCacheOption dmaScatterGatherCacheAttr;
bool dmaWriteOptimize;
uint16_t liodnOffset;
bool noScatherGather;
t_FmBufPoolDepletion *p_BufPoolDepletion;
t_FmBackupBmPools *p_BackupBmPools;
t_FmExtPools extBufPools;
} t_FmVspEntryDriverParams;
typedef struct {
bool valid;
volatile bool lock;
uint8_t pointedOwners;
uint16_t absoluteSpId;
uint8_t internalBufferOffset;
t_FmSpBufMargins bufMargins;
t_FmSpIntContextDataCopy intContext;
t_FmSpBufferOffsets bufferOffsets;
t_Handle h_Fm;
e_FmPortType portType; /**< Port type */
uint8_t portId; /**< Port Id - relative to type */
uint8_t relativeProfileId;
struct fm_pcd_storage_profile_regs *p_FmSpRegsBase;
t_FmExtPools extBufPools;
t_FmVspEntryDriverParams *p_FmVspEntryDriverParams;
} t_FmVspEntry;
#endif /* __FM_SP_H */

197
sys/contrib/ncsw/Peripherals/FM/SP/fman_sp.c Executable file
View File

@ -0,0 +1,197 @@
/*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_sp.h"
uint32_t fman_vsp_get_statistics(struct fm_pcd_storage_profile_regs *regs,
uint16_t index)
{
struct fm_pcd_storage_profile_regs *sp_regs;
sp_regs = &regs[index];
return ioread32be(&sp_regs->fm_sp_acnt);
}
void fman_vsp_set_statistics(struct fm_pcd_storage_profile_regs *regs,
uint16_t index, uint32_t value)
{
struct fm_pcd_storage_profile_regs *sp_regs;
sp_regs = &regs[index];
iowrite32be(value, &sp_regs->fm_sp_acnt);
}
void fman_vsp_defconfig(struct fm_storage_profile_params *cfg)
{
cfg->dma_swap_data =
DEFAULT_FMAN_SP_DMA_SWAP_DATA;
cfg->int_context_cache_attr =
DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR;
cfg->header_cache_attr =
DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR;
cfg->scatter_gather_cache_attr =
DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR;
cfg->dma_write_optimize =
DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE;
cfg->no_scather_gather =
DEFAULT_FMAN_SP_NO_SCATTER_GATHER;
}
static inline uint32_t calc_vec_dep(int max_pools, bool *pools,
struct fman_ext_pools *ext_buf_pools, uint32_t mask)
{
int i, j;
uint32_t vector = 0;
for (i = 0; i < max_pools; i++)
if (pools[i])
for (j = 0; j < ext_buf_pools->num_pools_used; j++)
if (i == ext_buf_pools->ext_buf_pool[j].id) {
vector |= mask >> j;
break;
}
return vector;
}
void fman_vsp_init(struct fm_pcd_storage_profile_regs *regs,
uint16_t index, struct fm_storage_profile_params *fm_vsp_params,
int port_max_num_of_ext_pools, int bm_max_num_of_pools,
int max_num_of_pfc_priorities)
{
int i = 0, j = 0;
struct fm_pcd_storage_profile_regs *sp_regs;
uint32_t tmp_reg, vector;
struct fman_ext_pools *ext_buf_pools = &fm_vsp_params->fm_ext_pools;
struct fman_buf_pool_depletion *buf_pool_depletion =
&fm_vsp_params->buf_pool_depletion;
struct fman_backup_bm_pools *backup_pools =
&fm_vsp_params->backup_pools;
struct fman_sp_int_context_data_copy *int_context_data_copy =
fm_vsp_params->int_context;
struct fman_sp_buf_margins *external_buffer_margins =
fm_vsp_params->buf_margins;
bool no_scather_gather = fm_vsp_params->no_scather_gather;
uint16_t liodn_offset = fm_vsp_params->liodn_offset;
sp_regs = &regs[index];
/* fill external buffers manager pool information register*/
for (i = 0; i < ext_buf_pools->num_pools_used; i++) {
tmp_reg = FMAN_SP_EXT_BUF_POOL_VALID |
FMAN_SP_EXT_BUF_POOL_EN_COUNTER;
tmp_reg |= ((uint32_t)ext_buf_pools->ext_buf_pool[i].id <<
FMAN_SP_EXT_BUF_POOL_ID_SHIFT);
tmp_reg |= ext_buf_pools->ext_buf_pool[i].size;
/* functionality available only for some deriviatives
(limited by config) */
for (j = 0; j < backup_pools->num_backup_pools; j++)
if (ext_buf_pools->ext_buf_pool[i].id ==
backup_pools->pool_ids[j]) {
tmp_reg |= FMAN_SP_EXT_BUF_POOL_BACKUP;
break;
}
iowrite32be(tmp_reg, &sp_regs->fm_sp_ebmpi[i]);
}
/* clear unused pools */
for (i = ext_buf_pools->num_pools_used;
i < port_max_num_of_ext_pools; i++)
iowrite32be(0, &sp_regs->fm_sp_ebmpi[i]);
/* fill pool depletion register*/
tmp_reg = 0;
if (buf_pool_depletion->buf_pool_depletion_enabled && buf_pool_depletion->pools_grp_mode_enable) {
/* calculate vector for number of pools depletion */
vector = calc_vec_dep(bm_max_num_of_pools, buf_pool_depletion->
pools_to_consider, ext_buf_pools, 0x80000000);
/* configure num of pools and vector for number of pools mode */
tmp_reg |= (((uint32_t)buf_pool_depletion->num_pools - 1) <<
FMAN_SP_POOL_DEP_NUM_OF_POOLS_SHIFT);
tmp_reg |= vector;
}
if (buf_pool_depletion->buf_pool_depletion_enabled && buf_pool_depletion->single_pool_mode_enable) {
/* calculate vector for number of pools depletion */
vector = calc_vec_dep(bm_max_num_of_pools, buf_pool_depletion->
pools_to_consider_for_single_mode,
ext_buf_pools, 0x00000080);
/* configure num of pools and vector for number of pools mode */
tmp_reg |= vector;
}
/* fill QbbPEV */
if (buf_pool_depletion->buf_pool_depletion_enabled) {
vector = 0;
for (i = 0; i < max_num_of_pfc_priorities; i++)
if (buf_pool_depletion->pfc_priorities_en[i] == TRUE)
vector |= 0x00000100 << i;
tmp_reg |= vector;
}
iowrite32be(tmp_reg, &sp_regs->fm_sp_mpd);
/* fill dma attributes register */
tmp_reg = 0;
tmp_reg |= (uint32_t)fm_vsp_params->dma_swap_data <<
FMAN_SP_DMA_ATTR_SWP_SHIFT;
tmp_reg |= (uint32_t)fm_vsp_params->int_context_cache_attr <<
FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT;
tmp_reg |= (uint32_t)fm_vsp_params->header_cache_attr <<
FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT;
tmp_reg |= (uint32_t)fm_vsp_params->scatter_gather_cache_attr <<
FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT;
if (fm_vsp_params->dma_write_optimize)
tmp_reg |= FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE;
iowrite32be(tmp_reg, &sp_regs->fm_sp_da);
/* IC parameters - fill internal context parameters register */
tmp_reg = 0;
tmp_reg |= (((uint32_t)int_context_data_copy->ext_buf_offset/
OFFSET_UNITS) << FMAN_SP_IC_TO_EXT_SHIFT);
tmp_reg |= (((uint32_t)int_context_data_copy->int_context_offset/
OFFSET_UNITS) << FMAN_SP_IC_FROM_INT_SHIFT);
tmp_reg |= (((uint32_t)int_context_data_copy->size/OFFSET_UNITS) <<
FMAN_SP_IC_SIZE_SHIFT);
iowrite32be(tmp_reg, &sp_regs->fm_sp_icp);
/* buffer margins - fill external buffer margins register */
tmp_reg = 0;
tmp_reg |= (((uint32_t)external_buffer_margins->start_margins) <<
FMAN_SP_EXT_BUF_MARG_START_SHIFT);
tmp_reg |= (((uint32_t)external_buffer_margins->end_margins) <<
FMAN_SP_EXT_BUF_MARG_END_SHIFT);
if (no_scather_gather)
tmp_reg |= FMAN_SP_SG_DISABLE;
iowrite32be(tmp_reg, &sp_regs->fm_sp_ebm);
/* buffer margins - fill spliodn register */
iowrite32be(liodn_offset, &sp_regs->fm_sp_spliodn);
}

5588
sys/contrib/ncsw/Peripherals/FM/fm.c
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File diff suppressed because it is too large Load Diff

869
sys/contrib/ncsw/Peripherals/FM/fm.h
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File diff suppressed because it is too large Load Diff

106
sys/contrib/ncsw/Peripherals/FM/fm_ipc.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_ipc.h
@ -61,7 +62,6 @@
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/**************************************************************************//**
@Description enum for defining MAC types
@ -94,6 +94,17 @@ typedef _Packed struct t_FmIpcPhysAddr
volatile uint32_t low;
} _PackedType t_FmIpcPhysAddr;
typedef _Packed struct t_FmIpcPortOutInitParams {
uint8_t numOfTasks; /**< OUT */
uint8_t numOfExtraTasks; /**< OUT */
uint8_t numOfOpenDmas; /**< OUT */
uint8_t numOfExtraOpenDmas; /**< OUT */
uint32_t sizeOfFifo; /**< OUT */
uint32_t extraSizeOfFifo; /**< OUT */
t_FmIpcPhysAddr ipcPhysAddr; /**< OUT */
} _PackedType t_FmIpcPortOutInitParams;
/**************************************************************************//**
@Description Structure for IPC communication during FM_PORT_Init.
*//***************************************************************************/
@ -109,6 +120,7 @@ typedef _Packed struct t_FmIpcPortInInitParams {
uint32_t sizeOfFifo; /**< IN. Port's requested resource */
uint32_t extraSizeOfFifo; /**< IN. Port's requested resource */
uint8_t deqPipelineDepth; /**< IN. Port's requested resource */
uint16_t maxFrameLength; /**< IN. Port's max frame length. */
uint16_t liodnBase; /**< IN. Irrelevant for P4080 rev 1.
LIODN base for this port, to be
used together with LIODN offset. */
@ -148,9 +160,7 @@ typedef _Packed struct t_FmIpcPortFifoParams {
typedef _Packed struct t_FmIpcPortFreeParams {
uint8_t hardwarePortId; /**< IN. port Id */
uint32_t enumPortType; /**< IN. Port type */
#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT
uint8_t deqPipelineDepth; /**< IN. Port's requested resource */
#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */
} _PackedType t_FmIpcPortFreeParams;
/**************************************************************************//**
@ -162,6 +172,7 @@ typedef _Packed struct t_FmIpcDmaStatus {
uint8_t boolReadBufEccError; /**< Double ECC error on buffer Read */
uint8_t boolWriteBufEccSysError; /**< Double ECC error on buffer write from system side */
uint8_t boolWriteBufEccFmError; /**< Double ECC error on buffer write from FM side */
uint8_t boolSinglePortEccError; /**< Single port ECC error from FM side */
} _PackedType t_FmIpcDmaStatus;
typedef _Packed struct t_FmIpcRegisterIntr
@ -177,12 +188,24 @@ typedef _Packed struct t_FmIpcIsr
} _PackedType t_FmIpcIsr;
/**************************************************************************//**
@Description structure for returning revision information
@Description structure for returning FM parameters
*//***************************************************************************/
typedef _Packed struct t_FmIpcRevisionInfo {
typedef _Packed struct t_FmIpcParams {
uint16_t fmClkFreq; /**< OUT: FM Clock frequency */
uint16_t fmMacClkFreq; /**< OUT: FM MAC clock frequence */
uint8_t majorRev; /**< OUT: FM Major revision */
uint8_t minorRev; /**< OUT: FM Minor revision */
} _PackedType t_FmIpcParams;
/**************************************************************************//**
@Description structure for returning Fman Ctrl Code revision information
*//***************************************************************************/
typedef _Packed struct t_FmIpcFmanCtrlCodeRevisionInfo {
uint16_t packageRev; /**< OUT: Package revision */
uint8_t majorRev; /**< OUT: Major revision */
uint8_t minorRev; /**< OUT: Minor revision */
} _PackedType t_FmIpcRevisionInfo;
} _PackedType t_FmIpcFmanCtrlCodeRevisionInfo;
/**************************************************************************//**
@Description Structure for defining Fm number of Fman controlers
@ -190,19 +213,38 @@ typedef _Packed struct t_FmIpcRevisionInfo {
typedef _Packed struct t_FmIpcPortNumOfFmanCtrls {
uint8_t hardwarePortId; /**< IN. port Id */
uint8_t numOfFmanCtrls; /**< IN. Port type */
t_FmFmanCtrl orFmanCtrl; /**< IN. fman controller for order restoration*/
} t_FmIpcPortNumOfFmanCtrls;
/**************************************************************************//**
@Description structure for setting Fman contriller events
*//***************************************************************************/
typedef _Packed struct t_FmIpcFmanEvents {
uint8_t eventRegId; /**< IN: Fman controller event register id */
uint32_t enableEvents; /**< IN/OUT: required enabled events mask */
uint8_t eventRegId; /**< IN: Fman controller event register id */
uint32_t enableEvents; /**< IN/OUT: required enabled events mask */
} _PackedType t_FmIpcFmanEvents;
#define FM_IPC_MAX_REPLY_BODY_SIZE 16
typedef _Packed struct t_FmIpcResourceAllocParams {
uint8_t guestId;
uint16_t base;
uint16_t num;
}_PackedType t_FmIpcResourceAllocParams;
typedef _Packed struct t_FmIpcVspSetPortWindow {
uint8_t hardwarePortId;
uint8_t baseStorageProfile;
uint8_t log2NumOfProfiles;
}_PackedType t_FmIpcVspSetPortWindow;
typedef _Packed struct t_FmIpcSetCongestionGroupPfcPriority {
uint32_t congestionGroupId;
uint8_t priorityBitMap;
}_PackedType t_FmIpcSetCongestionGroupPfcPriority;
#define FM_IPC_MAX_REPLY_BODY_SIZE 20
#define FM_IPC_MAX_REPLY_SIZE (FM_IPC_MAX_REPLY_BODY_SIZE + sizeof(uint32_t))
#define FM_IPC_MAX_MSG_SIZE 30
typedef _Packed struct t_FmIpcMsg
{
uint32_t msgId;
@ -215,7 +257,6 @@ typedef _Packed struct t_FmIpcReply
uint8_t replyBody[FM_IPC_MAX_REPLY_BODY_SIZE];
} _PackedType t_FmIpcReply;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
@ -243,16 +284,6 @@ typedef _Packed struct t_FmIpcReply
*//***************************************************************************/
#define FM_GET_COUNTER 2
/**************************************************************************//**
@Function FM_DUMP_REGS
@Description Used by FM front-end for the PORT module in order to set and get
parameters in/from master FM module on FM PORT initialization time.
@Param None
*//***************************************************************************/
#define FM_DUMP_REGS 3
/**************************************************************************//**
@Function FM_GET_SET_PORT_PARAMS
@ -303,24 +334,14 @@ typedef _Packed struct t_FmIpcReply
#define FM_IS_PORT_STALLED 8
/**************************************************************************//**
@Function FM_DUMP_PORT_REGS
@Function FM_GET_PARAMS
@Description Used by FM front-end for the PORT module in order to dump
all port registers.
return FM parameters.
@Param[in] uint8_t Pointer
*//***************************************************************************/
#define FM_DUMP_PORT_REGS 9
/**************************************************************************//**
@Function FM_GET_REV
@Description Used by FM front-end for the PORT module in order to dump
all port registers.
@Param[in] uint8_t Pointer
*//***************************************************************************/
#define FM_GET_REV 10
#define FM_GET_PARAMS 10
/**************************************************************************//**
@Function FM_REGISTER_INTR
@ -332,15 +353,6 @@ typedef _Packed struct t_FmIpcReply
*//***************************************************************************/
#define FM_REGISTER_INTR 11
/**************************************************************************//**
@Function FM_GET_CLK_FREQ
@Description Used by FM Front-end to read the FM clock frequency.
@Param[out] uint32_t Pointer
*//***************************************************************************/
#define FM_GET_CLK_FREQ 12
/**************************************************************************//**
@Function FM_DMA_STAT
@ -422,7 +434,11 @@ typedef _Packed struct t_FmIpcReply
#define FM_SET_SIZE_OF_FIFO 24
#define FM_SET_NUM_OF_TASKS 25
#define FM_SET_NUM_OF_OPEN_DMAS 26
#define FM_VSP_ALLOC 27
#define FM_VSP_FREE 28
#define FM_VSP_SET_PORT_WINDOW 29
#define FM_GET_FMAN_CTRL_CODE_REV 30
#define FM_SET_CONG_GRP_PFC_PRIO 31
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
#define FM_10G_TX_ECC_WA 100
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */

18
sys/contrib/ncsw/Peripherals/FM/fm_muram.c
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File FM_muram.c
@ -43,7 +44,6 @@
#include "fm_muram_ext.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_MURAM
@ -158,7 +158,17 @@ t_Error FM_MURAM_FreeMem(t_Handle h_FmMuram, void *ptr)
SANITY_CHECK_RETURN_ERROR(p_FmMuram->h_Mem, E_INVALID_HANDLE);
if (MM_Put(p_FmMuram->h_Mem, PTR_TO_UINT(ptr)) == 0)
RETURN_ERROR(MINOR, E_INVALID_HANDLE, ("memory pointer!!!"));
RETURN_ERROR(MINOR, E_INVALID_ADDRESS, ("memory pointer!!!"));
return E_OK;
}
uint64_t FM_MURAM_GetFreeMemSize(t_Handle h_FmMuram)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
SANITY_CHECK_RETURN_VALUE(h_FmMuram, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(p_FmMuram->h_Mem, E_INVALID_HANDLE, 0);
return MM_GetFreeMemSize(p_FmMuram->h_Mem);
}

1398
sys/contrib/ncsw/Peripherals/FM/fman_ncsw.c Executable file
View File

File diff suppressed because it is too large Load Diff

917
sys/contrib/ncsw/Peripherals/FM/inc/fm_common.h
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File diff suppressed because it is too large Load Diff

33
sys/contrib/ncsw/Peripherals/FM/inc/fm_hc.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,12 +30,13 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FM_HC_H
#define __FM_HC_H
#include "std_ext.h"
#include "error_ext.h"
#include "fsl_fman_kg.h"
#define __ERR_MODULE__ MODULE_FM_PCD
@ -49,28 +50,29 @@ typedef struct t_FmHcParams {
t_Handle FmHcConfigAndInit(t_FmHcParams *p_FmHcParams);
void FmHcFree(t_Handle h_FmHc);
t_Error FmHcSetFramesDataMemory(t_Handle h_FmHc,
uint8_t memId);
t_Error FmHcDumpRegs(t_Handle h_FmHc);
void FmHcTxConf(t_Handle h_FmHc, t_DpaaFD *p_Fd);
t_Handle FmHcPcdKgSetScheme(t_Handle h_FmHc, t_FmPcdKgSchemeParams *p_Scheme);
t_Error FmHcPcdKgSetScheme(t_Handle h_FmHc,
t_Handle h_Scheme,
struct fman_kg_scheme_regs *p_SchemeRegs,
bool updateCounter);
t_Error FmHcPcdKgDeleteScheme(t_Handle h_FmHc, t_Handle h_Scheme);
t_Error FmHcPcdCcCapwapTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcCapwapReassmTimeoutParams *p_CcCapwapReassmTimeoutParams );
t_Error FmHcPcdCcIpFragScratchPollCmd(t_Handle h_FmHc, bool fill, t_FmPcdCcFragScratchPoolCmdParams *p_FmPcdCcFragScratchPoolCmdParams);
t_Error FmHcPcdCcTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcReassmTimeoutParams *p_CcReassmTimeoutParams, uint8_t *p_Result);
t_Error FmHcPcdKgSetClsPlan(t_Handle h_FmHc, t_FmPcdKgInterModuleClsPlanSet *p_Set);
t_Error FmHcPcdKgDeleteClsPlan(t_Handle h_FmHc, uint8_t clsPlanGrpId);
t_Error FmHcPcdKgSetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t value);
uint32_t FmHcPcdKgGetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme);
t_Error FmHcPcdCcModifyTreeNextEngine(t_Handle h_FmHc, t_Handle h_CcTree, uint8_t grpId, uint8_t index, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams);
t_Error FmHcPcdCcModifyNodeNextEngine(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams);
t_Error FmHcPcdCcModifyNodeMissNextEngine(t_Handle h_FmHc, t_Handle h_CcNode, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams);
t_Error FmHcPcdCcRemoveKey(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex);
t_Error FmHcPcdCcAddKey(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex, uint8_t keySize, t_FmPcdCcKeyParams *p_KeyParams);
t_Error FmHcPcdCcModifyKeyAndNextEngine(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex, uint8_t keySize, t_FmPcdCcKeyParams *p_KeyParams);
t_Error FmHcPcdCcModifyKey(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex, uint8_t keySize, uint8_t *p_Key, uint8_t *p_Mask);
t_Error FmHcPcdCcDoDynamicChange(t_Handle h_FmHc, uint32_t oldAdAddrOffset, uint32_t newAdAddrOffset);
t_Handle FmHcPcdPlcrSetProfile(t_Handle h_FmHc,t_FmPcdPlcrProfileParams *p_Profile);
t_Error FmHcPcdPlcrSetProfile(t_Handle h_FmHc, t_Handle h_Profile, t_FmPcdPlcrProfileRegs *p_PlcrRegs);
t_Error FmHcPcdPlcrDeleteProfile(t_Handle h_FmHc, t_Handle h_Profile);
t_Error FmHcPcdPlcrSetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter, uint32_t value);
@ -79,8 +81,13 @@ uint32_t FmHcPcdPlcrGetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_
t_Error FmHcKgWriteSp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t spReg, bool add);
t_Error FmHcKgWriteCpp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t cppReg);
t_Error FmHcPcdKgCcGetSetParams(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t requiredAction);
t_Error FmHcPcdKgCcGetSetParams(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t requiredAction, uint32_t value);
t_Error FmHcPcdPlcrCcGetSetParams(t_Handle h_FmHc,uint16_t absoluteProfileId, uint32_t requiredAction);
t_Error FmHcPcdSync(t_Handle h_FmHc);
t_Handle FmHcGetPort(t_Handle h_FmHc);
#endif /* __FM_HC_H */

117
sys/contrib/ncsw/Peripherals/FM/inc/fm_sp_common.h Normal file
View File

@ -0,0 +1,117 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_sp_common.h
@Description FM SP ...
*//***************************************************************************/
#ifndef __FM_SP_COMMON_H
#define __FM_SP_COMMON_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_ext.h"
#include "fm_pcd_ext.h"
#include "fsl_fman.h"
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
#define DEFAULT_FM_SP_bufferPrefixContent_privDataSize 0
#define DEFAULT_FM_SP_bufferPrefixContent_passPrsResult FALSE
#define DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp FALSE
#define DEFAULT_FM_SP_bufferPrefixContent_allOtherPCDInfo FALSE
#define DEFAULT_FM_SP_bufferPrefixContent_dataAlign 64
/**************************************************************************//**
@Description structure for defining internal context copying
*//***************************************************************************/
typedef struct
{
uint16_t extBufOffset; /**< Offset in External buffer to which internal
context is copied to (Rx) or taken from (Tx, Op). */
uint8_t intContextOffset; /**< Offset within internal context to copy from
(Rx) or to copy to (Tx, Op). */
uint16_t size; /**< Internal offset size to be copied */
} t_FmSpIntContextDataCopy;
/**************************************************************************//**
@Description struct for defining external buffer margins
*//***************************************************************************/
typedef struct {
uint16_t startMargins; /**< Number of bytes to be left at the beginning
of the external buffer (must be divisible by 16) */
uint16_t endMargins; /**< number of bytes to be left at the end
of the external buffer(must be divisible by 16) */
} t_FmSpBufMargins;
typedef struct {
uint32_t dataOffset;
uint32_t prsResultOffset;
uint32_t timeStampOffset;
uint32_t hashResultOffset;
uint32_t pcdInfoOffset;
uint32_t manipOffset;
} t_FmSpBufferOffsets;
t_Error FmSpBuildBufferStructure(t_FmSpIntContextDataCopy *p_FmPortIntContextDataCopy,
t_FmBufferPrefixContent *p_BufferPrefixContent,
t_FmSpBufMargins *p_FmPortBufMargins,
t_FmSpBufferOffsets *p_FmPortBufferOffsets,
uint8_t *internalBufferOffset);
t_Error FmSpCheckIntContextParams(t_FmSpIntContextDataCopy *p_FmSpIntContextDataCopy);
t_Error FmSpCheckBufPoolsParams(t_FmExtPools *p_FmExtPools,
t_FmBackupBmPools *p_FmBackupBmPools,
t_FmBufPoolDepletion *p_FmBufPoolDepletion);
t_Error FmSpCheckBufMargins(t_FmSpBufMargins *p_FmSpBufMargins);
void FmSpSetBufPoolsInAscOrderOfBufSizes(t_FmExtPools *p_FmExtPools, uint8_t *orderedArray, uint16_t *sizesArray);
t_Error FmPcdSpAllocProfiles(t_Handle h_FmPcd,
uint8_t hardwarePortId,
uint16_t numOfStorageProfiles,
uint16_t *base,
uint8_t *log2Num);
t_Error FmPcdSpGetAbsoluteProfileId(t_Handle h_FmPcd,
t_Handle h_FmPort,
uint16_t relativeProfile,
uint16_t *p_AbsoluteId);
void SpInvalidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId);
void SpValidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId);
#endif /* __FM_SP_COMMON_H */

2
sys/contrib/ncsw/Peripherals/QM/fsl_qman.h
View File

@ -117,7 +117,7 @@ struct qm_portal_config {
* affinity configured. */
int cpu;
/* portal interrupt line */
int irq;
uintptr_t irq;
/* The portal's dedicated channel id, use this value for initializing
* frame queues to target this portal when scheduled. */
e_QmFQChannel channel;

11
sys/contrib/ncsw/Peripherals/QM/qm.c
View File

@ -38,6 +38,10 @@
@Description QM & Portal implementation
*//***************************************************************************/
#include <sys/cdefs.h>
#include <sys/types.h>
#include <machine/atomic.h>
#include "error_ext.h"
#include "std_ext.h"
#include "string_ext.h"
@ -209,7 +213,7 @@ static t_Error QmInitPfdr(t_Qm *p_Qm, uint32_t pfdr_start, uint32_t num)
WRITE_UINT32(p_Qm->p_QmRegs->mcp1, (pfdr_start + num - 16));
WRITE_UINT32(p_Qm->p_QmRegs->mcp1, (pfdr_start + num - 1));
CORE_MemoryBarrier();
mb();
WRITE_UINT32(p_Qm->p_QmRegs->mcr, MCR_INIT_PFDR);
/* Poll for the result */
@ -556,6 +560,7 @@ uint32_t QmFqidGet(t_Qm *p_Qm, uint32_t size, uint32_t alignment, bool force, ui
"QM FQID MEM");
XX_UnlockIntrSpinlock(p_Qm->lock, intFlags);
KASSERT(ans < UINT32_MAX, ("Oops, %lx > UINT32_MAX!\n", ans));
return (uint32_t)ans;
}
@ -784,10 +789,10 @@ t_Error QM_Init(t_Handle h_Qm)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FQD obj!!!"));
}
memset(p_Qm->p_FqdBase, 0, dsSize);
CORE_MemoryBarrier();
mb();
for (i=0; i<dsSize; i+=64)
dcbf(PTR_MOVE(p_Qm->p_FqdBase, i));
CORE_MemoryBarrier();
mb();
phyAddr = XX_VirtToPhys(p_Qm->p_FqdBase);
WRITE_UINT32(p_Qm->p_QmRegs->fqd_bare, ((uint32_t)(phyAddr >> 32) & 0x000000ff));

2
sys/contrib/ncsw/Peripherals/QM/qm.h
View File

@ -482,7 +482,7 @@ typedef struct {
uint32_t exceptions;
t_QmExceptionsCallback *f_Exception;
t_Handle h_App;
int errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */
uintptr_t errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */
uint32_t numOfPfdr;
uint16_t partNumOfCgs;
uint16_t partCgsBase;

74
sys/contrib/ncsw/Peripherals/QM/qm_portal_fqr.c
View File

@ -38,6 +38,10 @@
@Description QM & Portal implementation
*//***************************************************************************/
#include <sys/cdefs.h>
#include <sys/types.h>
#include <machine/atomic.h>
#include "error_ext.h"
#include "std_ext.h"
#include "string_ext.h"
@ -45,6 +49,7 @@
#include "qm.h"
#include "qman_low.h"
#include <machine/vmparam.h>
/****************************************/
/* static functions */
@ -53,6 +58,40 @@
#define SLOW_POLL_IDLE 1000
#define SLOW_POLL_BUSY 10
/*
* Context entries are 32-bit. The qman driver uses the pointer to the queue as
* its context, and the pointer is 64-byte aligned, per the XX_MallocSmart()
* call. Take advantage of this fact to shove a 64-bit kernel pointer into a
* 32-bit context integer, and back.
*
* XXX: This depends on the fact that VM_MAX_KERNEL_ADDRESS is less than 38-bit
* count from VM_MIN_KERNEL_ADDRESS. If this ever changes, this needs to be
* updated.
*/
CTASSERT((VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS) < (1ULL << 35));
static inline uint32_t
aligned_int_from_ptr(const void *p)
{
uintptr_t ctx;
ctx = (uintptr_t)p;
KASSERT(ctx >= VM_MIN_KERNEL_ADDRESS, ("%p is too low!\n", p));
ctx -= VM_MIN_KERNEL_ADDRESS;
KASSERT((ctx & 0x07) == 0, ("Pointer %p is not 8-byte aligned!\n", p));
if ((ctx & (0x7)) != 0)
return (0);
return (ctx >> 3);
}
static inline void *
ptr_from_aligned_int(uint32_t ctx)
{
uintptr_t p;
p = VM_MIN_KERNEL_ADDRESS + (ctx << 3);
return ((void *)p);
}
static t_Error qman_volatile_dequeue(t_QmPortal *p_QmPortal,
struct qman_fq *p_Fq,
@ -259,7 +298,7 @@ static t_Error qman_retire_fq(t_QmPortal *p_QmPortal,
p_Mcc = qm_mc_start(p_QmPortal->p_LowQmPortal);
p_Mcc->alterfq.fqid = p_Fq->fqid;
if (drain)
p_Mcc->alterfq.context_b = (uint32_t)PTR_TO_UINT(p_Fq);
p_Mcc->alterfq.context_b = aligned_int_from_ptr(p_Fq);
qm_mc_commit(p_QmPortal->p_LowQmPortal,
(uint8_t)((drain)?QM_MCC_VERB_ALTER_RETIRE_CTXB:QM_MCC_VERB_ALTER_RETIRE));
while (!(p_Mcr = qm_mc_result(p_QmPortal->p_LowQmPortal))) ;
@ -568,8 +607,8 @@ static uint32_t LoopMessageRing(t_QmPortal *p_QmPortal, uint32_t is)
qmPortalMrPvbUpdate(p_QmPortal->p_LowQmPortal);
p_Msg = qm_mr_current(p_QmPortal->p_LowQmPortal);
if (p_Msg) {
struct qman_fq *p_FqFqs = UINT_TO_PTR(p_Msg->fq.contextB);
struct qman_fq *p_FqErn = UINT_TO_PTR(p_Msg->ern.tag);
struct qman_fq *p_FqFqs = ptr_from_aligned_int(p_Msg->fq.contextB);
struct qman_fq *p_FqErn = ptr_from_aligned_int(p_Msg->ern.tag);
uint8_t verb =(uint8_t)(p_Msg->verb & QM_MR_VERB_TYPE_MASK);
t_QmRejectedFrameInfo rejectedFrameInfo;
@ -646,7 +685,7 @@ static void LoopDequeueRing(t_Handle h_QmPortal)
p_Dq = qm_dqrr_current(p_QmPortal->p_LowQmPortal);
if (!p_Dq)
break;
p_Fq = UINT_TO_PTR(p_Dq->contextB);
p_Fq = ptr_from_aligned_int(p_Dq->contextB);
if (p_Dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
/* We only set QMAN_FQ_STATE_NE when retiring, so we only need
* to check for clearing it when doing volatile dequeues. It's
@ -728,7 +767,7 @@ static void LoopDequeueRingDcaOptimized(t_Handle h_QmPortal)
p_Dq = qm_dqrr_current(p_QmPortal->p_LowQmPortal);
if (!p_Dq)
break;
p_Fq = UINT_TO_PTR(p_Dq->contextB);
p_Fq = ptr_from_aligned_int(p_Dq->contextB);
if (p_Dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
/* We only set QMAN_FQ_STATE_NE when retiring, so we only need
* to check for clearing it when doing volatile dequeues. It's
@ -802,7 +841,7 @@ static void LoopDequeueRingOptimized(t_Handle h_QmPortal)
p_Dq = qm_dqrr_current(p_QmPortal->p_LowQmPortal);
if (!p_Dq)
break;
p_Fq = UINT_TO_PTR(p_Dq->contextB);
p_Fq = ptr_from_aligned_int(p_Dq->contextB);
if (p_Dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
/* We only set QMAN_FQ_STATE_NE when retiring, so we only need
* to check for clearing it when doing volatile dequeues. It's
@ -1023,13 +1062,8 @@ static t_Error qm_new_fq(t_QmPortal *p_QmPortal,
/* If this FQ will not be used for tx, we can use contextB field */
if (fq_opts.fqd.dest.channel < e_QM_FQ_CHANNEL_FMAN0_SP0)
{
if (sizeof(p_Fqs[0]) <= sizeof(fq_opts.fqd.context_b))
{
fq_opts.we_mask |= QM_INITFQ_WE_CONTEXTB;
fq_opts.fqd.context_b = (uint32_t)PTR_TO_UINT(p_Fqs[0]);
}
else
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("64 bit pointer (virtual) not supported yet!!!"));
fq_opts.fqd.context_b = aligned_int_from_ptr(p_Fqs[0]);
}
else if (p_ContextB) /* Tx-Queue */
{
@ -1102,7 +1136,7 @@ static t_Error qm_free_fq(t_QmPortal *p_QmPortal, struct qman_fq *p_Fq)
{
uint32_t flags=0;
if (qman_retire_fq(p_QmPortal, p_Fq, &flags, FALSE) != E_OK)
if (qman_retire_fq(p_QmPortal, p_Fq, &flags, false) != E_OK)
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("qman_retire_fq() failed!"));
if (flags & QMAN_FQ_STATE_CHANGING)
@ -1471,7 +1505,7 @@ static t_Error QmPortalPullFrame(t_Handle h_QmPortal, uint32_t pdqcr, t_DpaaFD *
NCSW_PLOCK(p_QmPortal);
qm_dqrr_pdqcr_set(p_QmPortal->p_LowQmPortal, pdqcr);
CORE_MemoryBarrier();
mb();
while (qm_dqrr_pdqcr_get(p_QmPortal->p_LowQmPortal)) ;
prefetch = !(p_QmPortal->options & QMAN_PORTAL_FLAG_RSTASH);
@ -1483,7 +1517,7 @@ static t_Error QmPortalPullFrame(t_Handle h_QmPortal, uint32_t pdqcr, t_DpaaFD *
p_Dq = qm_dqrr_current(p_QmPortal->p_LowQmPortal);
if (!p_Dq)
continue;
p_Fq = UINT_TO_PTR(p_Dq->contextB);
p_Fq = ptr_from_aligned_int(p_Dq->contextB);
ASSERT_COND(p_Dq->fqid);
p_Dst = (uint32_t *)p_Frame;
p_Src = (uint32_t *)&p_Dq->fd;
@ -1495,7 +1529,7 @@ static t_Error QmPortalPullFrame(t_Handle h_QmPortal, uint32_t pdqcr, t_DpaaFD *
{
qmPortalDqrrDcaConsume1ptr(p_QmPortal->p_LowQmPortal,
p_Dq,
FALSE);
false);
qm_dqrr_next(p_QmPortal->p_LowQmPortal);
}
else
@ -1811,7 +1845,7 @@ t_Error QM_PORTAL_PollFrame(t_Handle h_QmPortal, t_QmPortalFrameInfo *p_frameInf
PUNLOCK(p_QmPortal);
return ERROR_CODE(E_EMPTY);
}
p_Fq = UINT_TO_PTR(p_Dq->contextB);
p_Fq = ptr_from_aligned_int(p_Dq->contextB);
ASSERT_COND(p_Dq->fqid);
if (p_Fq)
{
@ -1830,7 +1864,7 @@ t_Error QM_PORTAL_PollFrame(t_Handle h_QmPortal, t_QmPortalFrameInfo *p_frameInf
if (p_QmPortal->options & QMAN_PORTAL_FLAG_DCA) {
qmPortalDqrrDcaConsume1ptr(p_QmPortal->p_LowQmPortal,
p_Dq,
FALSE);
false);
qm_dqrr_next(p_QmPortal->p_LowQmPortal);
} else {
qm_dqrr_next(p_QmPortal->p_LowQmPortal);
@ -2064,7 +2098,7 @@ t_Error QM_FQR_FreeWDrain(t_Handle h_QmFqr,
for (i=0;i<p_QmFqr->numOfFqids;i++)
{
if (qman_retire_fq(p_QmFqr->h_QmPortal, p_QmFqr->p_Fqs[i], 0, TRUE) != E_OK)
if (qman_retire_fq(p_QmFqr->h_QmPortal, p_QmFqr->p_Fqs[i], 0, true) != E_OK)
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("qman_retire_fq() failed!"));
if (p_QmFqr->p_Fqs[i]->flags & QMAN_FQ_STATE_CHANGING)
@ -2141,7 +2175,7 @@ t_Error QM_FQR_Enqueue(t_Handle h_QmFqr, t_Handle h_QmPortal, uint32_t fqidOffse
}
p_Eq->fqid = p_Fq->fqid;
p_Eq->tag = (uintptr_t)p_Fq;
p_Eq->tag = aligned_int_from_ptr(p_Fq);
/* gcc does a dreadful job of the following;
* eq->fd = *fd;
* It causes the entire function to save/restore a wider range of

10
sys/contrib/ncsw/Peripherals/QM/qman_low.h
View File

@ -96,7 +96,7 @@ static __inline__ void *ptr_ADD(void *a, uintptr_t b)
/* Bitwise-OR two pointers */
static __inline__ void *ptr_OR(void *a, uintptr_t b)
{
return (void *)((uintptr_t)a + b);
return (void *)((uintptr_t)a | b);
}
/* Cache-inhibited register access */
@ -323,7 +323,7 @@ static __inline__ void qmPortalEqcrPciCommit(struct qm_portal *portal, uint8_t m
EQCR_INC(eqcr);
eqcr->available--;
dcbf_64(eqcr->cursor);
hwsync();
mb();
qm_out(EQCR_PI_CINH, EQCR_PTR2IDX(eqcr->cursor));
#ifdef QM_CHECKING
eqcr->busy = 0;
@ -351,7 +351,7 @@ static __inline__ void qmPortalEqcrPceCommit(struct qm_portal *portal, uint8_t m
EQCR_INC(eqcr);
eqcr->available--;
dcbf_64(eqcr->cursor);
lwsync();
wmb();
qm_cl_out(EQCR_PI, EQCR_PTR2IDX(eqcr->cursor));
#ifdef QM_CHECKING
eqcr->busy = 0;
@ -366,7 +366,7 @@ static __inline__ void qmPortalEqcrPvbCommit(struct qm_portal *portal, uint8_t m
EQCR_COMMIT_CHECKS(eqcr);
ASSERT_COND(eqcr->pmode == e_QmPortalPVB);
#endif /* QM_CHECKING */
lwsync();
rmb();
eqcursor = eqcr->cursor;
eqcursor->__dont_write_directly__verb = (uint8_t)(myverb | eqcr->vbit);
dcbf_64(eqcursor);
@ -1086,7 +1086,7 @@ static __inline__ void qm_mc_commit(struct qm_portal *portal, uint8_t myverb)
#ifdef QM_CHECKING
ASSERT_COND(mc->state == mc_user);
#endif /* QM_CHECKING */
lwsync();
rmb();
mc->cr->__dont_write_directly__verb = (uint8_t)(myverb | mc->vbit);
dcbf_64(mc->cr);
dcbit_ro(mc->rr + mc->rridx);

81
sys/contrib/ncsw/Peripherals/QM/qman_private.h
View File

@ -55,76 +55,13 @@
* and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or
* execution reordering with respect to other code/instructions that manipulate
* the same cacheline. */
#ifdef CORE_E500MC
#if defined(_DIAB_TOOL)
#define hwsync() \
do { \
__asm__ __volatile__ ("sync"); \
} while(0)
#define lwsync() \
do { \
__asm__ __volatile__ ("lwsync"); \
} while(0)
__asm__ __volatile__ void dcbf (volatile void * addr)
{
%reg addr
dcbf r0, addr
}
__asm__ __volatile__ void dcbt_ro (volatile void * addr)
{
%reg addr
dcbt r0, addr
}
__asm__ __volatile__ void dcbt_rw (volatile void * addr)
{
%reg addr
dcbtst r0, addr
}
__asm__ __volatile__ void dcbzl (volatile void * addr)
{
%reg addr
dcbzl r0, addr
}
#define dcbz_64(p) \
do { \
dcbzl(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbt_ro(p); \
} while (0)
#else /* GNU C */
#define hwsync() \
do { \
__asm__ __volatile__ ("sync" : : : "memory"); \
} while(0)
#define lwsync() \
do { \
__asm__ __volatile__ ("lwsync" : : : "memory"); \
} while(0)
#define dcbf(addr) \
do { \
__asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \
} while(0)
#ifdef CORE_E500MC
#define dcbt_ro(addr) \
do { \
__asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \
@ -157,16 +94,8 @@ __asm__ __volatile__ void dcbzl (volatile void * addr)
dcbt_ro(p); \
} while (0)
#endif /* _DIAB_TOOL */
#else
#define hwsync CORE_MemoryBarrier
#define lwsync hwsync
#define dcbf(p) \
do { \
__asm__ __volatile__ ("dcbf 0,%0" : : "r" (p)); \
} while(0)
#define dcbt_ro(p) \
do { \
__asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \
@ -182,21 +111,21 @@ __asm__ __volatile__ void dcbzl (volatile void * addr)
} while (0)
#define dcbz_64(p) \
do { \
dcbz((uint32_t)p + 32); \
dcbz((char *)p + 32); \
dcbz(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf((uint32_t)p + 32); \
dcbf((char *)p + 32); \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbi((uint32_t)p + 32); \
dcbi((char *)p + 32); \
dcbt_ro(p); \
dcbt_ro((uint32_t)p + 32); \
dcbt_ro((char *)p + 32); \
} while (0)
#endif /* CORE_E500MC */

113
sys/contrib/ncsw/etc/error.c
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,14 +30,16 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
@File error.c
@Description General errors and events reporting utilities.
*//***************************************************************************/
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
#include "error_ext.h"
const char *dbgLevelStrings[] =
{
@ -49,70 +51,45 @@ const char *dbgLevelStrings[] =
,"TRACE"
};
const char *errTypeStrings[] =
char * ErrTypeStrings (e_ErrorType err)
{
"Invalid State" /* E_INVALID_STATE */
,"Invalid Operation" /* E_INVALID_OPERATION */
,"Unsupported Operation" /* E_NOT_SUPPORTED */
,"No Device" /* E_NO_DEVICE */
,"Invalid Handle" /* E_INVALID_HANDLE */
,"Invalid ID" /* E_INVALID_ID */
,"Unexpected NULL Pointer" /* E_NULL_POINTER */
,"Invalid Value" /* E_INVALID_VALUE */
,"Invalid Selection" /* E_INVALID_SELECTION */
,"Invalid Communication Mode" /* E_INVALID_COMM_MODE */
,"Invalid Byte Order" /* E_INVALID_BYTE_ORDER */
,"Invalid Memory Type" /* E_INVALID_MEMORY_TYPE */
,"Invalid Interrupt Queue" /* E_INVALID_INTR_QUEUE */
,"Invalid Priority" /* E_INVALID_PRIORITY */
,"Invalid Clock" /* E_INVALID_CLOCK */
,"Invalid Rate" /* E_INVALID_RATE */
,"Invalid Address" /* E_INVALID_ADDRESS */
,"Invalid Bus" /* E_INVALID_BUS */
,"Conflict In Bus Selection" /* E_BUS_CONFLICT */
,"Conflict In Settings" /* E_CONFLICT */
,"Incorrect Alignment" /* E_NOT_ALIGNED */
,"Value Out Of Range" /* E_NOT_IN_RANGE */
,"Invalid Frame" /* E_INVALID_FRAME */
,"Frame Is Empty" /* E_EMPTY_FRAME */
,"Buffer Is Empty" /* E_EMPTY_BUFFER */
,"Memory Allocation Failed" /* E_NO_MEMORY */
,"Resource Not Found" /* E_NOT_FOUND */
,"Resource Is Unavailable" /* E_NOT_AVAILABLE */
,"Resource Already Exists" /* E_ALREADY_EXISTS */
,"Resource Is Full" /* E_FULL */
,"Resource Is Empty" /* E_EMPTY */
,"Resource Is Busy" /* E_BUSY */
,"Resource Already Free" /* E_ALREADY_FREE */
,"Read Access Failed" /* E_READ_FAILED */
,"Write Access Failed" /* E_WRITE_FAILED */
,"Send Operation Failed" /* E_SEND_FAILED */
,"Receive Operation Failed" /* E_RECEIVE_FAILED */
,"Operation Timed Out" /* E_TIMEOUT */
};
#if (defined(REPORT_EVENTS) && (REPORT_EVENTS > 0))
const char *eventStrings[] =
{
"Rx Discard" /* EV_RX_DISCARD */
,"Rx Error" /* EV_RX_ERROR */
,"Tx Error" /* EV_TX_ERROR */
,"No Buffer Objects" /* EV_NO_BUFFERS */
,"No MB-Frame Objects" /* EV_NO_MB_FRAMES */
,"No SB-Frame Objects" /* EV_NO_SB_FRAMES */
,"Tx Queue Is Full" /* EV_TX_QUEUE_FULL */
,"Rx Queue Is Full" /* EV_RX_QUEUE_FULL */
,"Interrupts Queue Is Full" /* EV_INTR_QUEUE_FULL */
,"Data Buffer Is Unavailable" /* EV_NO_DATA_BUFFER */
,"Objects Pool Is Empty" /* EV_OBJ_POOL_EMPTY */
,"Illegal bus access" /* EV_BUS_ERROR */
,"PTP Tx Timestamps Queue Is Full" /* EV_PTP_TXTS_QUEUE_FULL */
,"PTP Rx Timestamps Queue Is Full" /* EV_PTP_RXTS_QUEUE_FULL */
};
#endif /* (defined(REPORT_EVENTS) && (REPORT_EVENTS > 0)) */
switch (err)
{
case (E_OK): return "OK";
case (E_WRITE_FAILED): return "Write Access Failed";
case (E_NO_DEVICE): return "No Device";
case (E_NOT_AVAILABLE): return "Resource Is Unavailable";
case (E_NO_MEMORY): return "Memory Allocation Failed";
case (E_INVALID_ADDRESS): return "Invalid Address";
case (E_BUSY): return "Resource Is Busy";
case (E_ALREADY_EXISTS): return "Resource Already Exists";
case (E_INVALID_OPERATION): return "Invalid Operation";
case (E_INVALID_VALUE): return "Invalid Value";
case (E_NOT_IN_RANGE): return "Value Out Of Range";
case (E_NOT_SUPPORTED): return "Unsupported Operation";
case (E_INVALID_STATE): return "Invalid State";
case (E_INVALID_HANDLE): return "Invalid Handle";
case (E_INVALID_ID): return "Invalid ID";
case (E_NULL_POINTER): return "Unexpected NULL Pointer";
case (E_INVALID_SELECTION): return "Invalid Selection";
case (E_INVALID_COMM_MODE): return "Invalid Communication Mode";
case (E_INVALID_MEMORY_TYPE): return "Invalid Memory Type";
case (E_INVALID_CLOCK): return "Invalid Clock";
case (E_CONFLICT): return "Conflict In Settings";
case (E_NOT_ALIGNED): return "Incorrect Alignment";
case (E_NOT_FOUND): return "Resource Not Found";
case (E_FULL): return "Resource Is Full";
case (E_EMPTY): return "Resource Is Empty";
case (E_ALREADY_FREE): return "Resource Already Free";
case (E_READ_FAILED): return "Read Access Failed";
case (E_INVALID_FRAME): return "Invalid Frame";
case (E_SEND_FAILED): return "Send Operation Failed";
case (E_RECEIVE_FAILED): return "Receive Operation Failed";
case (E_TIMEOUT): return "Operation Timed Out";
default:
break;
}
return NULL;
}
#endif /* (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) */

12
sys/contrib/ncsw/etc/list.c
View File

@ -40,30 +40,30 @@
#include "list_ext.h"
void LIST_Append(t_List *p_NewList, t_List *p_Head)
void NCSW_LIST_Append(t_List *p_NewList, t_List *p_Head)
{
t_List *p_First = NCSW_LIST_FIRST(p_NewList);
if (p_First != p_NewList)
{
t_List *p_Last = LIST_LAST(p_NewList);
t_List *p_Last = NCSW_LIST_LAST(p_NewList);
t_List *p_Cur = NCSW_LIST_NEXT(p_Head);
NCSW_LIST_PREV(p_First) = p_Head;
NCSW_LIST_FIRST(p_Head) = p_First;
NCSW_LIST_NEXT(p_Last) = p_Cur;
LIST_LAST(p_Cur) = p_Last;
NCSW_LIST_LAST(p_Cur) = p_Last;
}
}
int LIST_NumOfObjs(t_List *p_List)
int NCSW_LIST_NumOfObjs(t_List *p_List)
{
t_List *p_Tmp;
int numOfObjs = 0;
if (!LIST_IsEmpty(p_List))
LIST_FOR_EACH(p_Tmp, p_List)
if (!NCSW_LIST_IsEmpty(p_List))
NCSW_LIST_FOR_EACH(p_Tmp, p_List)
numOfObjs++;
return numOfObjs;

99
sys/contrib/ncsw/etc/memcpy.c
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -31,76 +31,31 @@
*/
#include "std_ext.h"
#include "xx_ext.h"
#include "memcpy_ext.h"
#ifdef CORE_8BIT_ACCESS_ERRATA
static void MY_MY_WRITE_UINT8(uint8_t *addr, uint8_t val)
void * MemCpy8(void* pDst, void* pSrc, uint32_t size)
{
uint32_t newAddr, newVal;
newAddr = (uint32_t)addr & ~0x3L;
switch ((uint32_t)addr%4)
{
case (0):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0x00ffffff) | (((uint32_t)val)<<24);
WRITE_UINT32(*(uint32_t*)newAddr, newVal);
break;
case (1):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0xff00ffff) | (((uint32_t)val)<<16);
WRITE_UINT32(*(uint32_t*)newAddr, newVal);
break;
case (2):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0xffff00ff) | (((uint32_t)val)<<8);
WRITE_UINT32(*(uint32_t*)newAddr, newVal);
break;
case (3):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0xffffff00) | val;
WRITE_UINT32(*(uint32_t*)newAddr, newVal);
break;
}
int i;
for(i = 0; i < size; ++i)
*(((uint8_t*)(pDst)) + i) = *(((uint8_t*)(pSrc)) + i);
return pDst;
}
static uint8_t MY_MY_GET_UINT8(uint8_t *addr)
void * MemSet8(void* pDst, int c, uint32_t size)
{
uint32_t newAddr, newVal=0;
newAddr = (uint32_t)addr & ~0x3L;
switch ((uint32_t)addr%4)
{
case (0):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0xff000000)>>24;
break;
case (1):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0x00ff0000)>>16;
break;
case (2):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0x0000ff00)>>8;
break;
case (3):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0x000000ff);
break;
}
int i;
return (uint8_t)newVal;
for(i = 0; i < size; ++i)
*(((uint8_t*)(pDst)) + i) = (uint8_t)(c);
return pDst;
}
#define MY_WRITE_UINT8(addr,val) MY_MY_WRITE_UINT8(&addr,val)
#define MY_GET_UINT8(addr) MY_MY_GET_UINT8(&addr)
#else
#define MY_WRITE_UINT8 WRITE_UINT8
#define MY_GET_UINT8 GET_UINT8
#endif /* CORE_8BIT_ACCESS_ERRATA */
void * MemCpy32(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
@ -194,7 +149,7 @@ void * IO2IOCpy32(void* pDst,void* pSrc, uint32_t size)
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, MY_GET_UINT8(*p_Src8));
WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8));
p_Dst8++;p_Src8++;
size--;
}
@ -202,7 +157,7 @@ void * IO2IOCpy32(void* pDst,void* pSrc, uint32_t size)
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, MY_GET_UINT8(*p_Src8));
WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8));
p_Dst8++;p_Src8++;
size--;
}
@ -247,7 +202,7 @@ void * IO2IOCpy32(void* pDst,void* pSrc, uint32_t size)
/* complete the left overs */
while (size--)
{
MY_WRITE_UINT8(*p_Dst8, MY_GET_UINT8(*p_Src8));
WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8));
p_Dst8++;p_Src8++;
}
@ -273,7 +228,7 @@ void * Mem2IOCpy32(void* pDst,void* pSrc, uint32_t size)
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, *p_Src8);
WRITE_UINT8(*p_Dst8, *p_Src8);
p_Dst8++;p_Src8++;
size--;
}
@ -281,7 +236,7 @@ void * Mem2IOCpy32(void* pDst,void* pSrc, uint32_t size)
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, *p_Src8);
WRITE_UINT8(*p_Dst8, *p_Src8);
p_Dst8++;p_Src8++;
size--;
}
@ -325,7 +280,7 @@ void * Mem2IOCpy32(void* pDst,void* pSrc, uint32_t size)
/* complete the left overs */
while (size--)
{
MY_WRITE_UINT8(*p_Dst8, *p_Src8);
WRITE_UINT8(*p_Dst8, *p_Src8);
p_Dst8++;p_Src8++;
}
@ -351,7 +306,7 @@ void * IO2MemCpy32(void* pDst,void* pSrc, uint32_t size)
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
*p_Dst8 = MY_GET_UINT8(*p_Src8);
*p_Dst8 = GET_UINT8(*p_Src8);
p_Dst8++;p_Src8++;
size--;
}
@ -359,7 +314,7 @@ void * IO2MemCpy32(void* pDst,void* pSrc, uint32_t size)
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
*p_Dst8 = MY_GET_UINT8(*p_Src8);
*p_Dst8 = GET_UINT8(*p_Src8);
p_Dst8++;p_Src8++;
size--;
}
@ -404,7 +359,7 @@ void * IO2MemCpy32(void* pDst,void* pSrc, uint32_t size)
/* complete the left overs */
while (size--)
{
*p_Dst8 = MY_GET_UINT8(*p_Src8);
*p_Dst8 = GET_UINT8(*p_Src8);
p_Dst8++;p_Src8++;
}
@ -537,7 +492,7 @@ void * IOMemSet32(void* pDst, uint8_t val, uint32_t size)
/* align destination to 32 */
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, val);
WRITE_UINT8(*p_Dst8, val);
p_Dst8++;
size--;
}
@ -555,7 +510,7 @@ void * IOMemSet32(void* pDst, uint8_t val, uint32_t size)
p_Dst8 = (uint8_t*)(p_Dst32);
while (size--)
{
MY_WRITE_UINT8(*p_Dst8, val);
WRITE_UINT8(*p_Dst8, val);
p_Dst8++;
}

78
sys/contrib/ncsw/etc/mm.c
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,10 +30,10 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "string_ext.h"
#include "error_ext.h"
#include "std_ext.h"
#include "sprint_ext.h"
#include "part_ext.h"
#include "xx_ext.h"
@ -246,6 +246,7 @@ static t_Error AddFree(t_MM *p_MM, uint64_t base, uint64_t end)
else
p_MM->freeBlocks[i] = p_CurrB->p_Next;
XX_Free(p_CurrB);
p_CurrB = NULL;
}
break;
}
@ -575,7 +576,10 @@ static uint64_t MmGetGreaterAlignment(t_MM *p_MM, uint64_t size, uint64_t alignm
/* calls Update routine to update a lists of free blocks */
if ( CutFree ( p_MM, holdBase, holdEnd ) != E_OK )
{
XX_Free(p_NewBusyB);
return (uint64_t)(ILLEGAL_BASE);
}
/* insert the new busy block into the list of busy blocks */
AddBusy ( p_MM, p_NewBusyB );
@ -614,21 +618,30 @@ t_Error MM_Init(t_Handle *h_MM, uint64_t base, uint64_t size)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MM spinlock!"));
}
/* initializes a new memory block */
if ((p_MM->memBlocks = CreateNewBlock(base, size)) == NULL)
RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG);
/* Initializes counter of free memory to total size */
p_MM->freeMemSize = size;
/* A busy list is empty */
p_MM->busyBlocks = 0;
/*Initializes a new free block for each free list*/
/* Initializes a new memory block */
if ((p_MM->memBlocks = CreateNewBlock(base, size)) == NULL)
{
MM_Free(p_MM);
RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG);
}
/* Initializes a new free block for each free list*/
for (i=0; i <= MM_MAX_ALIGNMENT; i++)
{
newBase = MAKE_ALIGNED( base, (0x1 << i) );
newSize = size - (newBase - base);
if ((p_MM->freeBlocks[i] = CreateFreeBlock(newBase, newSize)) == NULL)
{
MM_Free(p_MM);
RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG);
}
}
*h_MM = p_MM;
@ -751,9 +764,13 @@ uint64_t MM_Get(t_Handle h_MM, uint64_t size, uint64_t alignment, char* name)
if ( CutFree ( p_MM, holdBase, holdEnd ) != E_OK )
{
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
XX_Free(p_NewBusyB);
return (uint64_t)(ILLEGAL_BASE);
}
/* Decreasing the allocated memory size from free memory size */
p_MM->freeMemSize -= size;
/* insert the new busy block into the list of busy blocks */
AddBusy ( p_MM, p_NewBusyB );
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
@ -804,9 +821,13 @@ uint64_t MM_GetForce(t_Handle h_MM, uint64_t base, uint64_t size, char* name)
if ( CutFree ( p_MM, base, base+size ) != E_OK )
{
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
XX_Free(p_NewBusyB);
return (uint64_t)(ILLEGAL_BASE);
}
/* Decreasing the allocated memory size from free memory size */
p_MM->freeMemSize -= size;
/* insert the new busy block into the list of busy blocks */
AddBusy ( p_MM, p_NewBusyB );
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
@ -889,9 +910,13 @@ uint64_t MM_GetForceMin(t_Handle h_MM, uint64_t size, uint64_t alignment, uint64
if ( CutFree( p_MM, holdBase, holdEnd ) != E_OK )
{
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
XX_Free(p_NewBusyB);
return (uint64_t)(ILLEGAL_BASE);
}
/* Decreasing the allocated memory size from free memory size */
p_MM->freeMemSize -= size;
/* insert the new busy block into the list of busy blocks */
AddBusy( p_MM, p_NewBusyB );
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
@ -942,6 +967,9 @@ uint64_t MM_Put(t_Handle h_MM, uint64_t base)
size = p_BusyB->end - p_BusyB->base;
/* Adding the deallocated memory size to free memory size */
p_MM->freeMemSize += size;
XX_Free(p_BusyB);
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
@ -958,6 +986,7 @@ uint64_t MM_PutForce(t_Handle h_MM, uint64_t base, uint64_t size)
ASSERT_COND(p_MM);
intFlags = XX_LockIntrSpinlock(p_MM->h_Spinlock);
if ( CutBusy( p_MM, base, end ) != E_OK )
{
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
@ -969,6 +998,10 @@ uint64_t MM_PutForce(t_Handle h_MM, uint64_t base, uint64_t size)
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
return (uint64_t)(0);
}
/* Adding the deallocated memory size to free memory size */
p_MM->freeMemSize += size;
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
return (size);
@ -988,6 +1021,7 @@ t_Error MM_Add(t_Handle h_MM, uint64_t base, uint64_t size)
* memory block
*/
intFlags = XX_LockIntrSpinlock(p_MM->h_Spinlock);
p_MemB = p_MM->memBlocks;
while ( p_MemB->p_Next )
{
@ -1024,6 +1058,10 @@ t_Error MM_Add(t_Handle h_MM, uint64_t base, uint64_t size)
XX_Free(p_NewMemB);
return ((t_Error)errCode);
}
/* Adding the new block size to free memory size */
p_MM->freeMemSize += size;
XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags);
return (E_OK);
@ -1077,7 +1115,17 @@ bool MM_InRange(t_Handle h_MM, uint64_t addr)
}
/*****************************************************************************/
void MM_Dump(t_Handle h_MM, void *buff)
uint64_t MM_GetFreeMemSize(t_Handle h_MM)
{
t_MM *p_MM = (t_MM*)h_MM;
ASSERT_COND(p_MM);
return p_MM->freeMemSize;
}
/*****************************************************************************/
void MM_Dump(t_Handle h_MM)
{
t_MM *p_MM = (t_MM *)h_MM;
t_FreeBlock *p_FreeB;
@ -1085,25 +1133,23 @@ void MM_Dump(t_Handle h_MM, void *buff)
int i;
p_BusyB = p_MM->busyBlocks;
Sprint(buff, "List of busy blocks:\n");
XX_Print("List of busy blocks:\n");
while (p_BusyB)
{
Sprint(buff, "\t0x%p: (%s: b=0x%lx, e=0x%lx)\n",
p_BusyB, p_BusyB->name, p_BusyB->base, p_BusyB->end );
XX_Print("\t0x%p: (%s: b=0x%llx, e=0x%llx)\n", p_BusyB, p_BusyB->name, p_BusyB->base, p_BusyB->end );
p_BusyB = p_BusyB->p_Next;
}
Sprint(buff, "\nLists of free blocks according to alignment:\n");
XX_Print("\nLists of free blocks according to alignment:\n");
for (i=0; i <= MM_MAX_ALIGNMENT; i++)
{
Sprint(buff, "%d alignment:\n", (0x1 << i));
XX_Print("%d alignment:\n", (0x1 << i));
p_FreeB = p_MM->freeBlocks[i];
while (p_FreeB)
{
Sprint(buff, "\t0x%p: (b=0x%lx, e=0x%lx)\n",
p_FreeB, p_FreeB->base, p_FreeB->end);
XX_Print("\t0x%p: (b=0x%llx, e=0x%llx)\n", p_FreeB, p_FreeB->base, p_FreeB->end);
p_FreeB = p_FreeB->p_Next;
}
Sprint(buff, "\n");
XX_Print("\n");
}
}

16
sys/contrib/ncsw/etc/mm.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/****************************************************************
*
* File: mm.h
@ -55,7 +56,7 @@
(((uint64_t)(addr) + ((align) - 1)) & (~(((uint64_t)align) - 1)))
/* t_MemBlock data stucutre defines parameters of the Memory Block */
/* t_MemBlock data structure defines parameters of the Memory Block */
typedef struct t_MemBlock
{
struct t_MemBlock *p_Next; /* Pointer to the next memory block */
@ -65,7 +66,7 @@ typedef struct t_MemBlock
} t_MemBlock;
/* t_FreeBlock data stucutre defines parameters of the Free Block */
/* t_FreeBlock data structure defines parameters of the Free Block */
typedef struct t_FreeBlock
{
struct t_FreeBlock *p_Next; /* Pointer to the next free block */
@ -75,7 +76,7 @@ typedef struct t_FreeBlock
} t_FreeBlock;
/* t_BusyBlock data stucutre defines parameters of the Busy Block */
/* t_BusyBlock data structure defines parameters of the Busy Block */
typedef struct t_BusyBlock
{
struct t_BusyBlock *p_Next; /* Pointer to the next free block */
@ -90,11 +91,14 @@ typedef struct t_BusyBlock
/* t_MM data structure defines parameters of the MM object */
typedef struct t_MM
{
t_Handle h_Spinlock;
t_MemBlock *memBlocks; /* List of memory blocks (Memory list) */
t_BusyBlock *busyBlocks; /* List of busy blocks (Busy list) */
t_FreeBlock *freeBlocks[MM_MAX_ALIGNMENT + 1];
/* Alignment lists of free blocks (Free lists) */
t_Handle h_Spinlock;
uint64_t freeMemSize; /* Total size of free memory (in bytes) */
} t_MM;

2
sys/contrib/ncsw/etc/ncsw_mem.c
View File

@ -42,6 +42,7 @@
#include "xx_ext.h"
#if 0
#define PAD_ALIGNMENT(align, x) (((x)%(align)) ? ((align)-((x)%(align))) : 0)
#define ALIGN_BLOCK(p_Block, prefixSize, alignment) \
@ -761,3 +762,4 @@ void MEM_CheckLeaks(t_Handle h_Mem)
#endif /* DEBUG_MEM_LEAKS */
#endif

26
sys/contrib/ncsw/inc/Peripherals/bm_ext.h
View File

@ -322,7 +322,7 @@ typedef struct {
uintptr_t ciBaseAddress; /**< Cache-inhibited base address (virtual) */
t_Handle h_Bm; /**< Bm Handle */
e_DpaaSwPortal swPortalId; /**< Portal id */
int irq; /**< portal interrupt line; NO_IRQ if interrupts not used */
uintptr_t irq; /**< portal interrupt line; NO_IRQ if interrupts not used */
} t_BmPortalParam;
@ -593,30 +593,6 @@ uint16_t BM_POOL_GetBufferSize(t_Handle h_BmPool);
*//***************************************************************************/
t_Handle BM_POOL_GetBufferContext(t_Handle h_BmPool, void *p_Buff);
/**************************************************************************//**
@Function BM_POOL_PhysToVirt
@Description Translates a physical address to the matching virtual address.
@Param[in] h_BmPool - A handle to a BM-pool
@Param[in] addr - The physical address to translate
@Return Virtual address.
*//***************************************************************************/
void * BM_POOL_PhysToVirt(t_Handle h_BmPool, physAddress_t addr);
/**************************************************************************//**
@Function BM_POOL_VirtToPhys
@Description Translates a virtual address to the matching physical address.
@Param[in] h_BmPool - A handle to a BM-pool
@Param[in] addr - The virtual address to translate
@Return Physical address.
*//***************************************************************************/
physAddress_t BM_POOL_VirtToPhys(t_Handle h_BmPool, void *addr);
/**************************************************************************//**
@Function BM_POOL_GetCounter

5
sys/contrib/ncsw/inc/Peripherals/crc_mac_addr_ext.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*------------------------------------------------------*/
/* */
/* File: crc_mac_addr_ext.h */

53
sys/contrib/ncsw/inc/Peripherals/dpaa_ext.h
View File

@ -1,4 +1,4 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -30,7 +30,8 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
/**************************************************************************//**
@File dpaa_ext.h
@Description DPAA Application Programming Interface.
@ -53,14 +54,29 @@
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
#include <machine/endian.h>
#define __BYTE_ORDER__ BYTE_ORDER
#define __ORDER_BIG_ENDIAN__ BIG_ENDIAN
/**************************************************************************//**
@Description Frame descriptor
*//***************************************************************************/
typedef _Packed struct t_DpaaFD {
volatile uint32_t id; /**< FD id */
volatile uint32_t addrl; /**< Data Address */
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
volatile uint8_t liodn;
volatile uint8_t bpid;
volatile uint8_t elion;
volatile uint8_t addrh;
volatile uint32_t addrl;
#else
volatile uint32_t addrl;
volatile uint8_t addrh;
volatile uint8_t elion;
volatile uint8_t bpid;
volatile uint8_t liodn;
#endif
volatile uint32_t length; /**< Frame length */
volatile uint32_t status; /**< FD status */
} _PackedType t_DpaaFD;
@ -95,25 +111,17 @@ typedef enum e_DpaaFDFormatType {
#define DPAA_FD_OFFSET_MASK 0x1ff00000 /**< FD OFFSET field mask */
#define DPAA_FD_LENGTH_MASK 0x000fffff /**< FD LENGTH field mask */
#define DPAA_FD_GET_DD(fd) ((((t_DpaaFD *)fd)->id & DPAA_FD_DD_MASK) >> (31-1)) /**< Macro to get FD DD field */
#define DPAA_FD_GET_PID(fd) (((((t_DpaaFD *)fd)->id & DPAA_FD_PID_MASK) >> (31-7)) | \
((((t_DpaaFD *)fd)->id & DPAA_FD_ELIODN_MASK) >> (31-19-6))) /**< Macro to get FD PID field */
#define DPAA_FD_GET_BPID(fd) ((((t_DpaaFD *)fd)->id & DPAA_FD_BPID_MASK) >> (31-15)) /**< Macro to get FD BPID field */
#define DPAA_FD_GET_ADDRH(fd) (((t_DpaaFD *)fd)->id & DPAA_FD_ADDRH_MASK) /**< Macro to get FD ADDRH field */
#define DPAA_FD_GET_ADDRH(fd) ((t_DpaaFD *)fd)->addrh /**< Macro to get FD ADDRH field */
#define DPAA_FD_GET_ADDRL(fd) ((t_DpaaFD *)fd)->addrl /**< Macro to get FD ADDRL field */
#define DPAA_FD_GET_PHYS_ADDR(fd) ((physAddress_t)(((uint64_t)DPAA_FD_GET_ADDRH(fd) << 32) | (uint64_t)DPAA_FD_GET_ADDRL(fd))) /**< Macro to get FD ADDR field */
#define DPAA_FD_GET_FORMAT(fd) ((((t_DpaaFD *)fd)->length & DPAA_FD_FORMAT_MASK) >> (31-2)) /**< Macro to get FD FORMAT field */
#define DPAA_FD_GET_OFFSET(fd) ((((t_DpaaFD *)fd)->length & DPAA_FD_OFFSET_MASK) >> (31-11)) /**< Macro to get FD OFFSET field */
#define DPAA_FD_GET_LENGTH(fd) (((t_DpaaFD *)fd)->length & DPAA_FD_LENGTH_MASK) /**< Macro to get FD LENGTH field */
#define DPAA_FD_GET_STATUS(fd) ((t_DpaaFD *)fd)->status /**< Macro to get FD STATUS field */
#define DPAA_FD_GET_ADDR(fd) XX_PhysToVirt(DPAA_FD_GET_PHYS_ADDR(fd))
#define DPAA_FD_GET_ADDR(fd) XX_PhysToVirt(DPAA_FD_GET_PHYS_ADDR(fd)) /**< Macro to get FD ADDR (virtual) */
#define DPAA_FD_SET_DD(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~DPAA_FD_DD_MASK) | (((val) << (31-1)) & DPAA_FD_DD_MASK ))) /**< Macro to set FD DD field */
/**< Macro to set FD PID field or LIODN offset*/
#define DPAA_FD_SET_PID(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~(DPAA_FD_PID_MASK|DPAA_FD_ELIODN_MASK)) | ((((val) << (31-7)) & DPAA_FD_PID_MASK) | ((((val)>>6) << (31-19)) & DPAA_FD_ELIODN_MASK))))
#define DPAA_FD_SET_BPID(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~DPAA_FD_BPID_MASK) | (((val) << (31-15)) & DPAA_FD_BPID_MASK))) /**< Macro to set FD BPID field */
#define DPAA_FD_SET_ADDRH(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~DPAA_FD_ADDRH_MASK) | ((val) & DPAA_FD_ADDRH_MASK))) /**< Macro to set FD ADDRH field */
#define DPAA_FD_SET_ADDRL(fd,val) ((t_DpaaFD *)fd)->addrl = (val) /**< Macro to set FD ADDRL field */
#define DPAA_FD_SET_ADDRH(fd,val) ((t_DpaaFD *)fd)->addrh = (val) /**< Macro to set FD ADDRH field */
#define DPAA_FD_SET_ADDRL(fd,val) ((t_DpaaFD *)fd)->addrl = (val) /**< Macro to set FD ADDRL field */
#define DPAA_FD_SET_ADDR(fd,val) \
do { \
uint64_t physAddr = (uint64_t)(XX_VirtToPhys(val)); \
@ -123,7 +131,7 @@ do { \
#define DPAA_FD_SET_FORMAT(fd,val) (((t_DpaaFD *)fd)->length = ((((t_DpaaFD *)fd)->length & ~DPAA_FD_FORMAT_MASK) | (((val) << (31-2))& DPAA_FD_FORMAT_MASK))) /**< Macro to set FD FORMAT field */
#define DPAA_FD_SET_OFFSET(fd,val) (((t_DpaaFD *)fd)->length = ((((t_DpaaFD *)fd)->length & ~DPAA_FD_OFFSET_MASK) | (((val) << (31-11))& DPAA_FD_OFFSET_MASK) )) /**< Macro to set FD OFFSET field */
#define DPAA_FD_SET_LENGTH(fd,val) (((t_DpaaFD *)fd)->length = (((t_DpaaFD *)fd)->length & ~DPAA_FD_LENGTH_MASK) | ((val) & DPAA_FD_LENGTH_MASK)) /**< Macro to set FD LENGTH field */
#define DPAA_FD_SET_STATUS(fd,val) ((t_DpaaFD *)fd)->status = (val) /**< Macro to set FD STATUS field */
#define DPAA_FD_SET_STATUS(fd,val) ((t_DpaaFD *)fd)->status = (val) /**< Macro to set FD STATUS field */
/* @} */
/**************************************************************************//**
@ -143,7 +151,7 @@ typedef _Packed struct t_DpaaSGTE {
*//***************************************************************************/
typedef _Packed struct t_DpaaSGT {
t_DpaaSGTE tableEntry[DPAA_NUM_OF_SG_TABLE_ENTRY];
/**< structure that hold the information about
/**< Structure that holds information about
a single S/G entry. */
} _PackedType t_DpaaSGT;
@ -151,10 +159,10 @@ typedef _Packed struct t_DpaaSGT {
@Description Compound Frame Table
*//***************************************************************************/
typedef _Packed struct t_DpaaCompTbl {
t_DpaaSGTE outputBuffInfo; /**< structure that holds the information about
t_DpaaSGTE outputBuffInfo; /**< Structure that holds information about
the compound-frame output buffer;
NOTE: this may point to a S/G table */
t_DpaaSGTE inputBuffInfo; /**< structure that holds the information about
t_DpaaSGTE inputBuffInfo; /**< Structure that holds information about
the compound-frame input buffer;
NOTE: this may point to a S/G table */
} _PackedType t_DpaaCompTbl;
@ -195,11 +203,12 @@ do { \
#define DPAA_SGTE_SET_OFFSET(sgte,val) (((t_DpaaSGTE *)sgte)->offset = ((((t_DpaaSGTE *)sgte)->offset & ~DPAA_SGTE_OFFSET_MASK) | (((val) << (31-31))& DPAA_SGTE_OFFSET_MASK) )) /**< Macro to set SGTE OFFSET field */
/* @} */
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
#define DPAA_LIODN_DONT_OVERRIDE (-1)
/** @} */ /* end of DPAA_grp group */

1146
sys/contrib/ncsw/inc/Peripherals/fm_ext.h
View File

File diff suppressed because it is too large Load Diff

356
sys/contrib/ncsw/inc/Peripherals/fm_mac_ext.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_mac_ext.h
@ -59,45 +60,51 @@
@{
*//***************************************************************************/
#define FM_MAC_NO_PFC 0xff
/**************************************************************************//**
@Description FM MAC Exceptions
*//***************************************************************************/
typedef enum e_FmMacExceptions {
e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0
,e_FM_MAC_EX_10G_MDIO_CMD_CMPL
,e_FM_MAC_EX_10G_REM_FAULT
,e_FM_MAC_EX_10G_LOC_FAULT
,e_FM_MAC_EX_10G_1TX_ECC_ER
,e_FM_MAC_EX_10G_TX_FIFO_UNFL
,e_FM_MAC_EX_10G_TX_FIFO_OVFL
,e_FM_MAC_EX_10G_TX_ER
,e_FM_MAC_EX_10G_RX_FIFO_OVFL
,e_FM_MAC_EX_10G_RX_ECC_ER
,e_FM_MAC_EX_10G_RX_JAB_FRM
,e_FM_MAC_EX_10G_RX_OVRSZ_FRM
,e_FM_MAC_EX_10G_RX_RUNT_FRM
,e_FM_MAC_EX_10G_RX_FRAG_FRM
,e_FM_MAC_EX_10G_RX_LEN_ER
,e_FM_MAC_EX_10G_RX_CRC_ER
,e_FM_MAC_EX_10G_RX_ALIGN_ER
,e_FM_MAC_EX_1G_BAB_RX
,e_FM_MAC_EX_1G_RX_CTL
,e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET
,e_FM_MAC_EX_1G_BAB_TX
,e_FM_MAC_EX_1G_TX_CTL
,e_FM_MAC_EX_1G_TX_ERR
,e_FM_MAC_EX_1G_LATE_COL
,e_FM_MAC_EX_1G_COL_RET_LMT
,e_FM_MAC_EX_1G_TX_FIFO_UNDRN
,e_FM_MAC_EX_1G_MAG_PCKT
,e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET
,e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET
,e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET
,e_FM_MAC_EX_1G_TX_DATA_ERR
,e_FM_MAC_EX_1G_RX_DATA_ERR
,e_FM_MAC_EX_1G_1588_TS_RX_ERR
,e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL
e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0 /**< 10GEC MDIO scan event interrupt */
,e_FM_MAC_EX_10G_MDIO_CMD_CMPL /**< 10GEC MDIO command completion interrupt */
,e_FM_MAC_EX_10G_REM_FAULT /**< 10GEC, mEMAC Remote fault interrupt */
,e_FM_MAC_EX_10G_LOC_FAULT /**< 10GEC, mEMAC Local fault interrupt */
,e_FM_MAC_EX_10G_1TX_ECC_ER /**< 10GEC, mEMAC Transmit frame ECC error interrupt */
,e_FM_MAC_EX_10G_TX_FIFO_UNFL /**< 10GEC, mEMAC Transmit FIFO underflow interrupt */
,e_FM_MAC_EX_10G_TX_FIFO_OVFL /**< 10GEC, mEMAC Transmit FIFO overflow interrupt */
,e_FM_MAC_EX_10G_TX_ER /**< 10GEC Transmit frame error interrupt */
,e_FM_MAC_EX_10G_RX_FIFO_OVFL /**< 10GEC, mEMAC Receive FIFO overflow interrupt */
,e_FM_MAC_EX_10G_RX_ECC_ER /**< 10GEC, mEMAC Receive frame ECC error interrupt */
,e_FM_MAC_EX_10G_RX_JAB_FRM /**< 10GEC Receive jabber frame interrupt */
,e_FM_MAC_EX_10G_RX_OVRSZ_FRM /**< 10GEC Receive oversized frame interrupt */
,e_FM_MAC_EX_10G_RX_RUNT_FRM /**< 10GEC Receive runt frame interrupt */
,e_FM_MAC_EX_10G_RX_FRAG_FRM /**< 10GEC Receive fragment frame interrupt */
,e_FM_MAC_EX_10G_RX_LEN_ER /**< 10GEC Receive payload length error interrupt */
,e_FM_MAC_EX_10G_RX_CRC_ER /**< 10GEC Receive CRC error interrupt */
,e_FM_MAC_EX_10G_RX_ALIGN_ER /**< 10GEC Receive alignment error interrupt */
,e_FM_MAC_EX_1G_BAB_RX /**< dTSEC Babbling receive error */
,e_FM_MAC_EX_1G_RX_CTL /**< dTSEC Receive control (pause frame) interrupt */
,e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET /**< dTSEC Graceful transmit stop complete */
,e_FM_MAC_EX_1G_BAB_TX /**< dTSEC Babbling transmit error */
,e_FM_MAC_EX_1G_TX_CTL /**< dTSEC Transmit control (pause frame) interrupt */
,e_FM_MAC_EX_1G_TX_ERR /**< dTSEC Transmit error */
,e_FM_MAC_EX_1G_LATE_COL /**< dTSEC Late collision */
,e_FM_MAC_EX_1G_COL_RET_LMT /**< dTSEC Collision retry limit */
,e_FM_MAC_EX_1G_TX_FIFO_UNDRN /**< dTSEC Transmit FIFO underrun */
,e_FM_MAC_EX_1G_MAG_PCKT /**< dTSEC Magic Packet detection */
,e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET /**< dTSEC MII management read completion */
,e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET /**< dTSEC MII management write completion */
,e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET /**< dTSEC Graceful receive stop complete */
,e_FM_MAC_EX_1G_TX_DATA_ERR /**< dTSEC Internal data error on transmit */
,e_FM_MAC_EX_1G_RX_DATA_ERR /**< dTSEC Internal data error on receive */
,e_FM_MAC_EX_1G_1588_TS_RX_ERR /**< dTSEC Time-Stamp Receive Error */
,e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL /**< dTSEC MIB counter overflow */
,e_FM_MAC_EX_TS_FIFO_ECC_ERR /**< mEMAC Time-stamp FIFO ECC error interrupt;
not supported on T4240/B4860 rev1 chips */
,e_FM_MAC_EX_MAGIC_PACKET_INDICATION = e_FM_MAC_EX_1G_MAG_PCKT
/**< mEMAC Magic Packet Indication Interrupt */
} e_FmMacExceptions;
/**************************************************************************//**
@ -105,11 +112,26 @@ typedef enum e_FmMacExceptions {
*//***************************************************************************/
typedef enum e_FmMacStatisticsLevel {
e_FM_MAC_NONE_STATISTICS = 0, /**< No statistics */
e_FM_MAC_PARTIAL_STATISTICS, /**< Only error counters are available. Optimized for performance */
e_FM_MAC_FULL_STATISTICS /**< All counters available. Not optimized for performance */
e_FM_MAC_PARTIAL_STATISTICS, /**< Only error counters are available; Optimized for performance */
e_FM_MAC_FULL_STATISTICS /**< All counters available; Not optimized for performance */
} e_FmMacStatisticsLevel;
#if (DPAA_VERSION >= 11)
/**************************************************************************//**
@Description Priority Flow Control Parameters
*//***************************************************************************/
typedef struct t_FmMacPfcParams {
bool pfcEnable; /**< Enable/Disable PFC */
uint16_t pauseQuanta[FM_MAX_NUM_OF_PFC_PRIORITIES]; /**< Pause Quanta per priority to be sent in a pause frame. Each quanta represents a 512 bit-times*/
uint16_t pauseThresholdQuanta[FM_MAX_NUM_OF_PFC_PRIORITIES];/**< Pause threshold per priority, when timer passes this threshold time a PFC frames is sent again if the port is still congested or BM pool in depletion*/
} t_FmMacPfcParams;
#endif /* (DPAA_VERSION >= 11) */
/**************************************************************************//**
@Function t_FmMacExceptionCallback
@ -119,7 +141,6 @@ typedef enum e_FmMacStatisticsLevel {
@Param[in] exceptions - The exception that occurred
@Return void.
*//***************************************************************************/
typedef void (t_FmMacExceptionCallback)(t_Handle h_App, e_FmMacExceptions exceptions);
@ -140,17 +161,20 @@ typedef struct t_FmMacStatistics {
/* */
uint64_t eStatFragments; /**< Total number of packets that were less than 64 octets long with a wrong CRC.*/
uint64_t eStatJabbers; /**< Total number of packets longer than valid maximum length octets */
uint64_t eStatsDropEvents; /**< number of dropped packets due to internal errors of the MAC Client. */
uint64_t eStatsDropEvents; /**< number of dropped packets due to internal errors of the MAC Client (during receive). */
uint64_t eStatCRCAlignErrors; /**< Incremented when frames of correct length but with CRC error are received.*/
uint64_t eStatUndersizePkts; /**< Total number of packets that were less than 64 octets long with a good CRC.*/
uint64_t eStatOversizePkts; /**< T,B.D*/
uint64_t eStatUndersizePkts; /**< Incremented for frames under 64 bytes with a valid FCS and otherwise well formed;
This count does not include range length errors */
uint64_t eStatOversizePkts; /**< Incremented for frames which exceed 1518 (non VLAN) or 1522 (VLAN) and contains
a valid FCS and otherwise well formed */
/* Pause */
uint64_t teStatPause; /**< Pause MAC Control received */
uint64_t reStatPause; /**< Pause MAC Control sent */
/* MIB II */
uint64_t ifInOctets; /**< Total number of byte received. */
uint64_t ifInPkts; /**< Total number of packets received.*/
uint64_t ifInUcastPkts; /**< Total number of unicast frame received;
NOTE: this counter is not supported on dTSEC MAC */
uint64_t ifInMcastPkts; /**< Total number of multicast frame received*/
uint64_t ifInBcastPkts; /**< Total number of broadcast frame received */
uint64_t ifInDiscards; /**< Frames received, but discarded due to problems within the MAC RX. */
@ -162,6 +186,8 @@ typedef struct t_FmMacStatistics {
- The dedicated Error Code (0xfe, not a code error) was received */
uint64_t ifOutOctets; /**< Total number of byte sent. */
uint64_t ifOutPkts; /**< Total number of packets sent .*/
uint64_t ifOutUcastPkts; /**< Total number of unicast frame sent;
NOTE: this counter is not supported on dTSEC MAC */
uint64_t ifOutMcastPkts; /**< Total number of multicast frame sent */
uint64_t ifOutBcastPkts; /**< Total number of multicast frame sent */
uint64_t ifOutDiscards; /**< Frames received, but discarded due to problems within the MAC TX N/A!.*/
@ -173,7 +199,7 @@ typedef struct t_FmMacStatistics {
/**************************************************************************//**
@Group FM_mac_init_grp Initialization Unit
@Group FM_mac_init_grp FM MAC Initialization Unit
@Description FM MAC Initialization Unit
@ -186,8 +212,24 @@ typedef struct t_FmMacStatistics {
typedef struct t_FmMacParams {
uintptr_t baseAddr; /**< Base of memory mapped FM MAC registers */
t_EnetAddr addr; /**< MAC address of device; First octet is sent first */
uint8_t macId; /**< MAC ID <dTSEC 0-3> <10G 0> */
e_EnetMode enetMode; /**< Ethernet operation mode (MAC-PHY interface and speed) */
uint8_t macId; /**< MAC ID;
numbering of dTSEC and 1G-mEMAC:
0 - FM_MAX_NUM_OF_1G_MACS;
numbering of 10G-MAC (TGEC) and 10G-mEMAC:
0 - FM_MAX_NUM_OF_10G_MACS */
e_EnetMode enetMode; /**< Ethernet operation mode (MAC-PHY interface and speed);
Note that the speed should indicate the maximum rate that
this MAC should support rather than the actual speed;
i.e. user should use the FM_MAC_AdjustLink() routine to
provide accurate speed;
In case of mEMAC RGMII mode, the MAC is configured to RGMII
automatic mode, where actual speed/duplex mode information
is provided by PHY automatically in-band; FM_MAC_AdjustLink()
function should be used to switch to manual RGMII speed/duplex mode
configuration if RGMII PHY doesn't support in-band status signaling;
In addition, in mEMAC, in case where user is using the higher MACs
(i.e. the MACs that should support 10G), user should pass here
speed=10000 even if the interface is not allowing that (e.g. SGMII). */
t_Handle h_Fm; /**< A handle to the FM object this port related to */
int mdioIrq; /**< MDIO exceptions interrupt source - not valid for all
MACs; MUST be set to 'NO_IRQ' for MACs that don't have
@ -215,7 +257,7 @@ typedef struct t_FmMacParams {
@Retval Handle to FM MAC object, or NULL for Failure.
*//***************************************************************************/
t_Handle FM_MAC_Config (t_FmMacParams *p_FmMacParam);
t_Handle FM_MAC_Config(t_FmMacParams *p_FmMacParam);
/**************************************************************************//**
@Function FM_MAC_Init
@ -226,7 +268,7 @@ t_Handle FM_MAC_Config (t_FmMacParams *p_FmMacParam);
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_Init (t_Handle h_FmMac);
t_Error FM_MAC_Init(t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_Free
@ -239,11 +281,11 @@ t_Error FM_MAC_Init (t_Handle h_FmMac);
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_Free (t_Handle h_FmMac);
t_Error FM_MAC_Free(t_Handle h_FmMac);
/**************************************************************************//**
@Group FM_mac_advanced_init_grp Advanced Configuration Unit
@Group FM_mac_advanced_init_grp FM MAC Advanced Configuration Unit
@Description Configuration functions used to change default values.
@ -254,7 +296,7 @@ t_Error FM_MAC_Free (t_Handle h_FmMac);
@Function FM_MAC_ConfigResetOnInit
@Description Tell the driver whether to reset the FM MAC before initialization or
not. It changes the default configuration [FALSE].
not. It changes the default configuration [DEFAULT_resetOnInit].
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable When TRUE, FM will be reset before any initialization.
@ -263,7 +305,7 @@ t_Error FM_MAC_Free (t_Handle h_FmMac);
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigResetOnInit (t_Handle h_FmMac, bool enable);
t_Error FM_MAC_ConfigResetOnInit(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigLoopback
@ -277,12 +319,12 @@ t_Error FM_MAC_ConfigResetOnInit (t_Handle h_FmMac, bool enable);
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigLoopback (t_Handle h_FmMac, bool enable);
t_Error FM_MAC_ConfigLoopback(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigMaxFrameLength
@Description Setup maximum Frame Length
@Description Setup maximum Rx Frame Length (in 1G MAC, effects also Tx)
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] newVal MAX Frame length
@ -291,12 +333,12 @@ t_Error FM_MAC_ConfigLoopback (t_Handle h_FmMac, bool enable);
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigMaxFrameLength (t_Handle h_FmMac, uint16_t newVal);
t_Error FM_MAC_ConfigMaxFrameLength(t_Handle h_FmMac, uint16_t newVal);
/**************************************************************************//**
@Function FM_MAC_ConfigWan
@Description ENABLE WAN mode in 10G MAC
@Description ENABLE WAN mode in 10G-MAC
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@ -305,7 +347,7 @@ t_Error FM_MAC_ConfigMaxFrameLength (t_Handle h_FmMac, uint16_t newVal);
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigWan (t_Handle h_FmMac, bool enable);
t_Error FM_MAC_ConfigWan(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigPadAndCrc
@ -318,8 +360,11 @@ t_Error FM_MAC_ConfigWan (t_Handle h_FmMac, bool enable);
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
Not supported on 10G-MAC (i.e. CRC & PAD are added automatically
by HW); on mEMAC, this routine supports only PAD (i.e. CRC is
added automatically by HW).
*//***************************************************************************/
t_Error FM_MAC_ConfigPadAndCrc (t_Handle h_FmMac, bool enable);
t_Error FM_MAC_ConfigPadAndCrc(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigHalfDuplex
@ -333,12 +378,26 @@ t_Error FM_MAC_ConfigPadAndCrc (t_Handle h_FmMac, bool enable);
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigHalfDuplex (t_Handle h_FmMac, bool enable);
t_Error FM_MAC_ConfigHalfDuplex(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigTbiPhyAddr
@Description Configures the address of internal TBI PHY.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] newVal TBI PHY address (1-31).
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigTbiPhyAddr(t_Handle h_FmMac, uint8_t newVal);
/**************************************************************************//**
@Function FM_MAC_ConfigLengthCheck
@Description Configure thef frame length checking.
@Description Configure the frame length checking.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@ -347,7 +406,7 @@ t_Error FM_MAC_ConfigHalfDuplex (t_Handle h_FmMac, bool enable);
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigLengthCheck (t_Handle h_FmMac, bool enable);
t_Error FM_MAC_ConfigLengthCheck(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigException
@ -358,7 +417,6 @@ t_Error FM_MAC_ConfigLengthCheck (t_Handle h_FmMac, bool enable);
@Param[in] ex Type of the desired exceptions
@Param[in] enable TRUE to enable the specified exception, FALSE to disable it.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
@ -373,7 +431,7 @@ t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac);
/**************************************************************************//**
@Group FM_mac_runtime_control_grp Runtime Control Unit
@Group FM_mac_runtime_control_grp FM MAC Runtime Control Unit
@Description FM MAC Runtime control unit API functions, definitions and enums.
@ -392,7 +450,7 @@ t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac);
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Enable (t_Handle h_FmMac, e_CommMode mode);
t_Error FM_MAC_Enable(t_Handle h_FmMac, e_CommMode mode);
/**************************************************************************//**
@Function FM_MAC_Disable
@ -406,7 +464,20 @@ t_Error FM_MAC_Enable (t_Handle h_FmMac, e_CommMode mode);
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Disable (t_Handle h_FmMac, e_CommMode mode);
t_Error FM_MAC_Disable(t_Handle h_FmMac, e_CommMode mode);
/**************************************************************************//**
@Function FM_MAC_Resume
@Description Re-init the MAC after suspend
@Param[in] h_FmMac A handle to a FM MAC Module.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Resume(t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_MAC_Enable1588TimeStamp
@ -437,56 +508,108 @@ t_Error FM_MAC_Disable1588TimeStamp(t_Handle h_Fm);
/**************************************************************************//**
@Function FM_MAC_SetTxAutoPauseFrames
@Description Enable/Disable transmition of Pause-Frames.
@Description Enable/Disable transmission of Pause-Frames.
The routine changes the default configuration [DEFAULT_TX_PAUSE_TIME].
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] pauseTime Pause quanta value used with transmitted pause frames.
Each quanta represents a 512 bit-times; Note that '0'
as an input here will be used as disabling the
transmission of the pause-frames.
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] pauseTime - Pause quanta value used with transmitted pause frames.
Each quanta represents a 512 bit-times; Note that '0'
as an input here will be used as disabling the
transmission of the pause-frames.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetTxAutoPauseFrames (t_Handle h_FmMac, uint16_t pauseTime);
t_Error FM_MAC_SetTxAutoPauseFrames(t_Handle h_FmMac,
uint16_t pauseTime);
/**************************************************************************//**
@Function FM_MAC_SetTxPauseFrames
@Description Enable/Disable transmission of Pause-Frames.
The routine changes the default configuration:
pause-time - [DEFAULT_TX_PAUSE_TIME]
threshold-time - [0]
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] priority - the PFC class of service; use 'FM_MAC_NO_PFC'
to indicate legacy pause support (i.e. no PFC).
@Param[in] pauseTime - Pause quanta value used with transmitted pause frames.
Each quanta represents a 512 bit-times;
Note that '0' as an input here will be used as disabling the
transmission of the pause-frames.
@Param[in] threshTime - Pause Threshold equanta value used by the MAC to retransmit pause frame.
if the situation causing a pause frame to be sent didn't finish when the timer
reached the threshold quanta, the MAC will retransmit the pause frame.
Each quanta represents a 512 bit-times.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
In order for PFC to work properly the user must configure
TNUM-aging in the tx-port it is recommended that pre-fetch and
rate limit in the tx port should be disabled;
PFC is supported only on new mEMAC; i.e. in MACs that don't have
PFC support (10G-MAC and dTSEC), user should use 'FM_MAC_NO_PFC'
in the 'priority' field.
*//***************************************************************************/
t_Error FM_MAC_SetTxPauseFrames(t_Handle h_FmMac,
uint8_t priority,
uint16_t pauseTime,
uint16_t threshTime);
/**************************************************************************//**
@Function FM_MAC_SetRxIgnorePauseFrames
@Description Enable/Disable ignoring of Pause-Frames.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] en boolean indicates whether to ignore the incoming pause
frames or not.
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] en - boolean indicates whether to ignore the incoming pause
frames or not.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetRxIgnorePauseFrames (t_Handle h_FmMac, bool en);
t_Error FM_MAC_SetRxIgnorePauseFrames(t_Handle h_FmMac, bool en);
/**************************************************************************//**
@Function FM_MAC_SetWakeOnLan
@Description Enable/Disable Wake On Lan support
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] en - boolean indicates whether to enable Wake On Lan
support or not.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetWakeOnLan(t_Handle h_FmMac, bool en);
/**************************************************************************//**
@Function FM_MAC_ResetCounters
@Description reset all statistics counters
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ResetCounters (t_Handle h_FmMac);
t_Error FM_MAC_ResetCounters(t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_MAC_SetException
@Description Enable/Disable a specific Exception
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] ex Type of the desired exceptions
@Param[in] enable TRUE to enable the specified exception, FALSE to disable it.
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] ex - Type of the desired exceptions
@Param[in] enable - TRUE to enable the specified exception, FALSE to disable it.
@Return E_OK on success; Error code otherwise.
@ -499,35 +622,36 @@ t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
@Function FM_MAC_SetStatistics
@Description Define Statistics level.
Where applicable, the routine also enables the MIB counters
overflow interrupt in order to keep counters accurate
and account for overflows.
Where applicable, the routine also enables the MIB counters
overflow interrupt in order to keep counters accurate
and account for overflows.
This routine is relevant only for dTSEC.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] statisticsLevel Full statistics level provides all standard counters but may
reduce performance. Partial statistics provides only special
event counters (errors etc.). If selected, regular counters (such as
byte/packet) will be invalid and will return -1.
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] statisticsLevel - Full statistics level provides all standard counters but may
reduce performance. Partial statistics provides only special
event counters (errors etc.). If selected, regular counters (such as
byte/packet) will be invalid and will return -1.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetStatistics (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel);
t_Error FM_MAC_SetStatistics(t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel);
/**************************************************************************//**
@Function FM_MAC_GetStatistics
@Description get all statistics counters
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] p_Statistics Staructure with statistics
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] p_Statistics - Structure with statistics
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_Init().
*//***************************************************************************/
t_Error FM_MAC_GetStatistics (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics);
t_Error FM_MAC_GetStatistics(t_Handle h_FmMac, t_FmMacStatistics *p_Statistics);
/**************************************************************************//**
@Function FM_MAC_ModifyMacAddr
@ -541,7 +665,7 @@ t_Error FM_MAC_GetStatistics (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics)
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ModifyMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error FM_MAC_ModifyMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_AddHashMacAddr
@ -556,7 +680,7 @@ t_Error FM_MAC_ModifyMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
@Cautions Allowed only following FM_MAC_Init(). It is a filter only address.
@Cautions Some address need to be filterd out in upper FM blocks.
*//***************************************************************************/
t_Error FM_MAC_AddHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error FM_MAC_AddHashMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_RemoveHashMacAddr
@ -570,7 +694,7 @@ t_Error FM_MAC_AddHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_RemoveHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error FM_MAC_RemoveHashMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_AddExactMatchMacAddr
@ -585,7 +709,7 @@ t_Error FM_MAC_RemoveHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_AddExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error FM_MAC_AddExactMatchMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_RemovelExactMatchMacAddr
@ -599,7 +723,7 @@ t_Error FM_MAC_AddExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_RemovelExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error FM_MAC_RemovelExactMatchMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_SetPromiscuous
@ -613,22 +737,45 @@ t_Error FM_MAC_RemovelExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAdd
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetPromiscuous (t_Handle h_FmMac, bool enable);
t_Error FM_MAC_SetPromiscuous(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_AdjustLink
@Description Adjusts the Ethernet link with new speed/duplex setup.
This routine is relevant for dTSEC and mEMAC.
In case of mEMAC, this routine is also used for manual
re-configuration of RGMII speed and duplex mode for
RGMII PHYs not supporting in-band status information
to MAC.
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] speed - Ethernet speed.
@Param[in] fullDuplex - TRUE for Full-Duplex mode;
FALSE for Half-Duplex mode.
@Param[in] fullDuplex - TRUE for full-duplex mode;
FALSE for half-duplex mode.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex);
/**************************************************************************//**
@Function FM_MAC_RestartAutoneg
@Description Restarts the auto-negotiation process.
When auto-negotiation process is invoked under traffic the
auto-negotiation process between the internal SGMII PHY and the
external PHY does not always complete successfully. Calling this
function will restart the auto-negotiation process that will end
successfully. It is recommended to call this function after issuing
auto-negotiation restart command to the Eth Phy.
This routine is relevant only for dTSEC.
@Param[in] h_FmMac - A handle to a FM Module.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_RestartAutoneg(t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_MAC_GetId
@ -641,7 +788,7 @@ t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex);
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_GetId (t_Handle h_FmMac, uint32_t *p_MacId);
t_Error FM_MAC_GetId(t_Handle h_FmMac, uint32_t *p_MacId);
/**************************************************************************//**
@Function FM_MAC_GetVesrion
@ -655,7 +802,7 @@ t_Error FM_MAC_GetId (t_Handle h_FmMac, uint32_t *p_MacId);
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_GetVesrion (t_Handle h_FmMac, uint32_t *p_MacVresion);
t_Error FM_MAC_GetVesrion(t_Handle h_FmMac, uint32_t *p_MacVresion);
/**************************************************************************//**
@Function FM_MAC_MII_WritePhyReg
@ -671,7 +818,7 @@ t_Error FM_MAC_GetVesrion (t_Handle h_FmMac, uint32_t *p_MacVresion);
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_MII_WritePhyReg (t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error FM_MAC_MII_WritePhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data);
/**************************************************************************//**
@Function FM_MAC_MII_ReadPhyReg
@ -709,5 +856,4 @@ t_Error FM_MAC_DumpRegs(t_Handle h_FmMac);
/** @} */ /* end of FM_grp group */
#endif /* __FM_MAC_EXT_H */

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sys/contrib/ncsw/inc/Peripherals/fm_muram_ext.h
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@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_muram_ext.h
@ -60,7 +61,7 @@
*//***************************************************************************/
/**************************************************************************//**
@Group FM_muram_init_grp FM MURAM Initialization
@Group FM_muram_init_grp FM MURAM Initialization Unit
@Description FM MURAM initialization API functions, definitions and enums
@ -103,7 +104,7 @@ t_Error FM_MURAM_Free(t_Handle h_FmMuram);
/**************************************************************************//**
@Group FM_muram_ctrl_grp FM MURAM Control
@Group FM_muram_ctrl_grp FM MURAM Control Unit
@Description FM MURAM control API functions, definitions and enums
@ -149,6 +150,17 @@ void * FM_MURAM_AllocMemForce(t_Handle h_FmMuram, uint64_t base, uint32_t size)
*//***************************************************************************/
t_Error FM_MURAM_FreeMem(t_Handle h_FmMuram, void *ptr);
/**************************************************************************//**
@Function FM_MURAM_GetFreeMemSize
@Description Returns the size (in bytes) of free MURAM memory.
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Return Free MURAM memory size in bytes.
*//***************************************************************************/
uint64_t FM_MURAM_GetFreeMemSize(t_Handle h_FmMuram);
/** @} */ /* end of FM_muram_ctrl_grp group */
/** @} */ /* end of FM_muram_grp group */
/** @} */ /* end of FM_grp group */

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sys/contrib/ncsw/inc/Peripherals/fm_port_ext.h
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71
sys/contrib/ncsw/inc/Peripherals/fm_rtc_ext.h
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@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_rtc_ext.h
@ -44,7 +45,7 @@
#include "error_ext.h"
#include "std_ext.h"
#include "fsl_fman_rtc.h"
/**************************************************************************//**
@ -76,8 +77,8 @@
*//***************************************************************************/
typedef enum e_FmRtcAlarmPolarity
{
e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH, /**< Active-high output polarity */
e_FM_RTC_ALARM_POLARITY_ACTIVE_LOW /**< Active-low output polarity */
e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH = E_FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH, /**< Active-high output polarity */
e_FM_RTC_ALARM_POLARITY_ACTIVE_LOW = E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW /**< Active-low output polarity */
} e_FmRtcAlarmPolarity;
/**************************************************************************//**
@ -85,8 +86,8 @@ typedef enum e_FmRtcAlarmPolarity
*//***************************************************************************/
typedef enum e_FmRtcTriggerPolarity
{
e_FM_RTC_TRIGGER_ON_RISING_EDGE, /**< Trigger on rising edge */
e_FM_RTC_TRIGGER_ON_FALLING_EDGE /**< Trigger on falling edge */
e_FM_RTC_TRIGGER_ON_RISING_EDGE = E_FMAN_RTC_TRIGGER_ON_RISING_EDGE, /**< Trigger on rising edge */
e_FM_RTC_TRIGGER_ON_FALLING_EDGE = E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE /**< Trigger on falling edge */
} e_FmRtcTriggerPolarity;
/**************************************************************************//**
@ -94,9 +95,9 @@ typedef enum e_FmRtcTriggerPolarity
*//***************************************************************************/
typedef enum e_FmSrcClock
{
e_FM_RTC_SOURCE_CLOCK_EXTERNAL, /**< external high precision timer reference clock */
e_FM_RTC_SOURCE_CLOCK_SYSTEM, /**< MAC system clock */
e_FM_RTC_SOURCE_CLOCK_OSCILATOR /**< RTC clock oscilator */
e_FM_RTC_SOURCE_CLOCK_EXTERNAL = E_FMAN_RTC_SOURCE_CLOCK_EXTERNAL, /**< external high precision timer reference clock */
e_FM_RTC_SOURCE_CLOCK_SYSTEM = E_FMAN_RTC_SOURCE_CLOCK_SYSTEM, /**< MAC system clock */
e_FM_RTC_SOURCE_CLOCK_OSCILATOR = E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR /**< RTC clock oscilator */
}e_FmSrcClk;
/**************************************************************************//**
@ -169,7 +170,7 @@ t_Error FM_RTC_Free(t_Handle h_FmRtc);
@Function FM_RTC_ConfigPeriod
@Description Configures the period of the timestamp if different than
default [1000].
default [DEFAULT_clockPeriod].
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] period - Period in nano-seconds.
@ -201,7 +202,7 @@ t_Error FM_RTC_ConfigSourceClock(t_Handle h_FmRtc,
@Function FM_RTC_ConfigPulseRealignment
@Description Configures the RTC to automatic FIPER pulse realignment in
response to timer adjustments [FALSE]
response to timer adjustments [DEFAULT_pulseRealign]
In this mode, the RTC clock is identical to the source clock.
This feature can be useful when the system contains an external
@ -220,7 +221,7 @@ t_Error FM_RTC_ConfigPulseRealignment(t_Handle h_FmRtc, bool enable);
@Function FM_RTC_ConfigFrequencyBypass
@Description Configures the RTC to bypass the frequency compensation
mechanism. [FALSE]
mechanism. [DEFAULT_bypass]
In this mode, the RTC clock is identical to the source clock.
This feature can be useful when the system contains an external
@ -240,7 +241,7 @@ t_Error FM_RTC_ConfigFrequencyBypass(t_Handle h_FmRtc, bool enabled);
@Function FM_RTC_ConfigInvertedInputClockPhase
@Description Configures the RTC to invert the source clock phase on input.
[FALSE]
[DEFAULT_invertInputClkPhase]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] inverted - TRUE to invert the source clock phase on input.
@ -256,7 +257,7 @@ t_Error FM_RTC_ConfigInvertedInputClockPhase(t_Handle h_FmRtc, bool inverted);
@Function FM_RTC_ConfigInvertedOutputClockPhase
@Description Configures the RTC to invert the output clock phase.
[FALSE]
[DEFAULT_invertOutputClkPhase]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] inverted - TRUE to invert the output clock phase.
@ -272,7 +273,7 @@ t_Error FM_RTC_ConfigInvertedOutputClockPhase(t_Handle h_FmRtc, bool inverted);
@Function FM_RTC_ConfigOutputClockDivisor
@Description Configures the divisor for generating the output clock from
the RTC clock. [0x00000002]
the RTC clock. [DEFAULT_outputClockDivisor]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] divisor - Divisor for generation of the output clock.
@ -287,7 +288,7 @@ t_Error FM_RTC_ConfigOutputClockDivisor(t_Handle h_FmRtc, uint16_t divisor);
@Function FM_RTC_ConfigAlarmPolarity
@Description Configures the polarity (active-high/active-low) of a specific
alarm signal. [e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH]
alarm signal. [DEFAULT_alarmPolarity]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] alarmId - Alarm ID.
@ -305,7 +306,7 @@ t_Error FM_RTC_ConfigAlarmPolarity(t_Handle h_FmRtc,
@Function FM_RTC_ConfigExternalTriggerPolarity
@Description Configures the polarity (rising/falling edge) of a specific
external trigger signal. [e_FM_RTC_TRIGGER_ON_FALLING_EDGE]
external trigger signal. [DEFAULT_triggerPolarity]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] triggerId - Trigger ID.
@ -540,11 +541,11 @@ t_Error FM_RTC_GetCurrentTime(t_Handle h_FmRtc, uint64_t *p_Ts);
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_SetCurrentTime(t_Handle h_FmRtc, uint64_t ts);
/**************************************************************************//**
@Function FM_RTC_GetFreqCompensation
@Description TODO
@Description Retrieves the frequency compensation value
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[out] p_Compensation - A pointer to the returned value of compensation.
@ -558,10 +559,10 @@ t_Error FM_RTC_GetFreqCompensation(t_Handle h_FmRtc, uint32_t *p_Compensation);
/**************************************************************************//**
@Function FM_RTC_SetFreqCompensation
@Description TODO
@Description Sets a new frequency compensation value.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] freqCompensation - the new desired compensation value to be set.
@Param[in] freqCompensation - The new frequency compensation value to set.
@Return E_OK on success; Error code otherwise.
@ -569,6 +570,32 @@ t_Error FM_RTC_GetFreqCompensation(t_Handle h_FmRtc, uint32_t *p_Compensation);
*//***************************************************************************/
t_Error FM_RTC_SetFreqCompensation(t_Handle h_FmRtc, uint32_t freqCompensation);
#ifdef CONFIG_PTP_1588_CLOCK_DPAA
/**************************************************************************//**
*@Function FM_RTC_EnableInterrupt
*
*@Description Enable interrupt of FM RTC.
*
*@Param[in] h_FmRtc - Handle to FM RTC object.
*@Param[in] events - Interrupt events.
*
*@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_RTC_EnableInterrupt(t_Handle h_FmRtc, uint32_t events);
/**************************************************************************//**
*@Function FM_RTC_DisableInterrupt
*
*@Description Disable interrupt of FM RTC.
*
*@Param[in] h_FmRtc - Handle to FM RTC object.
*@Param[in] events - Interrupt events.
*
*@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_RTC_DisableInterrupt(t_Handle h_FmRtc, uint32_t events);
#endif
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
/**************************************************************************//**
@Function FM_RTC_DumpRegs

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sys/contrib/ncsw/inc/Peripherals/fm_vsp_ext.h Normal file
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@ -0,0 +1,411 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_vsp_ext.h
@Description FM Virtual Storage-Profile ...
*//***************************************************************************/
#ifndef __FM_VSP_EXT_H
#define __FM_VSP_EXT_H
#include "std_ext.h"
#include "error_ext.h"
#include "string_ext.h"
#include "debug_ext.h"
#include "fm_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_VSP_grp FM Virtual-Storage-Profile
@Description FM Virtual-Storage-Profile API
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_VSP_init_grp FM VSP Initialization Unit
@Description FM VSP initialization API.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Virtual Storage Profile
*//***************************************************************************/
typedef struct t_FmVspParams {
t_Handle h_Fm; /**< A handle to the FM object this VSP related to */
t_FmExtPools extBufPools; /**< Which external buffer pools are used
(up to FM_PORT_MAX_NUM_OF_EXT_POOLS), and their sizes.
parameter associated with Rx / OP port */
uint16_t liodnOffset; /**< VSP's LIODN offset */
struct {
e_FmPortType portType; /**< Port type */
uint8_t portId; /**< Port Id - relative to type */
} portParams;
uint8_t relativeProfileId; /**< VSP Id - relative to VSP's range
defined in relevant FM object */
} t_FmVspParams;
/**************************************************************************//**
@Function FM_VSP_Config
@Description Creates descriptor for the FM VSP module.
The routine returns a handle (descriptor) to the FM VSP object.
This descriptor must be passed as first parameter to all other
FM VSP function calls.
No actual initialization or configuration of FM hardware is
done by this routine.
@Param[in] p_FmVspParams Pointer to data structure of parameters
@Retval Handle to FM VSP object, or NULL for Failure.
*//***************************************************************************/
t_Handle FM_VSP_Config(t_FmVspParams *p_FmVspParams);
/**************************************************************************//**
@Function FM_VSP_Init
@Description Initializes the FM VSP module
@Param[in] h_FmVsp - FM VSP module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_VSP_Init(t_Handle h_FmVsp);
/**************************************************************************//**
@Function FM_VSP_Free
@Description Frees all resources that were assigned to FM VSP module.
Calling this routine invalidates the descriptor.
@Param[in] h_FmVsp - FM VSP module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_VSP_Free(t_Handle h_FmVsp);
/**************************************************************************//**
@Group FM_VSP_adv_config_grp FM VSP Advanced Configuration Unit
@Description FM VSP advanced configuration functions.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_VSP_ConfigBufferPrefixContent
@Description Defines the structure, size and content of the application buffer.
The prefix will
In VSPs defined for Tx ports, if 'passPrsResult', the application
should set a value to their offsets in the prefix of
the FM will save the first 'privDataSize', than,
depending on 'passPrsResult' and 'passTimeStamp', copy parse result
and timeStamp, and the packet itself (in this order), to the
application buffer, and to offset.
Calling this routine changes the buffer margins definitions
in the internal driver data base from its default
configuration: Data size: [DEFAULT_FM_SP_bufferPrefixContent_privDataSize]
Pass Parser result: [DEFAULT_FM_SP_bufferPrefixContent_passPrsResult].
Pass timestamp: [DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp].
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in,out] p_FmBufferPrefixContent A structure of parameters describing the
structure of the buffer.
Out parameter: Start margin - offset
of data from start of external buffer.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigBufferPrefixContent(t_Handle h_FmVsp,
t_FmBufferPrefixContent *p_FmBufferPrefixContent);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaSwapData
@Description Calling this routine changes the DMA swap data parameter
in the internal driver data base from its default
configuration [DEFAULT_FM_SP_dmaSwapData]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] swapData New selection
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaSwapData(t_Handle h_FmVsp, e_FmDmaSwapOption swapData);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaIcCacheAttr
@Description Calling this routine changes the internal context cache
attribute parameter in the internal driver data base
from its default configuration [DEFAULT_FM_SP_dmaIntContextCacheAttr]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] intContextCacheAttr New selection
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaIcCacheAttr(t_Handle h_FmVsp,
e_FmDmaCacheOption intContextCacheAttr);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaHdrAttr
@Description Calling this routine changes the header cache
attribute parameter in the internal driver data base
from its default configuration [DEFAULT_FM_SP_dmaHeaderCacheAttr]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] headerCacheAttr New selection
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaHdrAttr(t_Handle h_FmVsp, e_FmDmaCacheOption headerCacheAttr);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaScatterGatherAttr
@Description Calling this routine changes the scatter gather cache
attribute parameter in the internal driver data base
from its default configuration [DEFAULT_FM_SP_dmaScatterGatherCacheAttr]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] scatterGatherCacheAttr New selection
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaScatterGatherAttr(t_Handle h_FmVsp,
e_FmDmaCacheOption scatterGatherCacheAttr);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaWriteOptimize
@Description Calling this routine changes the write optimization
parameter in the internal driver data base
from its default configuration: optimize = [DEFAULT_FM_SP_dmaWriteOptimize]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] optimize TRUE to enable optimization, FALSE for normal operation
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaWriteOptimize(t_Handle h_FmVsp, bool optimize);
/**************************************************************************//**
@Function FM_VSP_ConfigNoScatherGather
@Description Calling this routine changes the possibility to receive S/G frame
in the internal driver data base
from its default configuration: optimize = [DEFAULT_FM_SP_noScatherGather]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] noScatherGather TRUE to operate without scatter/gather capability.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigNoScatherGather(t_Handle h_FmVsp, bool noScatherGather);
/**************************************************************************//**
@Function FM_VSP_ConfigPoolDepletion
@Description Calling this routine enables pause frame generation depending on the
depletion status of BM pools. It also defines the conditions to activate
this functionality. By default, this functionality is disabled.
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] p_BufPoolDepletion A structure of pool depletion parameters
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigPoolDepletion(t_Handle h_FmVsp, t_FmBufPoolDepletion *p_BufPoolDepletion);
/**************************************************************************//**
@Function FM_VSP_ConfigBackupPools
@Description Calling this routine allows the configuration of some of the BM pools
defined for this port as backup pools.
A pool configured to be a backup pool will be used only if all other
enabled non-backup pools are depleted.
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] p_BackupBmPools An array of pool id's. All pools specified here will
be defined as backup pools.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigBackupPools(t_Handle h_FmVsp, t_FmBackupBmPools *p_BackupBmPools);
/** @} */ /* end of FM_VSP_adv_config_grp group */
/** @} */ /* end of FM_VSP_init_grp group */
/**************************************************************************//**
@Group FM_VSP_control_grp FM VSP Control Unit
@Description FM VSP runtime control API.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_VSP_GetBufferDataOffset
@Description Relevant for Rx ports.
Returns the data offset from the beginning of the data buffer
@Param[in] h_FmVsp - FM PORT module descriptor
@Return data offset.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
uint32_t FM_VSP_GetBufferDataOffset(t_Handle h_FmVsp);
/**************************************************************************//**
@Function FM_VSP_GetBufferICInfo
@Description Returns the Internal Context offset from the beginning of the data buffer
@Param[in] h_FmVsp - FM PORT module descriptor
@Param[in] p_Data - A pointer to the data buffer.
@Return Internal context info pointer on success, NULL if 'allOtherInfo' was not
configured for this port.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
uint8_t * FM_VSP_GetBufferICInfo(t_Handle h_FmVsp, char *p_Data);
/**************************************************************************//**
@Function FM_VSP_GetBufferPrsResult
@Description Returns the pointer to the parse result in the data buffer.
In Rx ports this is relevant after reception, if parse
result is configured to be part of the data passed to the
application. For non Rx ports it may be used to get the pointer
of the area in the buffer where parse result should be
initialized - if so configured.
See FM_VSP_ConfigBufferPrefixContent for data buffer prefix
configuration.
@Param[in] h_FmVsp - FM PORT module descriptor
@Param[in] p_Data - A pointer to the data buffer.
@Return Parse result pointer on success, NULL if parse result was not
configured for this port.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
t_FmPrsResult * FM_VSP_GetBufferPrsResult(t_Handle h_FmVsp, char *p_Data);
/**************************************************************************//**
@Function FM_VSP_GetBufferTimeStamp
@Description Returns the time stamp in the data buffer.
Relevant for Rx ports for getting the buffer time stamp.
See FM_VSP_ConfigBufferPrefixContent for data buffer prefix
configuration.
@Param[in] h_FmVsp - FM PORT module descriptor
@Param[in] p_Data - A pointer to the data buffer.
@Return A pointer to the hash result on success, NULL otherwise.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
uint64_t * FM_VSP_GetBufferTimeStamp(t_Handle h_FmVsp, char *p_Data);
/**************************************************************************//**
@Function FM_VSP_GetBufferHashResult
@Description Given a data buffer, on the condition that hash result was defined
as a part of the buffer content (see FM_VSP_ConfigBufferPrefixContent)
this routine will return the pointer to the hash result location in the
buffer prefix.
@Param[in] h_FmVsp - FM PORT module descriptor
@Param[in] p_Data - A pointer to the data buffer.
@Return A pointer to the hash result on success, NULL otherwise.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
uint8_t * FM_VSP_GetBufferHashResult(t_Handle h_FmVsp, char *p_Data);
/** @} */ /* end of FM_VSP_control_grp group */
/** @} */ /* end of FM_VSP_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_VSP_EXT_H */

76
sys/contrib/ncsw/inc/Peripherals/mii_acc_ext.h Normal file
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@ -0,0 +1,76 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MII_ACC_EXT_H
#define __MII_ACC_EXT_H
/**************************************************************************//**
@Function MII_ReadPhyReg
@Description This routine is called to read a specified PHY
register value.
@Param[in] h_MiiAccess - Handle to MII configuration access registers
@Param[in] phyAddr - PHY address (0-31).
@Param[in] reg - PHY register to read
@Param[out] p_Data - Gets the register value.
@Return Always zero (success).
*//***************************************************************************/
int MII_ReadPhyReg(t_Handle h_MiiAccess,
uint8_t phyAddr,
uint8_t reg,
uint16_t *p_Data);
/**************************************************************************//**
@Function MII_WritePhyReg
@Description This routine is called to write data to a specified PHY
register.
@Param[in] h_MiiAccess - Handle to MII configuration access registers
@Param[in] phyAddr - PHY address (0-31).
@Param[in] reg - PHY register to write
@Param[in] data - Data to write in register.
@Return Always zero (success).
*//***************************************************************************/
int MII_WritePhyReg(t_Handle h_MiiAccess,
uint8_t phyAddr,
uint8_t reg,
uint16_t data);
#endif /* __MII_ACC_EXT_H */

2
sys/contrib/ncsw/inc/Peripherals/qm_ext.h
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@ -627,7 +627,7 @@ typedef struct {
uintptr_t ciBaseAddress; /**< Cache-inhibited base address (virtual) */
t_Handle h_Qm; /**< Qm Handle */
e_DpaaSwPortal swPortalId; /**< Portal id */
int irq; /**< portal interrupt line; used only if useIrq set to TRUE */
uintptr_t irq; /**< portal interrupt line; used only if useIrq set to TRUE */
uint16_t fdLiodnOffset; /**< liodn to be used for all frames enqueued via this software portal */
t_QmReceivedFrameCallback *f_DfltFrame; /**< this callback will be called unless specific callback assigned to the FQ*/
t_QmRejectedFrameCallback *f_RejectedFrame; /**< this callback will be called for rejected frames. */

19
sys/contrib/ncsw/inc/core_ext.h
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@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File core_ext.h
@ -42,7 +43,10 @@
#ifndef __CORE_EXT_H
#define __CORE_EXT_H
#ifdef CONFIG_FMAN_ARM
#include "arm_ext.h"
#include <linux/smp.h>
#else
#ifdef NCSW_PPC_CORE
#include "ppc_ext.h"
#elif defined(NCSW_VXWORKS)
@ -55,6 +59,12 @@
#error "Must define core as little-endian or big-endian!"
#endif /* (!defined(CORE_IS_LITTLE_ENDIAN) && ... */
#ifndef CORE_CACHELINE_SIZE
#error "Must define the core cache-line size!"
#endif /* !CORE_CACHELINE_SIZE */
#endif /* CONFIG_FMAN_ARM */
/**************************************************************************//**
@Function CORE_GetId
@ -75,7 +85,6 @@ uint32_t CORE_GetId(void);
@Return None.
*//***************************************************************************/
void CORE_MemoryBarrier(void);
#define fsl_mem_core_barrier() CORE_MemoryBarrier()
#endif /* __CORE_EXT_H */

55
sys/contrib/ncsw/inc/cores/arm_ext.h Normal file
View File

@ -0,0 +1,55 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File arm_ext.h
@Description Core API for ARM cores
These routines must be implemented by each specific PowerPC
core driver.
*//***************************************************************************/
#ifndef __ARM_EXT_H
#define __ARM_EXT_H
#include "part_ext.h"
#define CORE_IS_LITTLE_ENDIAN
static __inline__ void CORE_MemoryBarrier(void)
{
mb();
}
#endif /* __PPC_EXT_H */

73
sys/contrib/ncsw/inc/cores/e500v2_ext.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File e500v2_ext.h
@ -58,6 +59,8 @@ void L1DCache_Disable(void);
void L1ICache_Disable(void);
void L1DCache_Flush(void);
void L1ICache_Flush(void);
uint32_t L1ICache_IsEnabled(void);
uint32_t L1DCache_IsEnabled(void);
/*
*
*/
@ -193,6 +196,7 @@ typedef enum e_E500mcL2CacheMode
e_L2_CACHE_MODE_DATA_AND_INST = 0x00000003 /**< Cache data and instructions */
} e_E500mcL2CacheMode;
#if defined(CORE_E500MC) || defined(CORE_E5500)
/**************************************************************************//**
@Function E500_L2CacheEnable
@ -237,6 +241,65 @@ void E500_L2CacheFlush(void);
@Return None.
*//***************************************************************************/
void E500_L2SetStashId(uint8_t stashId);
#endif /* defined(CORE_E500MC) || defined(CORE_E5500) */
#ifdef CORE_E6500
/**************************************************************************//**
@Function E6500_L2CacheEnable
@Description Enables the cache for memory pages that are not cache inhibited.
@param[in] mode - L2 cache mode: support data & instruction only.
@Return None.
@Cautions This routine must be call only ONCE for both caches. I.e. it is
not possible to call this routine for i-cache and than to call
again for d-cache; The second call will override the first one.
*//***************************************************************************/
void E6500_L2CacheEnable(uintptr_t clusterBase);
/**************************************************************************//**
@Function E6500_L2CacheDisable
@Description Disables the cache (data instruction or both).
@Return None.
*//***************************************************************************/
void E6500_L2CacheDisable(uintptr_t clusterBase);
/**************************************************************************//**
@Function E6500_L2CacheFlush
@Description Flushes the cache.
@Return None.
*//***************************************************************************/
void E6500_L2CacheFlush(uintptr_t clusterBase);
/**************************************************************************//**
@Function E6500_L2SetStashId
@Description Set Stash Id
@Param[in] stashId the stash id to be set.
@Return None.
*//***************************************************************************/
void E6500_L2SetStashId(uintptr_t clusterBase, uint8_t stashId);
/**************************************************************************//**
@Function E6500_GetCcsrBase
@Description Obtain SoC CCSR base address
@Param[in] None.
@Return Physical CCSR base address.
*//***************************************************************************/
physAddress_t E6500_GetCcsrBase(void);
#endif /* CORE_E6500 */
/**************************************************************************//**
@Function E500_AddressBusStreamingEnable
@ -374,9 +437,9 @@ int E500_TestAndSet(volatile int *p);
*//***************************************************************************/
static __inline__ void E500_MemoryBarrier(void)
{
#ifdef CORE_E500MC
#ifndef CORE_E500V2
__asm__ ("mbar 1");
#else
#else /* CORE_E500V2 */
/**** ERRATA WORK AROUND START ****/
/* ERRATA num: CPU1 */
/* Description: "mbar MO = 1" instruction fails to order caching-inhibited
@ -387,7 +450,7 @@ static __inline__ void E500_MemoryBarrier(void)
__asm__ ("msync");
/**** ERRATA WORK AROUND END ****/
#endif
#endif /* CORE_E500V2 */
}
/**************************************************************************//**

21
sys/contrib/ncsw/inc/cores/ppc_ext.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -30,6 +30,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File ppc_ext.h
@ -46,6 +47,14 @@
#define CORE_IS_BIG_ENDIAN
#if defined(CORE_E300) || defined(CORE_E500V2)
#define CORE_CACHELINE_SIZE 32
#elif defined(CORE_E500MC) || defined(CORE_E5500) || defined(CORE_E6500)
#define CORE_CACHELINE_SIZE 64
#else
#error "Core not defined!"
#endif /* defined(CORE_E300) || ... */
/**************************************************************************//**
@Function CORE_TestAndSet
@ -117,14 +126,6 @@ void CORE_ICacheDisable(void);
#if defined(CORE_E300)
#include "e300_ext.h"
#elif defined(CORE_E500V2) || defined(CORE_E500MC)
#include "e500v2_ext.h"
#else
#error "Core not defined!"
#endif
#endif /* __PPC_EXT_H */

67
sys/contrib/ncsw/inc/ddr_std_ext.h
View File

@ -1,38 +1,34 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
**************************************************************************/
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DDR_SDT_EXT_H
#define __DDR_SDT_EXT_H
@ -60,7 +56,8 @@ typedef enum e_DdrType
e_DDR_DDR1,
e_DDR_DDR2,
e_DDR_DDR3,
e_DDR_DDR3L
e_DDR_DDR3L,
e_DDR_DDR4
} e_DdrType;
/**************************************************************************//**

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