Add an ahci driver for imx6.
This was submitted by Rogiel Sulzbach (thank you!) but has a few last-minute changes by me, mostly where the code interfaces to my still-utterly-deficient imx6_ccm clocks implementation. So blame me for any mistakes. Submitted by: Rogiel Sulzbach <rogiel@rogiel.com> Differential Revision: https://reviews.freebsd.org/D11177
This commit is contained in:
Ian Lepore
parent
f856f099cb
commit
854519fdd9
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=322015
@ -78,6 +78,9 @@ device da # Direct Access (disks)
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device cd # CD
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device pass # Passthrough device (direct ATA/SCSI access)
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# ATA controllers
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device ahci # AHCI-compatible SATA controllers
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# USB support
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device ehci # OHCI USB interface
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device usb # USB Bus (required)
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@ -25,6 +25,7 @@ arm/freescale/imx/imx_i2c.c optional fsliic
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arm/freescale/imx/imx6_sdma.c optional sdma
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arm/freescale/imx/imx6_audmux.c optional sound
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arm/freescale/imx/imx6_ssi.c optional sound
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arm/freescale/imx/imx6_ahci.c optional ahci
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dev/hdmi/hdmi_if.m optional hdmi
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dev/hdmi/dwc_hdmi.c optional hdmi
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358
sys/arm/freescale/imx/imx6_ahci.c
Normal file
358
sys/arm/freescale/imx/imx6_ahci.c
Normal file
@ -0,0 +1,358 @@
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/*-
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* Copyright (c) 2017 Rogiel Sulzbach <rogiel@allogica.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ahci/ahci.h>
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#include <arm/freescale/imx/imx_iomuxreg.h>
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#include <arm/freescale/imx/imx_iomuxvar.h>
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#include <arm/freescale/imx/imx_ccmvar.h>
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#define SATA_TIMER1MS 0x000000e0
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#define SATA_P0PHYCR 0x00000178
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#define SATA_P0PHYCR_CR_READ (1 << 19)
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#define SATA_P0PHYCR_CR_WRITE (1 << 18)
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#define SATA_P0PHYCR_CR_CAP_DATA (1 << 17)
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#define SATA_P0PHYCR_CR_CAP_ADDR (1 << 16)
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#define SATA_P0PHYCR_CR_DATA_IN(v) ((v) & 0xffff)
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#define SATA_P0PHYSR 0x0000017c
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#define SATA_P0PHYSR_CR_ACK (1 << 18)
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#define SATA_P0PHYSR_CR_DATA_OUT(v) ((v) & 0xffff)
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/* phy registers */
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#define SATA_PHY_CLOCK_RESET 0x7f3f
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#define SATA_PHY_CLOCK_RESET_RST (1 << 0)
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#define SATA_PHY_LANE0_OUT_STAT 0x2003
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#define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE (1 << 1)
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static int
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imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, bool on)
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{
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uint32_t v;
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int timeout;
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bool state;
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v = ATA_INL(sc->r_mem, SATA_P0PHYCR);
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if (on) {
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v |= bitmask;
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} else {
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v &= ~bitmask;
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}
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ATA_OUTL(sc->r_mem, SATA_P0PHYCR, v);
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for (timeout = 5000; timeout > 0; --timeout) {
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v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
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state = (v & SATA_P0PHYSR_CR_ACK) == SATA_P0PHYSR_CR_ACK;
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if(state == on) {
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break;
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}
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DELAY(100);
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}
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if (timeout > 0) {
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return (0);
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}
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return (ETIMEDOUT);
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}
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static int
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imx6_ahci_phy_addr(struct ahci_controller* sc, uint32_t addr)
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{
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int error;
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DELAY(100);
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ATA_OUTL(sc->r_mem, SATA_P0PHYCR, addr);
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error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, true);
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if (error != 0) {
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device_printf(sc->dev,
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"%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=1\n",
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__FUNCTION__);
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return (error);
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}
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error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, false);
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if (error != 0) {
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device_printf(sc->dev,
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"%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=0\n",
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__FUNCTION__);
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return (error);
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}
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return (0);
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}
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static int
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imx6_ahci_phy_write(struct ahci_controller* sc, uint32_t addr,
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uint16_t data)
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{
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int error;
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error = imx6_ahci_phy_addr(sc, addr);
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if (error != 0) {
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device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n",
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__FUNCTION__);
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return (error);
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}
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ATA_OUTL(sc->r_mem, SATA_P0PHYCR, data);
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error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, true);
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if (error != 0) {
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device_printf(sc->dev,
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"%s: error on SATA_P0PHYCR_CR_CAP_DATA=1\n", __FUNCTION__);
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return (error);
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}
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if (imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, false) != 0) {
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device_printf(sc->dev,
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"%s: error on SATA_P0PHYCR_CR_CAP_DATA=0\n", __FUNCTION__);
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return (error);
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}
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if ((addr == SATA_PHY_CLOCK_RESET) && data) {
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/* we can't check ACK after RESET */
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ATA_OUTL(sc->r_mem, SATA_P0PHYCR,
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SATA_P0PHYCR_CR_DATA_IN(data) | SATA_P0PHYCR_CR_WRITE);
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return (0);
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}
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error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, true);
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if (error != 0) {
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device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=1\n",
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__FUNCTION__);
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return (error);
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}
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error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, false);
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if (error != 0) {
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device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=0\n",
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__FUNCTION__);
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return (error);
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}
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return (0);
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}
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static int
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imx6_ahci_phy_read(struct ahci_controller* sc, uint32_t addr, uint16_t* val)
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{
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int error;
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uint32_t v;
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error = imx6_ahci_phy_addr(sc, addr);
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if (error != 0) {
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device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n",
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__FUNCTION__);
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return (error);
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}
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error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, true);
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if (error != 0) {
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device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=1\n",
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__FUNCTION__);
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return (error);
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}
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v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
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error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, false);
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if (error != 0) {
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device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=0\n",
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__FUNCTION__);
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return (error);
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}
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*val = SATA_P0PHYSR_CR_DATA_OUT(v);
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return (0);
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}
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static int
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imx6_ahci_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev)) {
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return (ENXIO);
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}
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if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ahci")) {
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return (ENXIO);
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}
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device_set_desc(dev, "i.MX6 Integrated AHCI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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imx6_ahci_attach(device_t dev)
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{
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struct ahci_controller* ctlr;
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uint16_t pllstat;
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uint32_t v;
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int error, timeout;
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ctlr = device_get_softc(dev);
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/* Power up the controller and phy. */
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error = imx6_ccm_sata_enable();
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if (error != 0) {
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device_printf(dev, "error enabling controller and phy\n");
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return (error);
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}
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ctlr->vendorid = 0;
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ctlr->deviceid = 0;
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ctlr->subvendorid = 0;
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ctlr->subdeviceid = 0;
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ctlr->numirqs = 1;
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ctlr->r_rid = 0;
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if ((ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&ctlr->r_rid, RF_ACTIVE)) == NULL) {
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return (ENXIO);
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}
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v = imx_iomux_gpr_get(IOMUX_GPR13);
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/* Clear out existing values; these numbers are bitmasks. */
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v &= ~(IOMUX_GPR13_SATA_PHY_8(7) |
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IOMUX_GPR13_SATA_PHY_7(0x1f) |
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IOMUX_GPR13_SATA_PHY_6(7) |
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IOMUX_GPR13_SATA_SPEED(1) |
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IOMUX_GPR13_SATA_PHY_5(1) |
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IOMUX_GPR13_SATA_PHY_4(7) |
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IOMUX_GPR13_SATA_PHY_3(0xf) |
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IOMUX_GPR13_SATA_PHY_2(0x1f) |
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IOMUX_GPR13_SATA_PHY_1(1) |
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IOMUX_GPR13_SATA_PHY_0(1));
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/* setting */
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v |= IOMUX_GPR13_SATA_PHY_8(5) | /* Rx 3.0db */
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IOMUX_GPR13_SATA_PHY_7(0x12) | /* Rx SATA2m */
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IOMUX_GPR13_SATA_PHY_6(3) | /* Rx DPLL mode */
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IOMUX_GPR13_SATA_SPEED(1) | /* 3.0GHz */
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IOMUX_GPR13_SATA_PHY_5(0) | /* SpreadSpectram */
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IOMUX_GPR13_SATA_PHY_4(4) | /* Tx Attenuation 9/16 */
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IOMUX_GPR13_SATA_PHY_3(0) | /* Tx Boost 0db */
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IOMUX_GPR13_SATA_PHY_2(0x11) | /* Tx Level 1.104V */
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IOMUX_GPR13_SATA_PHY_1(1); /* PLL clock enable */
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imx_iomux_gpr_set(IOMUX_GPR13, v);
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/* phy reset */
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error = imx6_ahci_phy_write(ctlr, SATA_PHY_CLOCK_RESET,
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SATA_PHY_CLOCK_RESET_RST);
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if (error != 0) {
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device_printf(dev, "cannot reset PHY\n");
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goto fail;
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}
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for (timeout = 50; timeout > 0; --timeout) {
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DELAY(100);
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error = imx6_ahci_phy_read(ctlr, SATA_PHY_LANE0_OUT_STAT,
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&pllstat);
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if (error != 0) {
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device_printf(dev, "cannot read LANE0 status\n");
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goto fail;
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}
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if (pllstat & SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE) {
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break;
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}
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}
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if (timeout <= 0) {
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device_printf(dev, "time out reading LANE0 status\n");
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error = ETIMEDOUT;
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goto fail;
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}
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/* Support Staggered Spin-up */
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v = ATA_INL(ctlr->r_mem, AHCI_CAP);
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ATA_OUTL(ctlr->r_mem, AHCI_CAP, v | AHCI_CAP_SSS);
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/* Ports Implemented. must set 1 */
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v = ATA_INL(ctlr->r_mem, AHCI_PI);
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ATA_OUTL(ctlr->r_mem, AHCI_PI, v | (1 << 0));
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/* set 1ms-timer = AHB clock / 1000 */
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ATA_OUTL(ctlr->r_mem, SATA_TIMER1MS,
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imx_ccm_ahb_hz() / 1000);
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/*
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* Note: ahci_attach will release ctlr->r_mem on errors automatically
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*/
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return (ahci_attach(dev));
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fail:
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bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
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return (error);
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}
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static int
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imx6_ahci_detach(device_t dev)
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{
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return (ahci_detach(dev));
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}
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devclass_t ahci_devclass;
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static device_method_t imx6_ahci_ata_methods[] = {
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/* device probe, attach and detach methods */
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DEVMETHOD(device_probe, imx6_ahci_probe),
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DEVMETHOD(device_attach, imx6_ahci_attach),
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DEVMETHOD(device_detach, imx6_ahci_detach),
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/* ahci bus methods */
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DEVMETHOD(bus_print_child, ahci_print_child),
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DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
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DEVMETHOD(bus_release_resource, ahci_release_resource),
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DEVMETHOD(bus_setup_intr, ahci_setup_intr),
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DEVMETHOD(bus_teardown_intr, ahci_teardown_intr),
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DEVMETHOD(bus_child_location_str, ahci_child_location_str),
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DEVMETHOD_END
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};
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static driver_t ahci_ata_driver = {
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"ahci",
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imx6_ahci_ata_methods,
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sizeof(struct ahci_controller)
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};
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DRIVER_MODULE(ahci, simplebus, ahci_ata_driver, ahci_devclass, 0, 0);
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@ -314,6 +314,41 @@ imx_ccm_usbphy_enable(device_t _phydev)
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#endif
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}
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int
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imx6_ccm_sata_enable(void)
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{
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uint32_t v;
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int timeout;
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/* Un-gate the sata controller. */
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WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA);
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/* Power up the PLL that feeds ENET/SATA/PCI phys, wait for lock. */
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v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET);
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v &= ~CCM_ANALOG_PLL_ENET_POWERDOWN;
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WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
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for (timeout = 100000; timeout > 0; timeout--) {
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if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) &
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CCM_ANALOG_PLL_ENET_LOCK) {
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break;
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}
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}
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if (timeout <= 0) {
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return ETIMEDOUT;
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}
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/* Enable the PLL, and enable its 100mhz output. */
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v |= CCM_ANALOG_PLL_ENET_ENABLE;
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v &= ~CCM_ANALOG_PLL_ENET_BYPASS;
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WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
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v |= CCM_ANALOG_PLL_ENET_ENABLE_100M;
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WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
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return 0;
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}
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uint32_t
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imx_ccm_ipg_hz(void)
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{
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@ -116,6 +116,7 @@
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#define CCGR4_PL301_MX6QPER1_BCH (0x3 << 12)
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#define CCGR4_PL301_MX6QPER2_MAIN (0x3 << 14)
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#define CCM_CCGR5 0x07C
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#define CCGR5_SATA (0x3 << 4)
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#define CCGR5_SDMA (0x3 << 6)
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#define CCGR5_SSI1 (0x3 << 18)
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#define CCGR5_SSI2 (0x3 << 20)
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||||
@ -130,4 +131,11 @@
|
||||
#define CCGR6_USDHC4 (0x3 << 8)
|
||||
#define CCM_CMEOR 0x088
|
||||
|
||||
#define CCM_ANALOG_PLL_ENET 0x000040e0
|
||||
#define CCM_ANALOG_PLL_ENET_LOCK (1u << 31)
|
||||
#define CCM_ANALOG_PLL_ENET_ENABLE_100M (1u << 20) /* SATA */
|
||||
#define CCM_ANALOG_PLL_ENET_BYPASS (1u << 16)
|
||||
#define CCM_ANALOG_PLL_ENET_ENABLE (1u << 13) /* Ether */
|
||||
#define CCM_ANALOG_PLL_ENET_POWERDOWN (1u << 12)
|
||||
|
||||
#endif
|
||||
|
||||
@ -54,6 +54,7 @@ void imx_ccm_usbphy_enable(device_t _phydev);
|
||||
void imx_ccm_ssi_configure(device_t _ssidev);
|
||||
void imx_ccm_hdmi_enable(void);
|
||||
void imx_ccm_ipu_enable(int ipu);
|
||||
int imx6_ccm_sata_enable(void);
|
||||
|
||||
/* Routines to get and set the arm clock root divisor register. */
|
||||
uint32_t imx_ccm_get_cacrr(void);
|
||||
|
||||
@ -29,14 +29,33 @@
|
||||
#ifndef IMX_IOMUXREG_H
|
||||
#define IMX_IOMUXREG_H
|
||||
|
||||
#define IOMUXC_GPR0 0x00
|
||||
#define IOMUXC_GPR1 0x04
|
||||
#define IOMUXC_GPR2 0x08
|
||||
#define IOMUXC_GPR3 0x0C
|
||||
#define IOMUXC_GPR3_HDMI_MASK (3 << 2)
|
||||
#define IOMUXC_GPR3_HDMI_IPU1_DI0 (0 << 2)
|
||||
#define IOMUXC_GPR3_HDMI_IPU1_DI1 (1 << 2)
|
||||
#define IOMUXC_GPR3_HDMI_IPU2_DI0 (2 << 2)
|
||||
#define IOMUXC_GPR3_HDMI_IPU2_DI1 (3 << 2)
|
||||
#define IMX_IOMUXREG_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
|
||||
#define IMX_IOMUXREG_SHIFTIN(__x, __mask) ((__x) * IMX_IOMUXREG_LOWEST_SET_BIT(__mask))
|
||||
|
||||
#define IMX_IOMUXREG_BIT(n) (1 << (n))
|
||||
#define IMX_IOMUXREG_BITS(__m, __n) \
|
||||
((IMX_IOMUXREG_BIT(MAX((__m), (__n)) + 1) - 1) ^ (IMX_IOMUXREG_BIT(MIN((__m), (__n))) - 1))
|
||||
|
||||
#define IOMUXC_GPR0 0x00
|
||||
#define IOMUXC_GPR1 0x04
|
||||
#define IOMUXC_GPR2 0x08
|
||||
#define IOMUXC_GPR3 0x0C
|
||||
#define IOMUXC_GPR3_HDMI_MASK (3 << 2)
|
||||
#define IOMUXC_GPR3_HDMI_IPU1_DI0 (0 << 2)
|
||||
#define IOMUXC_GPR3_HDMI_IPU1_DI1 (1 << 2)
|
||||
#define IOMUXC_GPR3_HDMI_IPU2_DI0 (2 << 2)
|
||||
#define IOMUXC_GPR3_HDMI_IPU2_DI1 (3 << 2)
|
||||
|
||||
#define IOMUX_GPR13 0x34
|
||||
#define IOMUX_GPR13_SATA_PHY_8(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(26, 24))
|
||||
#define IOMUX_GPR13_SATA_PHY_7(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(23, 19))
|
||||
#define IOMUX_GPR13_SATA_PHY_6(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(18, 16))
|
||||
#define IOMUX_GPR13_SATA_SPEED(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 15))
|
||||
#define IOMUX_GPR13_SATA_PHY_5(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 14))
|
||||
#define IOMUX_GPR13_SATA_PHY_4(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(13, 11))
|
||||
#define IOMUX_GPR13_SATA_PHY_3(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(10, 7))
|
||||
#define IOMUX_GPR13_SATA_PHY_2(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(6, 2))
|
||||
#define IOMUX_GPR13_SATA_PHY_1(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 1))
|
||||
#define IOMUX_GPR13_SATA_PHY_0(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 0))
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user