From 8657387683946d0c03e09fe77029edfe309eeb20 Mon Sep 17 00:00:00 2001 From: Andrew Turner Date: Sat, 26 Aug 2017 15:08:27 +0000 Subject: [PATCH] Work around a bug in QEMU when loading data with a load pair instruction where the source register is also the first destination register. If this is the case, and we raise an exception in the middle of the instruction, for example the load is across two pages and the second page isn't mapped, QEMU will have overwritten the address with invalid data. This is a valid behaviour in most cases, with the exception of when a destination register is also use in address generation. As such switch the order of the registers to ensure the address register is second so it will be written to second, after any exceptions have happened. This has been acknowledged in upstream QEMU, however as the workaround is simple also handle it here. Sponsored by: DARPA, AFRL --- contrib/cortex-strings/src/aarch64/memcpy.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/contrib/cortex-strings/src/aarch64/memcpy.S b/contrib/cortex-strings/src/aarch64/memcpy.S index cbae37121844..46fb166e345e 100644 --- a/contrib/cortex-strings/src/aarch64/memcpy.S +++ b/contrib/cortex-strings/src/aarch64/memcpy.S @@ -77,8 +77,8 @@ #define D_h x13 #define E_l src #define E_h count -#define F_l srcend -#define F_h dst +#define F_l dst +#define F_h srcend #define tmp1 x9 #define L(l) .L ## l