Moved the definitions of the bits in the ns*50 registers from sioreg.h
to ns16550.h. The organization of these files was sort of backwards. The bits in the registers have no driver or bus dependencies but they but the offsets of the registers in bus space are very bus-dependent. However, it does no harm to keep the definitions of the register offsets in ns16550.h provided they are thought of as internal ns*50 offsets.
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=120116
@ -49,3 +49,88 @@
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#define com_lsr 5 /* line status register (R/W) */
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#define com_msr 6 /* modem status register (R/W) */
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#define com_scr 7 /* scratch register for 16450 up (R/W) */
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/* interrupt enable register */
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#define IER_ERXRDY 0x1
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#define IER_ETXRDY 0x2
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#define IER_ERLS 0x4
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#define IER_EMSC 0x8
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/* interrupt identification register */
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#define IIR_IMASK 0xf
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#define IIR_RXTOUT 0xc
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#define IIR_RLS 0x6
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#define IIR_RXRDY 0x4
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#define IIR_TXRDY 0x2
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#define IIR_NOPEND 0x1
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#define IIR_MLSC 0x0
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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/* fifo control register */
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#define FIFO_ENABLE 0x01
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#define FIFO_RCV_RST 0x02
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#define FIFO_XMT_RST 0x04
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#define FIFO_DMA_MODE 0x08
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#define FIFO_RX_LOW 0x00
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#define FIFO_RX_MEDL 0x40
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#define FIFO_RX_MEDH 0x80
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#define FIFO_RX_HIGH 0xc0
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/* character format control register (aka line control register) */
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#define CFCR_DLAB 0x80
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#define CFCR_SBREAK 0x40
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#define CFCR_PZERO 0x30
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#define CFCR_PONE 0x20
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#define CFCR_PEVEN 0x10
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#define CFCR_PODD 0x00
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#define CFCR_PENAB 0x08
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#define CFCR_STOPB 0x04
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#define CFCR_8BITS 0x03
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#define CFCR_7BITS 0x02
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#define CFCR_6BITS 0x01
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#define CFCR_5BITS 0x00
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#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
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/* modem control register */
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#define MCR_PRESCALE 0x80 /* only available on 16650 up */
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#define MCR_LOOPBACK 0x10
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#define MCR_IENABLE 0x08
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#define MCR_DRS 0x04
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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/* line status register */
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#define LSR_RCV_FIFO 0x80
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#define LSR_TSRE 0x40
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#define LSR_TXRDY 0x20
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#define LSR_BI 0x10
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#define LSR_FE 0x08
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#define LSR_PE 0x04
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#define LSR_OE 0x02
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#define LSR_RXRDY 0x01
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#define LSR_RCV_MASK 0x1f
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/* modem status register */
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#define MSR_DCD 0x80
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#define MSR_RI 0x40
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#define MSR_DSR 0x20
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#define MSR_CTS 0x10
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#define MSR_DDCD 0x08
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#define MSR_TERI 0x04
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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/* enhanced feature register (only available on 16650 up) */
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#define com_efr com_fifo
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#define EFR_EFE 0x10 /* enhanced functions enable */
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#ifdef PC98
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/* Hardware extension mode register for RSB-2000/3000. */
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#define com_emr com_msr
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#define EMR_EXBUFF 0x04
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#define EMR_CTSFLW 0x08
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#define EMR_DSRFLW 0x10
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#define EMR_RTSFLW 0x20
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#define EMR_DTRFLW 0x40
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#define EMR_EFMODE 0x80
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#endif
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@ -37,91 +37,6 @@
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/* Receiver clock frequency for "standard" pc serial ports. */
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#define DEFAULT_RCLK 1843200
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/* interrupt enable register */
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#define IER_ERXRDY 0x1
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#define IER_ETXRDY 0x2
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#define IER_ERLS 0x4
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#define IER_EMSC 0x8
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/* interrupt identification register */
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#define IIR_IMASK 0xf
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#define IIR_RXTOUT 0xc
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#define IIR_RLS 0x6
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#define IIR_RXRDY 0x4
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#define IIR_TXRDY 0x2
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#define IIR_NOPEND 0x1
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#define IIR_MLSC 0x0
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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/* fifo control register */
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#define FIFO_ENABLE 0x01
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#define FIFO_RCV_RST 0x02
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#define FIFO_XMT_RST 0x04
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#define FIFO_DMA_MODE 0x08
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#define FIFO_RX_LOW 0x00
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#define FIFO_RX_MEDL 0x40
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#define FIFO_RX_MEDH 0x80
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#define FIFO_RX_HIGH 0xc0
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/* character format control register (aka line control register) */
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#define CFCR_DLAB 0x80
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#define CFCR_SBREAK 0x40
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#define CFCR_PZERO 0x30
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#define CFCR_PONE 0x20
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#define CFCR_PEVEN 0x10
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#define CFCR_PODD 0x00
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#define CFCR_PENAB 0x08
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#define CFCR_STOPB 0x04
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#define CFCR_8BITS 0x03
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#define CFCR_7BITS 0x02
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#define CFCR_6BITS 0x01
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#define CFCR_5BITS 0x00
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#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
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/* modem control register */
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#define MCR_PRESCALE 0x80 /* only available on 16650 up */
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#define MCR_LOOPBACK 0x10
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#define MCR_IENABLE 0x08
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#define MCR_DRS 0x04
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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/* line status register */
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#define LSR_RCV_FIFO 0x80
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#define LSR_TSRE 0x40
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#define LSR_TXRDY 0x20
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#define LSR_BI 0x10
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#define LSR_FE 0x08
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#define LSR_PE 0x04
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#define LSR_OE 0x02
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#define LSR_RXRDY 0x01
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#define LSR_RCV_MASK 0x1f
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/* modem status register */
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#define MSR_DCD 0x80
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#define MSR_RI 0x40
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#define MSR_DSR 0x20
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#define MSR_CTS 0x10
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#define MSR_DDCD 0x08
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#define MSR_TERI 0x04
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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/* enhanced feature register (only available on 16650 up) */
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#define com_efr com_fifo
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#define EFR_EFE 0x10 /* enhanced functions enable */
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#ifdef PC98
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/* Hardware extension mode register for RSB-2000/3000. */
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#define com_emr com_msr
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#define EMR_EXBUFF 0x04
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#define EMR_CTSFLW 0x08
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#define EMR_DSRFLW 0x10
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#define EMR_RTSFLW 0x20
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#define EMR_DTRFLW 0x40
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#define EMR_EFMODE 0x80
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#endif
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/* speed to initialize to during chip tests */
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#define SIO_TEST_SPEED 9600
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