dwmmc: Multiple busdma fixes.
- limit maximum segment size to 2048 bytes. Although dwmmc supports a buffer fragment with a maximum length of 4095 bytes, use the nearest lower power of two as the maximum fragment size. Otherwise, busdma create excessive buffer fragments. - fix off by one error in computation of the maximum data transfer length. - in addition, reserve two DMA descriptors that can be used by busdma bouncing. The beginning or end of the buffer can be misaligned. - Don’t ignore errors passed to bus_dmamap_load() callback function. - In theory, a DMA engine may be running at time when next dma descriptor is constructed. Create a full DMA descriptor before OWN bit is set. MFC after: 2 weeks
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14c40d2c29
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@ -107,8 +107,7 @@ __FBSDID("$FreeBSD$");
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#define CARD_INIT_DONE 0x04
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#define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \
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|SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE \
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|SDMMC_INTMASK_EBE)
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|SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE)
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#define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \
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|SDMMC_INTMASK_RE)
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#define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \
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@ -134,7 +133,16 @@ struct idmac_desc {
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#define IDMAC_DESC_SEGS (PAGE_SIZE / (sizeof(struct idmac_desc)))
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#define IDMAC_DESC_SIZE (sizeof(struct idmac_desc) * IDMAC_DESC_SEGS)
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#define DEF_MSIZE 0x2 /* Burst size of multiple transaction */
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#define IDMAC_MAX_SIZE 4096
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/*
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* Size field in DMA descriptor is 13 bits long (up to 4095 bytes),
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* but must be a multiple of the data bus size.Additionally, we must ensure
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* that bus_dmamap_load() doesn't additionally fragments buffer (because it
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* is processed with page size granularity). Thus limit fragment size to half
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* of page.
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* XXX switch descriptor format to array and use second buffer pointer for
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* second half of page
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*/
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#define IDMAC_MAX_SIZE 2048
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static void dwmmc_next_operation(struct dwmmc_softc *);
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static int dwmmc_setup_bus(struct dwmmc_softc *, int);
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@ -165,8 +173,11 @@ static void
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dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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{
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if (nsegs != 1)
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panic("%s: nsegs != 1 (%d)\n", __func__, nsegs);
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if (error != 0)
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return;
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panic("%s: error != 0 (%d)\n", __func__, error);
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*(bus_addr_t *)arg = segs[0].ds_addr;
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}
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@ -176,15 +187,13 @@ dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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struct dwmmc_softc *sc;
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int idx;
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if (error != 0)
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return;
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sc = arg;
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dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len);
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if (error != 0)
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panic("%s: error != 0 (%d)\n", __func__, error);
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for (idx = 0; idx < nsegs; idx++) {
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sc->desc_ring[idx].des0 = (DES0_OWN | DES0_DIC | DES0_CH);
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sc->desc_ring[idx].des0 = DES0_DIC | DES0_CH;
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sc->desc_ring[idx].des1 = segs[idx].ds_len & DES1_BS1_MASK;
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sc->desc_ring[idx].des2 = segs[idx].ds_addr;
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@ -195,6 +204,8 @@ dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH);
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sc->desc_ring[idx].des0 |= DES0_LD;
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}
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wmb();
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sc->desc_ring[idx].des0 |= DES0_OWN;
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}
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}
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@ -277,7 +288,7 @@ dma_setup(struct dwmmc_softc *sc)
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error = bus_dma_tag_create(
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bus_get_dma_tag(sc->dev), /* Parent tag. */
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CACHE_LINE_SIZE, 0, /* alignment, boundary */
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8, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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@ -786,7 +797,7 @@ dwmmc_attach(device_t dev)
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fail:
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mtx_unlock(&sc->sim_mtx);
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#endif
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/*
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/*
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* Schedule a card detection as we won't get an interrupt
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* if the card is inserted when we attach
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*/
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@ -900,8 +911,8 @@ dwmmc_update_ios(device_t brdev, device_t reqdev)
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sc = device_get_softc(brdev);
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ios = &sc->host.ios;
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dprintf("Setting up clk %u bus_width %d\n",
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ios->clock, ios->bus_width);
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dprintf("Setting up clk %u bus_width %d, timming: %d\n",
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ios->clock, ios->bus_width, ios->timing);
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if (ios->bus_width == bus_width_8)
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WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT);
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@ -985,7 +996,7 @@ dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd)
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reg = READ4(sc, SDMMC_INTMASK);
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reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR);
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WRITE4(sc, SDMMC_INTMASK, reg);
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dprintf("%s: bus_dmamap_load size: %zu\n", __func__, data->len);
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err = bus_dmamap_load(sc->buf_tag, sc->buf_map,
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data->data, data->len, dwmmc_ring_setup,
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sc, BUS_DMA_NOWAIT);
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@ -1358,7 +1369,13 @@ dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
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*(int *)result = sc->host.caps;
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break;
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case MMCBR_IVAR_MAX_DATA:
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*(int *)result = (IDMAC_MAX_SIZE * IDMAC_DESC_SEGS) / MMC_SECTOR_SIZE;
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/*
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* Busdma may bounce buffers, so we must reserve 2 descriptors
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* (on start and on end) for bounced fragments.
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*
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*/
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*(int *)result = (IDMAC_MAX_SIZE * IDMAC_DESC_SEGS) /
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MMC_SECTOR_SIZE - 3;
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break;
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case MMCBR_IVAR_TIMING:
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*(int *)result = sc->host.ios.timing;
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