Virgin import of Xircom PCCARD driver v1.14
This driver is mostly based on the `xirc2ps' driver for Linux by Werner Koch. Werner has even allowed his code to be distributed under a BSD licence, making our life considerably easier -- thanks Werner! This driver supports: * Intel EtherExpress(TM) PRO/100 PCCARD (16-bit version) * Xircom CreditCard CE2 / CEM28 / CEM33 / CE3 / CEM56 Ethernet adapters. * Toshiba Advanced Network 10/100 PCCARD * Certain Compaq Netelligent 10/100 branded cards v1.14 has major changes to media selection code, and bugfixes in the probe routine. Developed by: Scott Mitchell <scott@uk.freebsd.org> Obtained from: http://www.freebsd-uk.eu.org/~scott/xe_drv/
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obrien
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sys/dev/xe/if_xe.c
2558
sys/dev/xe/if_xe.c
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@ -23,13 +23,13 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_xereg.h,v 1.2 1999/01/24 22:15:30 root Exp $
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* $Id: if_xereg.h,v 1.3 1999/02/22 14:00:53 root Exp $
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*/
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/*
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* Register definitions for Xircom CreditCard Ethernet adapters. See if_xe.c
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* for details of supported hardware. Adapted from Werner Koch's 'xirc2ps'
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* driver for Linux.
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* driver for Linux and the FreeBSD 'xl' driver (for the MII support).
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*/
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#include "xe.h"
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@ -199,88 +199,98 @@
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*/
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/*
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* MII/PHY defines adapted from the xl driver. These need cleaning up a
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* little if we end up using them.
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* Definitions for the Micro Linear ML6692 100Base-TX PHY, which handles the
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* 100Mbit functionality of CE3 type cards, including media autonegotiation.
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* It appears to be mostly compatible with the National Semiconductor
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* DP83840A, but with a much smaller register set. Please refer to the data
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* sheets for these devices for the definitive word on what all this stuff
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* means :)
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*
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* Note that the ML6692 has no 10Mbit capability -- that is handled by another
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* chip that we don't know anything about.
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*
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* Most of these definitions were adapted from the xl driver.
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*/
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/*
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* Masks for the MII-related bits in GPR2. For some reason read and write
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* data are on separate bits.
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*/
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#define XE_MII_CLK 0x01
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#define XE_MII_DIR 0x08
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#define XE_MII_WRD 0x02
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#define XE_MII_RDD 0x20
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/*
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* MII command (etc) bit strings.
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*/
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#define XE_MII_STARTDELIM 0x01
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#define XE_MII_READOP 0x02
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#define XE_MII_WRITEOP 0x01
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#define XE_MII_TURNAROUND 0x02
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#define XE_MII_SET(x) XE_OUTB(XE_GPR2, (XE_INB(XE_GPR2) | 0x04) | (x))
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#define XE_MII_CLR(x) XE_OUTB(XE_GPR2, (XE_INB(XE_GPR2) | 0x04) & ~(x))
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/*
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* PHY registers.
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*/
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#define PHY_BMCR 0x00 /* Basic Mode Control Register */
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#define PHY_BMSR 0x01 /* Basic Mode Status Register */
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#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisment Register */
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#define PHY_LPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */
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#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */
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#define XL_PHY_GENCTL 0x00
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#define XL_PHY_GENSTS 0x01
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#define XL_PHY_VENID 0x02
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#define XL_PHY_DEVID 0x03
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#define XL_PHY_ANAR 0x04
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#define XL_PHY_LPAR 0x05
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#define XL_PHY_ANER 0x06
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#define PHY_BMCR_RESET 0x8000 /* Soft reset PHY. Self-clearing */
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#define PHY_BMCR_LOOPBK 0x4000 /* Enable loopback */
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#define PHY_BMCR_SPEEDSEL 0x2000 /* 1=100Mbps, 0=10Mbps */
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#define PHY_BMCR_AUTONEGENBL 0x1000 /* Auto-negotiation enabled */
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#define PHY_BMCR_ISOLATE 0x0400 /* Isolate ML6692 from MII */
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#define PHY_BMCR_AUTONEGRSTR 0x0200 /* Restart auto-negotiation. Self-clearing */
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#define PHY_BMCR_DUPLEX 0x0100 /* Full duplex operation */
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#define PHY_BMCR_COLLTEST 0x0080 /* Enable collision test */
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#define PHY_ANAR_NEXTPAGE 0x8000
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#define PHY_ANAR_RSVD0 0x4000
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#define PHY_ANAR_TLRFLT 0x2000
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#define PHY_ANAR_RSVD1 0x1000
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#define PHY_ANAR_RSVD2 0x0800
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#define PHY_ANAR_RSVD3 0x0400
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#define PHY_ANAR_100BT4 0x0200
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#define PHY_ANAR_100BTXFULL 0x0100
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#define PHY_ANAR_100BTXHALF 0x0080
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#define PHY_ANAR_10BTFULL 0x0040
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#define PHY_ANAR_10BTHALF 0x0020
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#define PHY_ANAR_PROTO4 0x0010
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#define PHY_BMSR_100BT4 0x8000 /* 100Base-T4 capable */
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#define PHY_BMSR_100BTXFULL 0x4000 /* 100Base-TX full duplex capable */
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#define PHY_BMSR_100BTXHALF 0x2000 /* 100Base-TX half duplex capable */
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#define PHY_BMSR_10BTFULL 0x1000 /* 10Base-T full duplex capable */
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#define PHY_BMSR_10BTHALF 0x0800 /* 10Base-T half duplex capable */
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#define PHY_BMSR_AUTONEGCOMP 0x0020 /* Auto-negotiation complete */
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#define PHY_BMSR_CANAUTONEG 0x0008 /* Auto-negotiation supported */
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#define PHY_BMSR_LINKSTAT 0x0004 /* Link is up */
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#define PHY_BMSR_EXTENDED 0x0001 /* Extended register capabilities */
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#define PHY_ANAR_NEXTPAGE 0x8000 /* Additional link code word pages */
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#define PHY_ANAR_TLRFLT 0x2000 /* Remote wire fault detected */
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#define PHY_ANAR_100BT4 0x0200 /* 100Base-T4 capable */
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#define PHY_ANAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */
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#define PHY_ANAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */
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#define PHY_ANAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */
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#define PHY_ANAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */
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#define PHY_ANAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */
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#define PHY_ANAR_PROTO3 0x0008
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#define PHY_ANAR_PROTO2 0x0004
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#define PHY_ANAR_PROTO1 0x0002
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#define PHY_ANAR_PROTO0 0x0001
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/*
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* PHY BMCR Basic Mode Control Register
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*/
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#define PHY_BMCR 0x00
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_LOOPBK 0x4000
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#define PHY_BMCR_SPEEDSEL 0x2000
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#define PHY_BMCR_AUTONEGENBL 0x1000
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#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
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#define PHY_BMCR_ISOLATE 0x0400
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#define PHY_BMCR_AUTONEGRSTR 0x0200
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#define PHY_BMCR_DUPLEX 0x0100
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#define PHY_BMCR_COLLTEST 0x0080
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#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
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#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
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#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
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#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
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#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
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#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
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#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
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#define PHY_LPAR_NEXTPAGE 0x8000 /* Additional link code word pages */
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#define PHY_LPAR_LPACK 0x4000 /* Link partner acknowledged receipt */
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#define PHY_LPAR_TLRFLT 0x2000 /* Remote wire fault detected */
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#define PHY_LPAR_100BT4 0x0200 /* 100Base-T4 capable */
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#define PHY_LPAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */
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#define PHY_LPAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */
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#define PHY_LPAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */
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#define PHY_LPAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */
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#define PHY_LPAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */
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#define PHY_LPAR_PROTO3 0x0008
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#define PHY_LPAR_PROTO2 0x0004
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#define PHY_LPAR_PROTO1 0x0002
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#define PHY_LPAR_PROTO0 0x0001
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/*
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* PHY, BMSR Basic Mode Status Register
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*/
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#define PHY_BMSR 0x01
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#define PHY_BMSR_100BT4 0x8000
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#define PHY_BMSR_100BTXFULL 0x4000
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#define PHY_BMSR_100BTXHALF 0x2000
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#define PHY_BMSR_10BTFULL 0x1000
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#define PHY_BMSR_10BTHALF 0x0800
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#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
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#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
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#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
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#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
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#define PHY_BMSR_MFPRESUP 0x0040
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#define PHY_BMSR_AUTONEGCOMP 0x0020
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#define PHY_BMSR_REMFAULT 0x0010
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#define PHY_BMSR_CANAUTONEG 0x0008
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#define PHY_BMSR_LINKSTAT 0x0004
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#define PHY_BMSR_JABBER 0x0002
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#define PHY_BMSR_EXTENDED 0x0001
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#define PHY_ANER_MLFAULT 0x0010 /* More than one link is up! */
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#define PHY_ANER_LPNPABLE 0x0008 /* Link partner supports next page */
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#define PHY_ANER_NPABLE 0x0004 /* Local port supports next page */
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#define PHY_ANER_PAGERX 0x0002 /* Page received */
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#define PHY_ANER_LPAUTONEG 0x0001 /* Link partner can auto-negotiate */
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#endif /* NXE > 0 */
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