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remove special handling for BNR; it is direct mapped to the harwdare so

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can be added to HAL_INT_COMMON except on the 5210 where it doesn't exist
This commit is contained in:
Sam Leffler 2009-05-19 17:35:15 +00:00
parent 683f31342d
commit 88608a2211
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=192397
6 changed files with 5 additions and 16 deletions
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1
sys/dev/ath/ath_hal/ah.h
View File

@ -356,6 +356,7 @@ typedef enum {
| HAL_INT_RXKCM
| HAL_INT_SWBA
| HAL_INT_BMISS
| HAL_INT_BNR
| HAL_INT_GPIO,
} HAL_INT;

2
sys/dev/ath/ath_hal/ar5210/ar5210_attach.c
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@ -369,7 +369,7 @@ ar5210FillCapabilityInfo(struct ath_hal *ah)
}
pCap->halTstampPrecision = 15; /* NB: s/w extended from 13 */
pCap->halIntrMask = HAL_INT_COMMON
pCap->halIntrMask = (HAL_INT_COMMON - HAL_INT_BNR)
| HAL_INT_RX
| HAL_INT_TX
| HAL_INT_FATAL

6
sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c
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@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5210_interrupts.c,v 1.4 2008/11/10 04:08:02 sam Exp $
* $FreeBSD$
*/
#include "opt_ah.h"
@ -59,7 +59,7 @@ ar5210GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
* status bits leak through that weren't requested
* (e.g. RXNOFRM) and that might confuse the caller.
*/
*masked = (isr & HAL_INT_COMMON) & ahp->ah_maskReg;
*masked = (isr & (HAL_INT_COMMON - HAL_INT_BNR)) & ahp->ah_maskReg;
if (isr & AR_FATAL_INT)
*masked |= HAL_INT_FATAL;
@ -105,7 +105,7 @@ ar5210SetInterrupts(struct ath_hal *ah, HAL_INT ints)
OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
}
mask = ints & HAL_INT_COMMON;
mask = ints & (HAL_INT_COMMON - HAL_INT_BNR);
if (ints & HAL_INT_RX)
mask |= AR_IMR_RXOK_INT | AR_IMR_RXERR_INT;
if (ints & HAL_INT_TX) {

4
sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c
View File

@ -64,8 +64,6 @@ ar5211GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
*masked |= HAL_INT_RX;
if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL))
*masked |= HAL_INT_TX;
if (isr & AR_ISR_BNR)
*masked |= HAL_INT_BNR;
/*
* Receive overrun is usually non-fatal on Oahu/Spirit.
* BUT on some parts rx could fail and the chip must be reset.
@ -139,8 +137,6 @@ ar5211SetInterrupts(struct ath_hal *ah, HAL_INT ints)
}
if (ints & HAL_INT_RX)
mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
if (ints & AR_ISR_BNR)
mask |= HAL_INT_BNR;
if (ints & HAL_INT_FATAL) {
/*
* NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2

4
sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c
View File

@ -92,8 +92,6 @@ ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
}
if (isr & AR_ISR_BNR)
*masked |= HAL_INT_BNR;
/*
* Receive overrun is usually non-fatal on Oahu/Spirit.
@ -175,8 +173,6 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
if (ints & HAL_INT_CABEND)
mask2 |= (AR_IMR_S2_CABEND );
}
if (ints & HAL_INT_BNR)
mask |= AR_IMR_BNR;
if (ints & HAL_INT_FATAL) {
/*
* NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2

4
sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c
View File

@ -119,8 +119,6 @@ ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
}
if (isr & AR_ISR_BNR)
*masked |= HAL_INT_BNR;
/* Interrupt Mitigation on AR5416 */
#ifdef AR5416_INT_MITIGATION
@ -229,8 +227,6 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
if (ints & HAL_INT_TSFOOR)
mask2 |= AR_IMR_S2_TSFOOR;
}
if (ints & HAL_INT_BNR)
mask |= AR_IMR_BNR;
/* Write the new IMR and store off our SW copy. */
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);