o introduce a flags 'errata' for HW bugs onto the softc.
o remove errata_a0 and introduce the corresponding flags into 'errata'. o introduce a new errata for K8, namely some platform might set the PENDING_BIT but aren't able to unset it, also don't loop forever waiting PENDING_BIT being cleared. o try to introduce a workaround for the PENDING_BIT stuck problem, o support now half multipliers for K8. Tested by: Abdullah Al-Marrie Approved by: njl
This commit is contained in:
Bruno Ducrot
parent
8bd73484dc
commit
8867dfa953
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=166197
@ -55,6 +55,15 @@ __FBSDID("$FreeBSD$");
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#define PN7_TYPE 0
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#define PN8_TYPE 1
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/* Flags for some hardware bugs. */
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#define A0_ERRATA 0x1 /* Bugs for the rev. A0 of Athlon (K7):
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* Interrupts must be disabled and no half
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* multipliers are allowed */
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#define PENDING_STUCK 0x2 /* With some buggy chipset and some newer AMD64
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* processor (Rev. G?):
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* the pending bit from the msr FIDVID_STATUS
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* is set forever. No workaround :( */
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/* Legacy configuration via BIOS table PSB. */
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#define PSB_START 0
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#define PSB_STEP 0x10
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@ -140,11 +149,6 @@ struct pst_header {
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wrmsr(MSR_AMDK7_FIDVID_CTL, \
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(((ctrl) << 32) | (1ULL << 16) | ((vid) << 8) | (fid)))
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#define READ_PENDING_WAIT(status) \
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do { \
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(status) = rdmsr(MSR_AMDK7_FIDVID_STATUS); \
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} while (PN8_STA_PENDING(status))
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#define COUNT_OFF_IRT(irt) DELAY(10 * (1 << (irt)))
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#define COUNT_OFF_VST(vst) DELAY(20 * (vst))
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@ -164,11 +168,15 @@ static int pn7_fid_to_mult[32] = {
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};
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static int pn8_fid_to_mult[32] = {
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40, 50, 60, 70, 80, 90, 100, 110,
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120, 130, 140, 150, 160, 170, 180, 190,
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220, 230, 240, 250, 260, 270, 280, 290,
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300, 310, 320, 330, 340, 350,
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static int pn8_fid_to_mult[64] = {
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40, 45, 50, 55, 60, 65, 70, 75,
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80, 85, 90, 95, 100, 105, 110, 115,
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120, 125, 130, 135, 140, 145, 150, 155,
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160, 165, 170, 175, 180, 185, 190, 195,
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200, 205, 210, 215, 220, 225, 230, 235,
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240, 245, 250, 255, 260, 265, 270, 275,
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280, 285, 290, 295, 300, 305, 310, 315,
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320, 325, 330, 335, 340, 345, 350, 355,
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};
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/*
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@ -219,7 +227,7 @@ struct pn_softc {
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int low;
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int powernow_max_states;
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u_int powernow_state;
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int errata_a0;
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u_int errata;
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int *vid_to_volts;
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};
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@ -285,7 +293,7 @@ pn7_setfidvid(struct pn_softc *sc, int fid, int vid)
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ctl |= PN7_CTR_VID(vid);
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ctl |= PN7_CTR_SGTC(sc->sgtc);
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if (sc->errata_a0)
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if (sc->errata & A0_ERRATA)
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disable_intr();
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if (pn7_fid_to_mult[fid] < pn7_fid_to_mult[cfid]) {
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@ -298,21 +306,49 @@ pn7_setfidvid(struct pn_softc *sc, int fid, int vid)
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wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC);
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}
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if (sc->errata_a0)
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if (sc->errata & A0_ERRATA)
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enable_intr();
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return (0);
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}
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static int
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pn8_read_pending_wait(uint64_t *status)
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{
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int i = 10000;
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do
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*status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
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while (PN8_STA_PENDING(*status) && --i);
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return (i == 0 ? ENXIO : 0);
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}
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static int
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pn8_write_fidvid(u_int fid, u_int vid, uint64_t ctrl, uint64_t *status)
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{
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int i = 100;
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do
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WRITE_FIDVID(fid, vid, ctrl);
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while (pn8_read_pending_wait(status) && --i);
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return (i == 0 ? ENXIO : 0);
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}
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static int
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pn8_setfidvid(struct pn_softc *sc, int fid, int vid)
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{
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uint64_t status;
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int cfid, cvid;
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int rvo;
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int rv;
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u_int val;
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READ_PENDING_WAIT(status);
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rv = pn8_read_pending_wait(&status);
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if (rv)
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return (rv);
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cfid = PN8_STA_CFID(status);
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cvid = PN8_STA_CVID(status);
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@ -325,8 +361,11 @@ pn8_setfidvid(struct pn_softc *sc, int fid, int vid)
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*/
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while (cvid > vid) {
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val = cvid - (1 << sc->mvs);
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WRITE_FIDVID(cfid, (val > 0) ? val : 0, 1ULL);
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READ_PENDING_WAIT(status);
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rv = pn8_write_fidvid(cfid, (val > 0) ? val : 0, 1ULL, &status);
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if (rv) {
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sc->errata |= PENDING_STUCK;
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return (rv);
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}
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cvid = PN8_STA_CVID(status);
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COUNT_OFF_VST(sc->vst);
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}
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@ -336,54 +375,67 @@ pn8_setfidvid(struct pn_softc *sc, int fid, int vid)
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/* XXX It's not clear from spec if we have to do that
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* in 0.25 step or in MVS. Therefore do it as it's done
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* under Linux */
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WRITE_FIDVID(cfid, cvid - 1, 1ULL);
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READ_PENDING_WAIT(status);
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rv = pn8_write_fidvid(cfid, cvid - 1, 1ULL, &status);
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if (rv) {
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sc->errata |= PENDING_STUCK;
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return (rv);
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}
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cvid = PN8_STA_CVID(status);
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COUNT_OFF_VST(sc->vst);
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}
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/* Phase 2: change to requested core frequency */
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if (cfid != fid) {
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u_int vco_fid, vco_cfid;
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u_int vco_fid, vco_cfid, fid_delta;
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vco_fid = FID_TO_VCO_FID(fid);
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vco_cfid = FID_TO_VCO_FID(cfid);
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while (abs(vco_fid - vco_cfid) > 2) {
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fid_delta = (vco_cfid & 1) ? 1 : 2;
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if (fid > cfid) {
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if (cfid > 6)
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val = cfid + 2;
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if (cfid > 7)
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val = cfid + fid_delta;
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else
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val = FID_TO_VCO_FID(cfid) + 2;
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val = FID_TO_VCO_FID(cfid) + fid_delta;
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} else
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val = cfid - 2;
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WRITE_FIDVID(val, cvid, sc->pll * (uint64_t) sc->fsb);
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READ_PENDING_WAIT(status);
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val = cfid - fid_delta;
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rv = pn8_write_fidvid(val, cvid,
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sc->pll * (uint64_t) sc->fsb,
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&status);
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if (rv) {
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sc->errata |= PENDING_STUCK;
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return (rv);
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}
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cfid = PN8_STA_CFID(status);
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COUNT_OFF_IRT(sc->irt);
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vco_cfid = FID_TO_VCO_FID(cfid);
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}
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WRITE_FIDVID(fid, cvid, sc->pll * (uint64_t) sc->fsb);
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READ_PENDING_WAIT(status);
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rv = pn8_write_fidvid(fid, cvid,
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sc->pll * (uint64_t) sc->fsb,
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&status);
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if (rv) {
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sc->errata |= PENDING_STUCK;
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return (rv);
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}
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cfid = PN8_STA_CFID(status);
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COUNT_OFF_IRT(sc->irt);
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}
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/* Phase 3: change to requested voltage */
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if (cvid != vid) {
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WRITE_FIDVID(cfid, vid, 1ULL);
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READ_PENDING_WAIT(status);
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rv = pn8_write_fidvid(cfid, vid, 1ULL, &status);
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cvid = PN8_STA_CVID(status);
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COUNT_OFF_VST(sc->vst);
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}
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/* Check if transition failed. */
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if (cfid != fid || cvid != vid)
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return (ENXIO);
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rv = ENXIO;
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return (0);
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return (rv);
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}
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static int
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@ -398,6 +450,9 @@ pn_set(device_t dev, const struct cf_setting *cf)
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return (EINVAL);
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sc = device_get_softc(dev);
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if (sc->errata & PENDING_STUCK)
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return (ENXIO);
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for (i = 0; i < sc->powernow_max_states; ++i)
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if (CPUFREQ_CMP(sc->powernow_states[i].freq / 1000, cf->freq))
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break;
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@ -430,6 +485,8 @@ pn_get(device_t dev, struct cf_setting *cf)
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if (cf == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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if (sc->errata & PENDING_STUCK)
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return (ENXIO);
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status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
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@ -517,13 +574,12 @@ decode_pst(struct pn_softc *sc, uint8_t *p, int npstates)
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switch (sc->pn_type) {
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case PN7_TYPE:
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state.freq = 100 * pn7_fid_to_mult[state.fid] * sc->fsb;
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if (sc->errata_a0 &&
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if ((sc->errata & A0_ERRATA) &&
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(pn7_fid_to_mult[state.fid] % 10) == 5)
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continue;
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break;
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case PN8_TYPE:
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state.freq = 100 * pn8_fid_to_mult[state.fid >> 1] *
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sc->fsb;
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state.freq = 100 * pn8_fid_to_mult[state.fid] * sc->fsb;
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break;
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}
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@ -540,7 +596,7 @@ decode_pst(struct pn_softc *sc, uint8_t *p, int npstates)
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}
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/*
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* Fix powernow_max_states, if errata_a0 give us less states
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* Fix powernow_max_states, if errata a0 give us less states
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* than expected.
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*/
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sc->powernow_max_states = n;
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@ -596,7 +652,7 @@ pn_decode_pst(device_t dev)
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cpuid = regs[0];
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if ((cpuid & 0xfff) == 0x760)
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sc->errata_a0 = TRUE;
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sc->errata |= A0_ERRATA;
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status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
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@ -748,7 +804,7 @@ pn_decode_acpi(device_t dev, device_t perf_dev)
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do_cpuid(0x80000001, regs);
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cpuid = regs[0];
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if ((cpuid & 0xfff) == 0x760)
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sc->errata_a0 = TRUE;
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sc->errata |= A0_ERRATA;
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ctrl = 0;
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sc->sgtc = 0;
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@ -758,7 +814,7 @@ pn_decode_acpi(device_t dev, device_t perf_dev)
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case PN7_TYPE:
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state.fid = ACPI_PN7_CTRL_TO_FID(ctrl);
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state.vid = ACPI_PN7_CTRL_TO_VID(ctrl);
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if (sc->errata_a0 &&
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if ((sc->errata & A0_ERRATA) &&
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(pn7_fid_to_mult[state.fid] % 10) == 5)
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continue;
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state.freq = 100 * pn7_fid_to_mult[state.fid] * sc->fsb;
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@ -766,8 +822,7 @@ pn_decode_acpi(device_t dev, device_t perf_dev)
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case PN8_TYPE:
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state.fid = ACPI_PN8_CTRL_TO_FID(ctrl);
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state.vid = ACPI_PN8_CTRL_TO_VID(ctrl);
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state.freq = 100 * pn8_fid_to_mult[state.fid >> 1] *
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sc->fsb;
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state.freq = 100 * pn8_fid_to_mult[state.fid] * sc->fsb;
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break;
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}
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@ -853,7 +908,7 @@ pn_probe(device_t dev)
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u_int sfid, mfid, cfid;
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sc = device_get_softc(dev);
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sc->errata_a0 = FALSE;
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sc->errata = 0;
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status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
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pc = cpu_get_pcpu(dev);
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@ -890,7 +945,7 @@ pn_probe(device_t dev)
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cfid = PN8_STA_CFID(status);
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sc->pn_type = PN8_TYPE;
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sc->vid_to_volts = pn8_vid_to_volts;
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sc->fsb = rate / 100000 / pn8_fid_to_mult[cfid >> 1];
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sc->fsb = rate / 100000 / pn8_fid_to_mult[cfid];
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if (PN8_STA_SFID(status) != PN8_STA_MFID(status))
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device_set_desc(dev, "PowerNow! K8");
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