Add support for the Davicom DM9102A 10/100 ethernet controller chip.
This is just to make sure we initialize the chip correctly: we need to make the sure the port select bit in CSR6 is set properly so that we use the internal PHY for 10/100 support. (The eval boards I have also include an external HomePNA PHY, but I need to play with that more before I can support it.)
This commit is contained in:
parent
012e166b55
commit
88d739dc5f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=56295
@ -43,7 +43,7 @@
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* ASIX Electronics AX88141 (www.asix.com.tw)
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* ADMtek AL981 (www.admtek.com.tw)
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* ADMtek AN985 (www.admtek.com.tw)
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* Davicom DM9100, DM9102 (www.davicom8.com)
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* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
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*
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* Datasheets for the 21143 are available at developer.intel.com.
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* Datasheets for the clone parts can be found at their respective sites.
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@ -160,6 +160,8 @@ static struct dc_type dc_devs[] = {
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"Davicom DM9100 10/100BaseTX" },
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{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
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"Davicom DM9102 10/100BaseTX" },
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{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
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"Davicom DM9102A 10/100BaseTX" },
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{ DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
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"ADMtek AL981 10/100BaseTX" },
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{ DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
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@ -1168,7 +1170,8 @@ static void dc_setcfg(sc, media)
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if (sc->dc_type == DC_TYPE_98713)
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DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
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DC_NETCFG_SCRAMBLER));
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
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if (!DC_IS_DAVICOM(sc))
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
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DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
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} else {
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if (DC_IS_PNIC(sc)) {
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@ -1190,7 +1193,8 @@ static void dc_setcfg(sc, media)
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DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
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if (sc->dc_type == DC_TYPE_98713)
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
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if (!DC_IS_DAVICOM(sc))
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
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DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
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} else {
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if (DC_IS_PNIC(sc)) {
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@ -1289,6 +1293,9 @@ static struct dc_type *dc_devtype(dev)
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if (t->dc_did == DC_DEVICEID_82C168 &&
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rev >= DC_REVISION_82C169)
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t++;
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if (t->dc_did == DC_DEVICEID_DM9102 &&
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rev >= DC_REVISION_DM9102A)
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t++;
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return(t);
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}
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t++;
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@ -1510,7 +1517,11 @@ static int dc_attach(dev)
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}
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/* Save the cache line size. */
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sc->dc_cachesize = pci_read_config(dev, DC_PCI_CFLT, 4) & 0xFF;
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if (DC_IS_DAVICOM(sc))
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sc->dc_cachesize = 0;
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else
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sc->dc_cachesize = pci_read_config(dev,
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DC_PCI_CFLT, 4) & 0xFF;
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/* Reset the adapter. */
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dc_reset(sc);
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@ -2493,7 +2504,7 @@ static void dc_init(xsc)
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/*
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* Set cache alignment and burst length.
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*/
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if (DC_IS_ASIX(sc))
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if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
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CSR_WRITE_4(sc, DC_BUSCTL, 0);
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else
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CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
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@ -754,6 +754,13 @@ struct dc_softc {
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#define DC_DEVICEID_DM9100 0x9100
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#define DC_DEVICEID_DM9102 0x9102
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/*
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* The DM9102A has the same PCI device ID as the DM9102,
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* but a higher revision code.
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*/
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#define DC_REVISION_DM9102 0x10
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#define DC_REVISION_DM9102A 0x30
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/*
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* ADMtek vendor ID.
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*/
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@ -43,7 +43,7 @@
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* ASIX Electronics AX88141 (www.asix.com.tw)
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* ADMtek AL981 (www.admtek.com.tw)
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* ADMtek AN985 (www.admtek.com.tw)
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* Davicom DM9100, DM9102 (www.davicom8.com)
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* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
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*
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* Datasheets for the 21143 are available at developer.intel.com.
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* Datasheets for the clone parts can be found at their respective sites.
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@ -160,6 +160,8 @@ static struct dc_type dc_devs[] = {
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"Davicom DM9100 10/100BaseTX" },
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{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
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"Davicom DM9102 10/100BaseTX" },
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{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
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"Davicom DM9102A 10/100BaseTX" },
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{ DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
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"ADMtek AL981 10/100BaseTX" },
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{ DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
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@ -1168,7 +1170,8 @@ static void dc_setcfg(sc, media)
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if (sc->dc_type == DC_TYPE_98713)
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DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
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DC_NETCFG_SCRAMBLER));
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
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if (!DC_IS_DAVICOM(sc))
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
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DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
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} else {
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if (DC_IS_PNIC(sc)) {
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@ -1190,7 +1193,8 @@ static void dc_setcfg(sc, media)
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DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
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if (sc->dc_type == DC_TYPE_98713)
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
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if (!DC_IS_DAVICOM(sc))
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DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
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DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
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} else {
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if (DC_IS_PNIC(sc)) {
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@ -1289,6 +1293,9 @@ static struct dc_type *dc_devtype(dev)
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if (t->dc_did == DC_DEVICEID_82C168 &&
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rev >= DC_REVISION_82C169)
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t++;
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if (t->dc_did == DC_DEVICEID_DM9102 &&
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rev >= DC_REVISION_DM9102A)
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t++;
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return(t);
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}
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t++;
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@ -1510,7 +1517,11 @@ static int dc_attach(dev)
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}
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/* Save the cache line size. */
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sc->dc_cachesize = pci_read_config(dev, DC_PCI_CFLT, 4) & 0xFF;
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if (DC_IS_DAVICOM(sc))
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sc->dc_cachesize = 0;
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else
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sc->dc_cachesize = pci_read_config(dev,
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DC_PCI_CFLT, 4) & 0xFF;
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/* Reset the adapter. */
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dc_reset(sc);
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@ -2493,7 +2504,7 @@ static void dc_init(xsc)
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/*
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* Set cache alignment and burst length.
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*/
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if (DC_IS_ASIX(sc))
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if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
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CSR_WRITE_4(sc, DC_BUSCTL, 0);
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else
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CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
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@ -754,6 +754,13 @@ struct dc_softc {
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#define DC_DEVICEID_DM9100 0x9100
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#define DC_DEVICEID_DM9102 0x9102
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/*
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* The DM9102A has the same PCI device ID as the DM9102,
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* but a higher revision code.
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*/
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#define DC_REVISION_DM9102 0x10
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#define DC_REVISION_DM9102A 0x30
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/*
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* ADMtek vendor ID.
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*/
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