stand: Remove i386-only support fire firewire
Remove support for booting off of firewire, and for having dcons via firewire in the loader. Kernel support for these things is unchanged. Discussed on arch@ and the current state is not working (and the build was wrong to boot). Sponsored by: Netflix Discussed: https://lists.freebsd.org/archives/freebsd-arch/2022-November/000267.html Reviewed by: kevans, melifaro, emaste Differential Revision: https://reviews.freebsd.org/D37334
This commit is contained in:
Warner Losh
parent
1a1fd76d0a
commit
8a744de27e
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@ -1,6 +1,6 @@
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.\" DO NOT EDIT-- this file is @generated by tools/build/options/makeman.
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.\" $FreeBSD$
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.Dd November 16, 2022
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.Dd November 18, 2022
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.Dt SRC.CONF 5
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.Os
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.Sh NAME
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@ -996,9 +996,6 @@ option should be used rather than this in most cases.
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Enable building
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.Xr loader 8
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with support for verification based on certificates obtained from UEFI.
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.It Va WITH_LOADER_FIREWIRE
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Enable firewire support in /boot/loader on x86.
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This option is a nop on all other platforms.
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.It Va WITHOUT_LOADER_GELI
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Disable inclusion of GELI crypto support in the boot chain binaries.
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.Pp
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@ -205,7 +205,6 @@ __DEFAULT_NO_OPTIONS = \
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DTRACE_TESTS \
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EXPERIMENTAL \
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HESIOD \
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LOADER_FIREWIRE \
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LOADER_VERBOSE \
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LOADER_VERIEXEC_PASS_MANIFEST \
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LLVM_BINUTILS \
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@ -8,7 +8,6 @@ NO_OBJ=t
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# before everything else proceeds so we don't end up building against a stale
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# btxldr and ending up with a build-during-install scenario.
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SUBDIR.yes+= btx libi386
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SUBDIR.${MK_LOADER_FIREWIRE}+= libfirewire
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SUBDIR.yes+= .WAIT
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SUBDIR.yes+= mbr pmbr boot0 boot0sio boot2 cdboot gptboot \
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@ -33,9 +33,4 @@ LD_FLAGS_BIN= -static -N --gc-sections
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DO32=1
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.endif
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.if defined(LOADER_FIREWIRE_SUPPORT)
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MK_LOADER_FIREWIRE=yes
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.warning LOADER_FIREWIRE_SUPPORT deprecated, please move to WITH_LOADER_FIREWIRE
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.endif
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.include "../Makefile.inc"
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@ -1,20 +0,0 @@
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# $FreeBSD$
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.include <bsd.init.mk>
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LIB= firewire
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.PATH: ${SYSDIR}/dev/dcons ${SYSDIR}/dev/firewire
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SRCS+= firewire.c fwohci.c dconsole.c
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SRCS+= dcons.c fwcrom.c
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.include "${BOOTSRC}/veriexec.mk"
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CFLAGS+= -D_BOOT
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CFLAGS+= -I${LDRSRC}
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CFLAGS+= -I${BOOTSRC}/i386/libi386
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CFLAGS+= -Wformat -Wall
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.include <bsd.lib.mk>
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@ -1,13 +0,0 @@
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# $FreeBSD$
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# Autogenerated - do NOT edit!
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DIRDEPS = \
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include \
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include/xlocale \
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.include <dirdeps.mk>
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.if ${DEP_RELDIR} == ${_DEP_RELDIR}
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# local dependencies - needed for -jN in clean tree
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.endif
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@ -1,127 +0,0 @@
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/*-
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* Copyright (c) 2004 Hidetoshi Shimokawa
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <stand.h>
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#include <bootstrap.h>
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#include <sys/param.h>
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#include <btxv86.h>
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#include <dev/dcons/dcons.h>
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void fw_enable(void);
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void fw_poll(void);
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static void dconsole_probe(struct console *cp);
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static int dconsole_init(int arg);
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static void dconsole_putchar(int c);
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static int dconsole_getchar(void);
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static int dconsole_ischar(void);
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static int dcons_started = 0;
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#define DCONS_BUF_SIZE (64*1024)
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static struct dcons_softc sc[DCONS_NPORT];
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uint32_t dcons_paddr;
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/* The buffer must be allocated in BSS because:
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* - The dcons driver in the kernel is initialized before VM/pmap is
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* initialized, so that the buffer must be allocate in the region
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* that is mapped at the very early boot state.
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* - We expect identiy map only for regions before KERNLOAD
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* (i386:4MB amd64:1MB).
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* - It seems that heap in conventional memory(640KB) is not sufficient
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* and we move it to high address as LOADER_SUPPORT_BZIP2.
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* - BSS is placed in conventional memory.
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*/
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static char dcons_buffer[DCONS_BUF_SIZE + PAGE_SIZE];
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struct console dconsole = {
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"dcons",
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"dumb console port",
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0,
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dconsole_probe,
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dconsole_init,
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dconsole_putchar,
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dconsole_getchar,
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dconsole_ischar
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};
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#define DCONSOLE_AS_MULTI_CONSOLE 1
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static void
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dconsole_probe(struct console *cp)
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{
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/* XXX check the BIOS equipment list? */
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cp->c_flags |= (C_PRESENTIN | C_PRESENTOUT);
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#if DCONSOLE_AS_MULTI_CONSOLE
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dconsole_init(0);
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cp->c_flags |= (C_ACTIVEIN | C_ACTIVEOUT);
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#endif
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}
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static int
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dconsole_init(int arg)
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{
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char buf[16], *dbuf;
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int size;
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if (dcons_started && arg == 0)
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return 0;
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dcons_started = 1;
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size = DCONS_BUF_SIZE;
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dbuf = (char *)round_page((vm_offset_t)&dcons_buffer[0]);
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dcons_paddr = VTOP(dbuf);
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sprintf(buf, "0x%08x", dcons_paddr);
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setenv("dcons.addr", buf, 1);
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dcons_init((struct dcons_buf *)dbuf, size, sc);
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sprintf(buf, "%d", size);
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setenv("dcons.size", buf, 1);
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fw_enable();
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return(0);
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}
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static void
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dconsole_putchar(int c)
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{
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dcons_putc(&sc[0], c);
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}
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static int
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dconsole_getchar(void)
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{
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fw_poll();
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return (dcons_checkc(&sc[0]));
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}
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static int
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dconsole_ischar(void)
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{
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fw_poll();
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return (dcons_ischar(&sc[0]));
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}
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@ -1,485 +0,0 @@
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/*-
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* Copyright (c) 2004 Hidetoshi Shimokawa <simokawa@FreeBSD.ORG>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* FireWire disk device handling.
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*
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*/
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#include <stand.h>
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#include <machine/bootinfo.h>
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#include <stdarg.h>
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#include <bootstrap.h>
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#include <btxv86.h>
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#include <libi386.h>
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#include <dev/firewire/firewire.h>
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#include "fwohci.h"
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#include <dev/dcons/dcons.h>
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/* XXX */
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#define BIT4x2(x,y) uint8_t y:4, x:4
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#define BIT16x2(x,y) uint32_t y:16, x:16
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#define _KERNEL
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#include <dev/firewire/iec13213.h>
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extern uint32_t dcons_paddr;
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extern struct console dconsole;
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struct crom_src_buf {
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struct crom_src src;
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struct crom_chunk root;
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struct crom_chunk vendor;
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struct crom_chunk hw;
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/* for dcons */
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struct crom_chunk unit;
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struct crom_chunk spec;
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struct crom_chunk ver;
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};
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static int fw_init(void);
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static int fw_strategy(void *devdata, int flag, daddr_t dblk,
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size_t size, char *buf, size_t *rsize);
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static int fw_open(struct open_file *f, ...);
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static int fw_close(struct open_file *f);
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static int fw_print(int verbose);
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static void fw_cleanup(void);
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void fw_enable(void);
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struct devsw fwohci = {
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.dv_name = "FW1394", /* 7 chars at most */
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.dv_type = DEVT_NET,
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.dv_init = fw_init,
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.dv_strategy = fw_strategy,
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.dv_open = fw_open,
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.dv_close = fw_close,
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.dv_ioctl = noioctl,
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.dv_print = fw_print,
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.dv_cleanup = fw_cleanup,
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};
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static struct fwohci_softc fwinfo[MAX_OHCI];
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static int fw_initialized = 0;
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static void
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fw_probe(int index, struct fwohci_softc *sc)
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{
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int err;
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sc->state = FWOHCI_STATE_INIT;
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err = biospci_find_devclass(
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0x0c0010 /* Serial:FireWire:OHCI */,
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index /* index */,
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&sc->locator);
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if (err != 0) {
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sc->state = FWOHCI_STATE_DEAD;
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return;
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}
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biospci_write_config(sc->locator,
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0x4 /* command */,
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BIOSPCI_16BITS,
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0x6 /* enable bus master and memory mapped I/O */);
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biospci_read_config(sc->locator, 0x00 /*devid*/, BIOSPCI_32BITS,
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&sc->devid);
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biospci_read_config(sc->locator, 0x10 /*base_addr*/, BIOSPCI_32BITS,
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&sc->base_addr);
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sc->handle = (uint32_t)PTOV(sc->base_addr);
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sc->bus_id = OREAD(sc, OHCI_BUS_ID);
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return;
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}
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static int
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fw_init(void)
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{
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int i, avail;
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struct fwohci_softc *sc;
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if (fw_initialized)
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return (0);
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avail = 0;
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for (i = 0; i < MAX_OHCI; i ++) {
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sc = &fwinfo[i];
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fw_probe(i, sc);
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if (sc->state == FWOHCI_STATE_DEAD)
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break;
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avail ++;
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break;
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}
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fw_initialized = 1;
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return (0);
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}
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/*
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* Print information about OHCI chips
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*/
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static int
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fw_print(int verbose)
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{
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char line[80];
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int i, ret = 0;
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struct fwohci_softc *sc;
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printf("%s devices:", fwohci.dv_name);
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if ((ret = pager_output("\n")) != 0)
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return (ret);
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for (i = 0; i < MAX_OHCI; i ++) {
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sc = &fwinfo[i];
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if (sc->state == FWOHCI_STATE_DEAD)
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break;
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snprintf(line, sizeof(line), "%d: locator=0x%04x devid=0x%08x"
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" base_addr=0x%08x handle=0x%08x bus_id=0x%08x\n",
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i, sc->locator, sc->devid,
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sc->base_addr, sc->handle, sc->bus_id);
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ret = pager_output(line);
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if (ret != 0)
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break;
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}
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return (ret);
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}
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static int
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fw_open(struct open_file *f, ...)
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{
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#if 0
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va_list ap;
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struct i386_devdesc *dev;
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struct open_disk *od;
|
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int error;
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va_start(ap, f);
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dev = va_arg(ap, struct i386_devdesc *);
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va_end(ap);
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#endif
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return (ENXIO);
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}
|
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|
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static int
|
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fw_close(struct open_file *f)
|
||||
{
|
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return (0);
|
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}
|
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|
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static void
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fw_cleanup()
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{
|
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struct dcons_buf *db;
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/* invalidate dcons buffer */
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if (dcons_paddr) {
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db = (struct dcons_buf *)PTOV(dcons_paddr);
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db->magic = 0;
|
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}
|
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}
|
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|
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static int
|
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fw_strategy(void *devdata, int rw, daddr_t dblk, size_t size,
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||||
char *buf, size_t *rsize)
|
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{
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return (EIO);
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}
|
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|
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static void
|
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fw_init_crom(struct fwohci_softc *sc)
|
||||
{
|
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struct crom_src *src;
|
||||
|
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printf("fw_init_crom\n");
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sc->crom_src_buf = (struct crom_src_buf *)
|
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malloc(sizeof(struct crom_src_buf));
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if (sc->crom_src_buf == NULL)
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return;
|
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|
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src = &sc->crom_src_buf->src;
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bzero(src, sizeof(struct crom_src));
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|
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/* BUS info sample */
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src->hdr.info_len = 4;
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src->businfo.bus_name = CSR_BUS_NAME_IEEE1394;
|
||||
|
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src->businfo.irmc = 1;
|
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src->businfo.cmc = 1;
|
||||
src->businfo.isc = 1;
|
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src->businfo.bmc = 1;
|
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src->businfo.pmc = 0;
|
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src->businfo.cyc_clk_acc = 100;
|
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src->businfo.max_rec = sc->maxrec;
|
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src->businfo.max_rom = MAXROM_4;
|
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#define FW_GENERATION_CHANGEABLE 2
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src->businfo.generation = FW_GENERATION_CHANGEABLE;
|
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src->businfo.link_spd = sc->speed;
|
||||
|
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src->businfo.eui64.hi = sc->eui.hi;
|
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src->businfo.eui64.lo = sc->eui.lo;
|
||||
|
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STAILQ_INIT(&src->chunk_list);
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|
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sc->crom_src = src;
|
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sc->crom_root = &sc->crom_src_buf->root;
|
||||
}
|
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|
||||
static void
|
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fw_reset_crom(struct fwohci_softc *sc)
|
||||
{
|
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struct crom_src_buf *buf;
|
||||
struct crom_src *src;
|
||||
struct crom_chunk *root;
|
||||
|
||||
printf("fw_reset\n");
|
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if (sc->crom_src_buf == NULL)
|
||||
fw_init_crom(sc);
|
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|
||||
buf = sc->crom_src_buf;
|
||||
src = sc->crom_src;
|
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root = sc->crom_root;
|
||||
|
||||
STAILQ_INIT(&src->chunk_list);
|
||||
|
||||
bzero(root, sizeof(struct crom_chunk));
|
||||
crom_add_chunk(src, NULL, root, 0);
|
||||
crom_add_entry(root, CSRKEY_NCAP, 0x0083c0); /* XXX */
|
||||
/* private company_id */
|
||||
crom_add_entry(root, CSRKEY_VENDOR, CSRVAL_VENDOR_PRIVATE);
|
||||
#ifdef __DragonFly__
|
||||
crom_add_simple_text(src, root, &buf->vendor, "DragonFly Project");
|
||||
#else
|
||||
crom_add_simple_text(src, root, &buf->vendor, "FreeBSD Project");
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#define ADDR_HI(x) (((x) >> 24) & 0xffffff)
|
||||
#define ADDR_LO(x) ((x) & 0xffffff)
|
||||
|
||||
static void
|
||||
dcons_crom(struct fwohci_softc *sc)
|
||||
{
|
||||
struct crom_src_buf *buf;
|
||||
struct crom_src *src;
|
||||
struct crom_chunk *root;
|
||||
|
||||
buf = sc->crom_src_buf;
|
||||
src = sc->crom_src;
|
||||
root = sc->crom_root;
|
||||
|
||||
bzero(&buf->unit, sizeof(struct crom_chunk));
|
||||
|
||||
crom_add_chunk(src, root, &buf->unit, CROM_UDIR);
|
||||
crom_add_entry(&buf->unit, CSRKEY_SPEC, CSRVAL_VENDOR_PRIVATE);
|
||||
crom_add_simple_text(src, &buf->unit, &buf->spec, "FreeBSD");
|
||||
crom_add_entry(&buf->unit, CSRKEY_VER, DCONS_CSR_VAL_VER);
|
||||
crom_add_simple_text(src, &buf->unit, &buf->ver, "dcons");
|
||||
crom_add_entry(&buf->unit, DCONS_CSR_KEY_HI, ADDR_HI(dcons_paddr));
|
||||
crom_add_entry(&buf->unit, DCONS_CSR_KEY_LO, ADDR_LO(dcons_paddr));
|
||||
}
|
||||
|
||||
void
|
||||
fw_crom(struct fwohci_softc *sc)
|
||||
{
|
||||
struct crom_src *src;
|
||||
void *newrom;
|
||||
|
||||
fw_reset_crom(sc);
|
||||
dcons_crom(sc);
|
||||
|
||||
newrom = malloc(CROMSIZE);
|
||||
src = &sc->crom_src_buf->src;
|
||||
crom_load(src, (uint32_t *)newrom, CROMSIZE);
|
||||
if (bcmp(newrom, sc->config_rom, CROMSIZE) != 0) {
|
||||
/* Bump generation and reload. */
|
||||
src->businfo.generation++;
|
||||
|
||||
/* Handle generation count wraps. */
|
||||
if (src->businfo.generation < 2)
|
||||
src->businfo.generation = 2;
|
||||
|
||||
/* Recalculate CRC to account for generation change. */
|
||||
crom_load(src, (uint32_t *)newrom, CROMSIZE);
|
||||
bcopy(newrom, (void *)sc->config_rom, CROMSIZE);
|
||||
}
|
||||
free(newrom);
|
||||
}
|
||||
|
||||
static int
|
||||
fw_busreset(struct fwohci_softc *sc)
|
||||
{
|
||||
int count;
|
||||
|
||||
if (sc->state < FWOHCI_STATE_ENABLED) {
|
||||
printf("fwohci not enabled\n");
|
||||
return(CMD_OK);
|
||||
}
|
||||
fw_crom(sc);
|
||||
fwohci_ibr(sc);
|
||||
count = 0;
|
||||
while (sc->state< FWOHCI_STATE_NORMAL) {
|
||||
fwohci_poll(sc);
|
||||
count ++;
|
||||
if (count > 1000) {
|
||||
printf("give up to wait bus initialize\n");
|
||||
return (-1);
|
||||
}
|
||||
}
|
||||
printf("poll count = %d\n", count);
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
fw_enable(void)
|
||||
{
|
||||
struct fwohci_softc *sc;
|
||||
int i;
|
||||
|
||||
if (fw_initialized == 0)
|
||||
fw_init();
|
||||
|
||||
for (i = 0; i < MAX_OHCI; i ++) {
|
||||
sc = &fwinfo[i];
|
||||
if (sc->state != FWOHCI_STATE_INIT)
|
||||
break;
|
||||
|
||||
sc->config_rom = (uint32_t *)
|
||||
(((uint32_t)sc->config_rom_buf
|
||||
+ (CROMSIZE - 1)) & ~(CROMSIZE - 1));
|
||||
#if 0
|
||||
printf("configrom: %08p %08p\n",
|
||||
sc->config_rom_buf, sc->config_rom);
|
||||
#endif
|
||||
if (fwohci_init(sc, 0) == 0) {
|
||||
sc->state = FWOHCI_STATE_ENABLED;
|
||||
fw_busreset(sc);
|
||||
} else
|
||||
sc->state = FWOHCI_STATE_DEAD;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
fw_poll(void)
|
||||
{
|
||||
struct fwohci_softc *sc;
|
||||
int i;
|
||||
|
||||
if (fw_initialized == 0)
|
||||
return;
|
||||
|
||||
for (i = 0; i < MAX_OHCI; i ++) {
|
||||
sc = &fwinfo[i];
|
||||
if (sc->state < FWOHCI_STATE_ENABLED)
|
||||
break;
|
||||
fwohci_poll(sc);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0 /* for debug */
|
||||
static int
|
||||
fw_busreset_cmd(int argc, char *argv[])
|
||||
{
|
||||
struct fwohci_softc *sc;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MAX_OHCI; i ++) {
|
||||
sc = &fwinfo[i];
|
||||
if (sc->state < FWOHCI_STATE_INIT)
|
||||
break;
|
||||
fw_busreset(sc);
|
||||
}
|
||||
return(CMD_OK);
|
||||
}
|
||||
|
||||
static int
|
||||
fw_poll_cmd(int argc, char *argv[])
|
||||
{
|
||||
fw_poll();
|
||||
return(CMD_OK);
|
||||
}
|
||||
|
||||
static int
|
||||
fw_enable_cmd(int argc, char *argv[])
|
||||
{
|
||||
fw_print(0);
|
||||
fw_enable();
|
||||
return(CMD_OK);
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
dcons_enable(int argc, char *argv[])
|
||||
{
|
||||
dconsole.c_init(0);
|
||||
fw_enable();
|
||||
dconsole.c_flags |= C_ACTIVEIN | C_ACTIVEOUT;
|
||||
return(CMD_OK);
|
||||
}
|
||||
|
||||
static int
|
||||
dcons_read(int argc, char *argv[])
|
||||
{
|
||||
char c;
|
||||
while (dconsole.c_ready()) {
|
||||
c = dconsole.c_in();
|
||||
printf("%c", c);
|
||||
}
|
||||
printf("\r\n");
|
||||
return(CMD_OK);
|
||||
}
|
||||
|
||||
static int
|
||||
dcons_write(int argc, char *argv[])
|
||||
{
|
||||
int len, i;
|
||||
if (argc < 2)
|
||||
return(CMD_OK);
|
||||
|
||||
len = strlen(argv[1]);
|
||||
for (i = 0; i < len; i ++)
|
||||
dconsole.c_out(argv[1][i]);
|
||||
dconsole.c_out('\r');
|
||||
dconsole.c_out('\n');
|
||||
return(CMD_OK);
|
||||
}
|
||||
COMMAND_SET(firewire, "firewire", "enable firewire", fw_enable_cmd);
|
||||
COMMAND_SET(fwbusreset, "fwbusreset", "firewire busreset", fw_busreset_cmd);
|
||||
COMMAND_SET(fwpoll, "fwpoll", "firewire poll", fw_poll_cmd);
|
||||
COMMAND_SET(dcons, "dcons", "enable dcons", dcons_enable);
|
||||
COMMAND_SET(dread, "dread", "read from dcons", dcons_read);
|
||||
COMMAND_SET(dwrite, "dwrite", "write to dcons", dcons_write);
|
||||
#endif
|
||||
|
|
@ -1,474 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2003 Hidetoshi Shimokawa
|
||||
* Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the acknowledgement as bellow:
|
||||
*
|
||||
* This product includes software developed by K. Kobayashi and H. Shimokawa
|
||||
*
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stand.h>
|
||||
#include <btxv86.h>
|
||||
#include <bootstrap.h>
|
||||
|
||||
#include <dev/firewire/firewire.h>
|
||||
#include "fwohci.h"
|
||||
#include <dev/firewire/fwohcireg.h>
|
||||
#include <dev/firewire/firewire_phy.h>
|
||||
|
||||
static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
|
||||
static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
|
||||
int firewire_debug=0;
|
||||
|
||||
#if 0
|
||||
#define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__)
|
||||
#else
|
||||
#define device_printf(a, x, ...)
|
||||
#endif
|
||||
|
||||
#define device_t int
|
||||
#define DELAY(x) delay(x)
|
||||
|
||||
#define MAX_SPEED 3
|
||||
#define MAXREC(x) (2 << (x))
|
||||
char *linkspeed[] = {
|
||||
"S100", "S200", "S400", "S800",
|
||||
"S1600", "S3200", "undef", "undef"
|
||||
};
|
||||
|
||||
/*
|
||||
* Communication with PHY device
|
||||
*/
|
||||
static uint32_t
|
||||
fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
|
||||
{
|
||||
uint32_t fun;
|
||||
|
||||
addr &= 0xf;
|
||||
data &= 0xff;
|
||||
|
||||
fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
|
||||
OWRITE(sc, OHCI_PHYACCESS, fun);
|
||||
DELAY(100);
|
||||
|
||||
return(fwphy_rddata( sc, addr));
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
fwphy_rddata(struct fwohci_softc *sc, u_int addr)
|
||||
{
|
||||
uint32_t fun, stat;
|
||||
u_int i, retry = 0;
|
||||
|
||||
addr &= 0xf;
|
||||
#define MAX_RETRY 100
|
||||
again:
|
||||
OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
|
||||
fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
|
||||
OWRITE(sc, OHCI_PHYACCESS, fun);
|
||||
for ( i = 0 ; i < MAX_RETRY ; i ++ ){
|
||||
fun = OREAD(sc, OHCI_PHYACCESS);
|
||||
if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
|
||||
break;
|
||||
DELAY(100);
|
||||
}
|
||||
if(i >= MAX_RETRY) {
|
||||
if (firewire_debug)
|
||||
device_printf(sc->fc.dev, "phy read failed(1).\n");
|
||||
if (++retry < MAX_RETRY) {
|
||||
DELAY(100);
|
||||
goto again;
|
||||
}
|
||||
}
|
||||
/* Make sure that SCLK is started */
|
||||
stat = OREAD(sc, FWOHCI_INTSTAT);
|
||||
if ((stat & OHCI_INT_REG_FAIL) != 0 ||
|
||||
((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
|
||||
if (firewire_debug)
|
||||
device_printf(sc->fc.dev, "phy read failed(2).\n");
|
||||
if (++retry < MAX_RETRY) {
|
||||
DELAY(100);
|
||||
goto again;
|
||||
}
|
||||
}
|
||||
if (firewire_debug || retry >= MAX_RETRY)
|
||||
device_printf(sc->fc.dev,
|
||||
"fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
|
||||
#undef MAX_RETRY
|
||||
return((fun >> PHYDEV_RDDATA )& 0xff);
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
|
||||
{
|
||||
uint32_t reg, reg2;
|
||||
int e1394a = 1;
|
||||
int nport, speed;
|
||||
/*
|
||||
* probe PHY parameters
|
||||
* 0. to prove PHY version, whether compliance of 1394a.
|
||||
* 1. to probe maximum speed supported by the PHY and
|
||||
* number of port supported by core-logic.
|
||||
* It is not actually available port on your PC .
|
||||
*/
|
||||
OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
|
||||
DELAY(500);
|
||||
|
||||
reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
|
||||
|
||||
if((reg >> 5) != 7 ){
|
||||
nport = reg & FW_PHY_NP;
|
||||
speed = reg & FW_PHY_SPD >> 6;
|
||||
if (speed > MAX_SPEED) {
|
||||
device_printf(dev, "invalid speed %d (fixed to %d).\n",
|
||||
speed, MAX_SPEED);
|
||||
speed = MAX_SPEED;
|
||||
}
|
||||
device_printf(dev,
|
||||
"Phy 1394 only %s, %d ports.\n",
|
||||
linkspeed[speed], nport);
|
||||
}else{
|
||||
reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
|
||||
nport = reg & FW_PHY_NP;
|
||||
speed = (reg2 & FW_PHY_ESPD) >> 5;
|
||||
if (speed > MAX_SPEED) {
|
||||
device_printf(dev, "invalid speed %d (fixed to %d).\n",
|
||||
speed, MAX_SPEED);
|
||||
speed = MAX_SPEED;
|
||||
}
|
||||
device_printf(dev,
|
||||
"Phy 1394a available %s, %d ports.\n",
|
||||
linkspeed[speed], nport);
|
||||
|
||||
/* check programPhyEnable */
|
||||
reg2 = fwphy_rddata(sc, 5);
|
||||
#if 0
|
||||
if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
|
||||
#else /* XXX force to enable 1394a */
|
||||
if (e1394a) {
|
||||
#endif
|
||||
if (firewire_debug)
|
||||
device_printf(dev,
|
||||
"Enable 1394a Enhancements\n");
|
||||
/* enable EAA EMC */
|
||||
reg2 |= 0x03;
|
||||
/* set aPhyEnhanceEnable */
|
||||
OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
|
||||
OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
|
||||
} else {
|
||||
/* for safe */
|
||||
reg2 &= ~0x83;
|
||||
}
|
||||
reg2 = fwphy_wrdata(sc, 5, reg2);
|
||||
}
|
||||
sc->speed = speed;
|
||||
|
||||
reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
|
||||
if((reg >> 5) == 7 ){
|
||||
reg = fwphy_rddata(sc, 4);
|
||||
reg |= 1 << 6;
|
||||
fwphy_wrdata(sc, 4, reg);
|
||||
reg = fwphy_rddata(sc, 4);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
fwohci_reset(struct fwohci_softc *sc, device_t dev)
|
||||
{
|
||||
int i, max_rec, speed;
|
||||
uint32_t reg, reg2;
|
||||
|
||||
/* Disable interrupts */
|
||||
OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
|
||||
|
||||
/* FLUSH FIFO and reset Transmitter/Receiver */
|
||||
OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
|
||||
if (firewire_debug)
|
||||
device_printf(dev, "resetting OHCI...");
|
||||
i = 0;
|
||||
while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
|
||||
if (i++ > 100) break;
|
||||
DELAY(1000);
|
||||
}
|
||||
if (firewire_debug)
|
||||
printf("done (loop=%d)\n", i);
|
||||
|
||||
/* Probe phy */
|
||||
fwohci_probe_phy(sc, dev);
|
||||
|
||||
/* Probe link */
|
||||
reg = OREAD(sc, OHCI_BUS_OPT);
|
||||
reg2 = reg | OHCI_BUSFNC;
|
||||
max_rec = (reg & 0x0000f000) >> 12;
|
||||
speed = (reg & 0x00000007);
|
||||
device_printf(dev, "Link %s, max_rec %d bytes.\n",
|
||||
linkspeed[speed], MAXREC(max_rec));
|
||||
/* XXX fix max_rec */
|
||||
sc->maxrec = sc->speed + 8;
|
||||
if (max_rec != sc->maxrec) {
|
||||
reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12);
|
||||
device_printf(dev, "max_rec %d -> %d\n",
|
||||
MAXREC(max_rec), MAXREC(sc->maxrec));
|
||||
}
|
||||
if (firewire_debug)
|
||||
device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
|
||||
OWRITE(sc, OHCI_BUS_OPT, reg2);
|
||||
|
||||
/* Initialize registers */
|
||||
OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]);
|
||||
OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom));
|
||||
#if 0
|
||||
OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
|
||||
#endif
|
||||
OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
|
||||
OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
|
||||
#if 0
|
||||
OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
|
||||
#endif
|
||||
|
||||
/* Enable link */
|
||||
OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
|
||||
}
|
||||
|
||||
int
|
||||
fwohci_init(struct fwohci_softc *sc, device_t dev)
|
||||
{
|
||||
int i, mver;
|
||||
uint32_t reg;
|
||||
uint8_t ui[8];
|
||||
|
||||
/* OHCI version */
|
||||
reg = OREAD(sc, OHCI_VERSION);
|
||||
mver = (reg >> 16) & 0xff;
|
||||
device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
|
||||
mver, reg & 0xff, (reg>>24) & 1);
|
||||
if (mver < 1 || mver > 9) {
|
||||
device_printf(dev, "invalid OHCI version\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
/* Available Isochronous DMA channel probe */
|
||||
OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
|
||||
OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
|
||||
reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
|
||||
OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
|
||||
OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
|
||||
for (i = 0; i < 0x20; i++)
|
||||
if ((reg & (1 << i)) == 0)
|
||||
break;
|
||||
device_printf(dev, "No. of Isochronous channels is %d.\n", i);
|
||||
if (i == 0)
|
||||
return (ENXIO);
|
||||
|
||||
#if 0
|
||||
/* SID receive buffer must align 2^11 */
|
||||
#define OHCI_SIDSIZE (1 << 11)
|
||||
sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
|
||||
&sc->sid_dma, BUS_DMA_WAITOK);
|
||||
if (sc->sid_buf == NULL) {
|
||||
device_printf(dev, "sid_buf alloc failed.");
|
||||
return ENOMEM;
|
||||
}
|
||||
#endif
|
||||
|
||||
sc->eui.hi = OREAD(sc, FWOHCIGUID_H);
|
||||
sc->eui.lo = OREAD(sc, FWOHCIGUID_L);
|
||||
for( i = 0 ; i < 8 ; i ++)
|
||||
ui[i] = FW_EUI64_BYTE(&sc->eui,i);
|
||||
device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
|
||||
fwohci_reset(sc, dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
fwohci_ibr(struct fwohci_softc *sc)
|
||||
{
|
||||
uint32_t fun;
|
||||
|
||||
device_printf(sc->dev, "Initiate bus reset\n");
|
||||
|
||||
/*
|
||||
* Make sure our cached values from the config rom are
|
||||
* initialised.
|
||||
*/
|
||||
OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
|
||||
OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
|
||||
|
||||
/*
|
||||
* Set root hold-off bit so that non cyclemaster capable node
|
||||
* shouldn't became the root node.
|
||||
*/
|
||||
#if 1
|
||||
fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
|
||||
fun |= FW_PHY_IBR;
|
||||
fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
|
||||
#else /* Short bus reset */
|
||||
fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
|
||||
fun |= FW_PHY_ISBR;
|
||||
fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
fwohci_sid(struct fwohci_softc *sc)
|
||||
{
|
||||
uint32_t node_id;
|
||||
int plen;
|
||||
|
||||
node_id = OREAD(sc, FWOHCI_NODEID);
|
||||
if (!(node_id & OHCI_NODE_VALID)) {
|
||||
#if 0
|
||||
printf("Bus reset failure\n");
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
/* Enable bus reset interrupt */
|
||||
OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
|
||||
/* Allow async. request to us */
|
||||
OWRITE(sc, OHCI_AREQHI, 1 << 31);
|
||||
/* XXX insecure ?? */
|
||||
OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
|
||||
OWRITE(sc, OHCI_PREQLO, 0xffffffff);
|
||||
OWRITE(sc, OHCI_PREQUPPER, 0x10000);
|
||||
/* Set ATRetries register */
|
||||
OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
|
||||
/*
|
||||
** Checking whether the node is root or not. If root, turn on
|
||||
** cycle master.
|
||||
*/
|
||||
plen = OREAD(sc, OHCI_SID_CNT);
|
||||
device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
|
||||
node_id, (plen >> 16) & 0xff);
|
||||
if (node_id & OHCI_NODE_ROOT) {
|
||||
device_printf(sc->dev, "CYCLEMASTER mode\n");
|
||||
OWRITE(sc, OHCI_LNKCTL,
|
||||
OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
|
||||
} else {
|
||||
device_printf(sc->dev, "non CYCLEMASTER mode\n");
|
||||
OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
|
||||
OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
|
||||
}
|
||||
if (plen & OHCI_SID_ERR) {
|
||||
device_printf(fc->dev, "SID Error\n");
|
||||
return;
|
||||
}
|
||||
device_printf(sc->dev, "bus reset phase done\n");
|
||||
sc->state = FWOHCI_STATE_NORMAL;
|
||||
}
|
||||
|
||||
static void
|
||||
fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
|
||||
{
|
||||
#undef OHCI_DEBUG
|
||||
#ifdef OHCI_DEBUG
|
||||
#if 0
|
||||
if(stat & OREAD(sc, FWOHCI_INTMASK))
|
||||
#else
|
||||
if (1)
|
||||
#endif
|
||||
device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
|
||||
stat & OHCI_INT_EN ? "DMA_EN ":"",
|
||||
stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
|
||||
stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
|
||||
stat & OHCI_INT_ERR ? "INT_ERR ":"",
|
||||
stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
|
||||
stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
|
||||
stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
|
||||
stat & OHCI_INT_CYC_START ? "CYC_START ":"",
|
||||
stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
|
||||
stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
|
||||
stat & OHCI_INT_PHY_SID ? "SID ":"",
|
||||
stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
|
||||
stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
|
||||
stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
|
||||
stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
|
||||
stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
|
||||
stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
|
||||
stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
|
||||
stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
|
||||
stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
|
||||
stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
|
||||
stat, OREAD(sc, FWOHCI_INTMASK)
|
||||
);
|
||||
#endif
|
||||
/* Bus reset */
|
||||
if(stat & OHCI_INT_PHY_BUS_R ){
|
||||
device_printf(fc->dev, "BUS reset\n");
|
||||
if (sc->state == FWOHCI_STATE_BUSRESET)
|
||||
goto busresetout;
|
||||
sc->state = FWOHCI_STATE_BUSRESET;
|
||||
/* Disable bus reset interrupt until sid recv. */
|
||||
OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
|
||||
|
||||
OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
|
||||
OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
|
||||
|
||||
OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
|
||||
OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
|
||||
} else if (sc->state == FWOHCI_STATE_BUSRESET) {
|
||||
fwohci_sid(sc);
|
||||
}
|
||||
busresetout:
|
||||
return;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
fwochi_check_stat(struct fwohci_softc *sc)
|
||||
{
|
||||
uint32_t stat;
|
||||
|
||||
stat = OREAD(sc, FWOHCI_INTSTAT);
|
||||
if (stat == 0xffffffff) {
|
||||
device_printf(sc->fc.dev,
|
||||
"device physically ejected?\n");
|
||||
return(stat);
|
||||
}
|
||||
if (stat)
|
||||
OWRITE(sc, FWOHCI_INTSTATCLR, stat);
|
||||
return(stat);
|
||||
}
|
||||
|
||||
void
|
||||
fwohci_poll(struct fwohci_softc *sc)
|
||||
{
|
||||
uint32_t stat;
|
||||
|
||||
stat = fwochi_check_stat(sc);
|
||||
if (stat != 0xffffffff)
|
||||
fwohci_intr_body(sc, stat, 1);
|
||||
}
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2007 Hidetoshi Shimokawa
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the acknowledgement as bellow:
|
||||
*
|
||||
* This product includes software developed by K. Kobayashi and H. Shimokawa
|
||||
*
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#define MAX_OHCI 5
|
||||
#define CROMSIZE 0x400
|
||||
|
||||
struct fwohci_softc {
|
||||
uint32_t locator;
|
||||
uint32_t devid;
|
||||
uint32_t base_addr;
|
||||
uint32_t bus_id;
|
||||
uint32_t handle;
|
||||
int32_t state;
|
||||
struct crom_src_buf *crom_src_buf;
|
||||
struct crom_src *crom_src;
|
||||
struct crom_chunk *crom_root;
|
||||
struct fw_eui64 eui;
|
||||
int speed;
|
||||
int maxrec;
|
||||
uint32_t *config_rom;
|
||||
char config_rom_buf[CROMSIZE*2]; /* double size for alignment */
|
||||
};
|
||||
|
||||
int fwohci_init(struct fwohci_softc *, int);
|
||||
void fwohci_ibr(struct fwohci_softc *);
|
||||
void fwohci_poll(struct fwohci_softc *);
|
||||
|
||||
#define FWOHCI_STATE_DEAD (-1)
|
||||
#define FWOHCI_STATE_INIT 0
|
||||
#define FWOHCI_STATE_ENABLED 1
|
||||
#define FWOHCI_STATE_BUSRESET 2
|
||||
#define FWOHCI_STATE_NORMAL 3
|
||||
|
||||
#define OREAD(f, o) (*(volatile uint32_t *)((f)->handle + (o)))
|
||||
#define OWRITE(f, o, v) (*(volatile uint32_t *)((f)->handle + (o)) = (v))
|
||||
|
||||
#define OHCI_VERSION 0x00
|
||||
#define OHCI_ATRETRY 0x08
|
||||
#define OHCI_CROMHDR 0x18
|
||||
#define OHCI_BUS_ID 0x1c
|
||||
#define OHCI_BUS_OPT 0x20
|
||||
#define OHCI_BUSIRMC (1U << 31)
|
||||
#define OHCI_BUSCMC (1 << 30)
|
||||
#define OHCI_BUSISC (1 << 29)
|
||||
#define OHCI_BUSBMC (1 << 28)
|
||||
#define OHCI_BUSPMC (1 << 27)
|
||||
#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
|
||||
OHCI_BUSBMC | OHCI_BUSPMC
|
||||
|
||||
#define OHCI_EUID_HI 0x24
|
||||
#define OHCI_EUID_LO 0x28
|
||||
|
||||
#define OHCI_CROMPTR 0x34
|
||||
#define OHCI_HCCCTL 0x50
|
||||
#define OHCI_HCCCTLCLR 0x54
|
||||
#define OHCI_AREQHI 0x100
|
||||
#define OHCI_AREQHICLR 0x104
|
||||
#define OHCI_AREQLO 0x108
|
||||
#define OHCI_AREQLOCLR 0x10c
|
||||
#define OHCI_PREQHI 0x110
|
||||
#define OHCI_PREQHICLR 0x114
|
||||
#define OHCI_PREQLO 0x118
|
||||
#define OHCI_PREQLOCLR 0x11c
|
||||
#define OHCI_PREQUPPER 0x120
|
||||
|
||||
#define OHCI_SID_BUF 0x64
|
||||
#define OHCI_SID_CNT 0x68
|
||||
#define OHCI_SID_ERR (1U << 31)
|
||||
#define OHCI_SID_CNT_MASK 0xffc
|
||||
|
||||
#define OHCI_IT_STAT 0x90
|
||||
#define OHCI_IT_STATCLR 0x94
|
||||
#define OHCI_IT_MASK 0x98
|
||||
#define OHCI_IT_MASKCLR 0x9c
|
||||
|
||||
#define OHCI_IR_STAT 0xa0
|
||||
#define OHCI_IR_STATCLR 0xa4
|
||||
#define OHCI_IR_MASK 0xa8
|
||||
#define OHCI_IR_MASKCLR 0xac
|
||||
|
||||
#define OHCI_LNKCTL 0xe0
|
||||
#define OHCI_LNKCTLCLR 0xe4
|
||||
|
||||
#define OHCI_PHYACCESS 0xec
|
||||
#define OHCI_CYCLETIMER 0xf0
|
||||
|
||||
#define OHCI_DMACTL(off) (off)
|
||||
#define OHCI_DMACTLCLR(off) (off + 4)
|
||||
#define OHCI_DMACMD(off) (off + 0xc)
|
||||
#define OHCI_DMAMATCH(off) (off + 0x10)
|
||||
|
||||
#define OHCI_ATQOFF 0x180
|
||||
#define OHCI_ATQCTL OHCI_ATQOFF
|
||||
#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
|
||||
#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
|
||||
#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
|
||||
|
||||
#define OHCI_ATSOFF 0x1a0
|
||||
#define OHCI_ATSCTL OHCI_ATSOFF
|
||||
#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
|
||||
#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
|
||||
#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
|
||||
|
||||
#define OHCI_ARQOFF 0x1c0
|
||||
#define OHCI_ARQCTL OHCI_ARQOFF
|
||||
#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
|
||||
#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
|
||||
#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
|
||||
|
||||
#define OHCI_ARSOFF 0x1e0
|
||||
#define OHCI_ARSCTL OHCI_ARSOFF
|
||||
#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
|
||||
#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
|
||||
#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
|
||||
|
||||
#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
|
||||
#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
|
||||
#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
|
||||
#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
|
||||
|
||||
#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
|
||||
#define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
|
||||
#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
|
||||
#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
|
||||
#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
|
||||
|
|
@ -54,11 +54,6 @@ HAVE_BCACHE= yes
|
|||
HAVE_PNP= yes
|
||||
HAVE_ISABUS= yes
|
||||
|
||||
.if ${MK_LOADER_FIREWIRE} == "yes"
|
||||
CFLAGS+= -DLOADER_FIREWIRE_SUPPORT
|
||||
LIBFIREWIRE= ${BOOTOBJ}/i386/libfirewire/libfirewire.a
|
||||
.endif
|
||||
|
||||
.if ${MK_LOADER_ZFS} == "yes"
|
||||
CFLAGS.main.c+= -I${SYSDIR}/contrib/openzfs/include
|
||||
CFLAGS.main.c+= -I${SYSDIR}/contrib/openzfs/include/os/freebsd/zfs
|
||||
|
|
@ -127,8 +122,8 @@ FILESMODE_${LOADER}= ${BINMODE} -b
|
|||
# files.
|
||||
LDFLAGS+= ${BTXCRT}
|
||||
|
||||
DPADD= ${LDR_INTERP32} ${LIBFIREWIRE} ${LIBI386} ${LIBSA32}
|
||||
LDADD= ${LDR_INTERP32} ${LIBFIREWIRE} ${LIBI386} ${LIBSA32}
|
||||
DPADD= ${LDR_INTERP32} ${LIBI386} ${LIBSA32}
|
||||
LDADD= ${LDR_INTERP32} ${LIBI386} ${LIBSA32}
|
||||
|
||||
.if ${MACHINE_CPUARCH} == "amd64"
|
||||
CFLAGS+= -DLOADER_PREFER_AMD64
|
||||
|
|
|
|||
|
|
@ -45,9 +45,6 @@ __FBSDID("$FreeBSD$");
|
|||
* XXX as libi386 and biosboot merge, some of these can become linker sets.
|
||||
*/
|
||||
|
||||
#if defined(LOADER_FIREWIRE_SUPPORT)
|
||||
extern struct devsw fwohci;
|
||||
#endif
|
||||
extern struct devsw vdisk_dev;
|
||||
|
||||
/* Exported for libsa */
|
||||
|
|
@ -57,9 +54,6 @@ struct devsw *devsw[] = {
|
|||
&bioshd,
|
||||
#if defined(LOADER_NFS_SUPPORT) || defined(LOADER_TFTP_SUPPORT)
|
||||
&pxedisk,
|
||||
#endif
|
||||
#if defined(LOADER_FIREWIRE_SUPPORT)
|
||||
&fwohci,
|
||||
#endif
|
||||
&vdisk_dev,
|
||||
#if defined(LOADER_ZFS_SUPPORT)
|
||||
|
|
@ -138,18 +132,12 @@ struct file_format *file_formats[] = {
|
|||
*/
|
||||
extern struct console vidconsole;
|
||||
extern struct console comconsole;
|
||||
#if defined(LOADER_FIREWIRE_SUPPORT)
|
||||
extern struct console dconsole;
|
||||
#endif
|
||||
extern struct console nullconsole;
|
||||
extern struct console spinconsole;
|
||||
|
||||
struct console *consoles[] = {
|
||||
&vidconsole,
|
||||
&comconsole,
|
||||
#if defined(LOADER_FIREWIRE_SUPPORT)
|
||||
&dconsole,
|
||||
#endif
|
||||
&nullconsole,
|
||||
&spinconsole,
|
||||
NULL
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@ main(void)
|
|||
*/
|
||||
bios_getmem();
|
||||
|
||||
#if defined(LOADER_BZIP2_SUPPORT) || defined(LOADER_FIREWIRE_SUPPORT) || \
|
||||
#if defined(LOADER_BZIP2_SUPPORT) || \
|
||||
defined(LOADER_GPT_SUPPORT) || defined(LOADER_ZFS_SUPPORT)
|
||||
if (high_heap_size > 0) {
|
||||
heap_top = PTOV(high_heap_base + high_heap_size);
|
||||
|
|
|
|||
|
|
@ -96,12 +96,3 @@ for i in \
|
|||
ta=${i##*/}
|
||||
dobuild $ta _.boot.${ta}.no_zfs.log "MK_LOADER_ZFS=no"
|
||||
done
|
||||
|
||||
# Build with firewire
|
||||
for i in \
|
||||
amd64/amd64 \
|
||||
i386/i386 \
|
||||
; do
|
||||
ta=${i##*/}
|
||||
dobuild $ta _.boot.${ta}.firewire.log "MK_LOADER_FIREWIRE=yes"
|
||||
done
|
||||
|
|
|
|||
|
|
@ -1,3 +0,0 @@
|
|||
.\" $FreeBSD$
|
||||
Enable firewire support in /boot/loader on x86.
|
||||
This option is a nop on all other platforms.
|
||||
Loading…
Reference in New Issue
Block a user