powerpc/booke: Fix TLB1 entry accounting
It's possible, with per-CPU mappings, for TLB1 indices to get out of sync. This presents a problem when trying to insert an entry into TLB1 of all CPUs. Currently that's done by assuming (hoping) that the TLBs are perfectly synced, and inserting to the same index for all CPUs. However, with aforementioned private mappings, this can result in overwriting mappings on the other CPUs. An example: CPU0 CPU1 <setup all mappings> <idle> 3 private mappings kick off CPU 1 initialize shared mappings (3 indices low) Load kernel module, triggers 20 new mappings Sync mappings at N-3 initialize 3 private mappings. At this point, CPU 1 has all the correct mappings, while CPU 0 is missing 3 mappings that were shared across to CPU 1. When CPU 0 tries to access memory in one of the overwritten mappings, it hangs while tripping through the TLB miss handler. Device mappings are not stored in any page table. This fixes by introducing a '-1' index for tlb1_write_entry_int(), so each CPU searches for an available index private to itself. MFC after: 3 weeks
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parent
ca64a75eda
commit
8b079fcca7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=354235
@ -1881,7 +1881,7 @@ mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
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}
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#ifdef SMP
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void
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void
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tlb1_ap_prep(void)
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{
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tlb_entry_t *e, tmp;
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@ -3776,14 +3776,34 @@ struct tlbwrite_args {
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unsigned int idx;
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};
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static uint32_t
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tlb1_find_free(void)
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{
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tlb_entry_t e;
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int i;
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for (i = 0; i < TLB1_ENTRIES; i++) {
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tlb1_read_entry(&e, i);
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if ((e.mas1 & MAS1_VALID) == 0)
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return (i);
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}
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return (-1);
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}
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static void
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tlb1_write_entry_int(void *arg)
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{
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struct tlbwrite_args *args = arg;
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uint32_t mas0;
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uint32_t idx, mas0;
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idx = args->idx;
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if (idx == -1) {
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idx = tlb1_find_free();
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if (idx == -1)
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panic("No free TLB1 entries!\n");
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}
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/* Select entry */
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(args->idx);
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
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mtspr(SPR_MAS0, mas0);
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mtspr(SPR_MAS1, args->e->mas1);
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@ -3897,10 +3917,9 @@ tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
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uint32_t ts, tid;
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int tsize, index;
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/* First try to update an existing entry. */
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for (index = 0; index < TLB1_ENTRIES; index++) {
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tlb1_read_entry(&e, index);
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if ((e.mas1 & MAS1_VALID) == 0)
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break;
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/* Check if we're just updating the flags, and update them. */
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if (e.phys == pa && e.virt == va && e.size == size) {
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e.mas2 = (va & MAS2_EPN_MASK) | flags;
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@ -3908,10 +3927,6 @@ tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
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return (0);
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}
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}
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if (index >= TLB1_ENTRIES) {
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printf("tlb1_set_entry: TLB1 full!\n");
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return (-1);
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}
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/* Convert size to TSIZE */
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tsize = size2tsize(size);
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@ -3931,13 +3946,8 @@ tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
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e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
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e.mas7 = (pa >> 32) & MAS7_RPN;
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tlb1_write_entry(&e, index);
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tlb1_write_entry(&e, -1);
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/*
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* XXX in general TLB1 updates should be propagated between CPUs,
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* since current design assumes to have the same TLB1 set-up on all
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* cores.
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*/
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return (0);
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}
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