Remove redundant data from pci host generic
The bus tag and handle fields are already stored in the resource. Use this with the bus_read/bus_write helper macros. Sponsored by: Arm Ltd
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078a69abcb
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8bc94f256e
@ -168,16 +168,14 @@ static void
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bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val)
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{
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bus_space_write_4(sc->base.base.bst, sc->base.base.bsh, reg,
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htole32(val));
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bus_write_4(sc->base.base.res, reg, htole32(val));
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}
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static uint32_t
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bcm_pcib_read_reg(struct bcm_pcib_softc *sc, uint32_t reg)
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{
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return (le32toh(bus_space_read_4(sc->base.base.bst, sc->base.base.bsh,
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reg)));
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return (le32toh(bus_read_4(sc->base.base.res, reg)));
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}
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static void
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@ -318,8 +316,6 @@ bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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int bytes)
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{
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struct bcm_pcib_softc *sc;
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bus_space_handle_t h;
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bus_space_tag_t t;
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bus_addr_t offset;
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uint32_t data;
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@ -330,18 +326,15 @@ bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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mtx_lock(&sc->config_mtx);
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offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg);
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t = sc->base.base.bst;
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h = sc->base.base.bsh;
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switch (bytes) {
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case 1:
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data = bus_space_read_1(t, h, offset);
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data = bus_read_1(sc->base.base.res, offset);
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break;
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case 2:
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data = le16toh(bus_space_read_2(t, h, offset));
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data = le16toh(bus_read_2(sc->base.base.res, offset));
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break;
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case 4:
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data = le32toh(bus_space_read_4(t, h, offset));
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data = le32toh(bus_read_4(sc->base.base.res, offset));
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break;
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default:
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data = ~0U;
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@ -357,8 +350,6 @@ bcm_pcib_write_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, uint32_t val, int bytes)
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{
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struct bcm_pcib_softc *sc;
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bus_space_handle_t h;
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bus_space_tag_t t;
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uint32_t offset;
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sc = device_get_softc(dev);
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@ -368,18 +359,15 @@ bcm_pcib_write_config(device_t dev, u_int bus, u_int slot,
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mtx_lock(&sc->config_mtx);
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offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg);
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t = sc->base.base.bst;
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h = sc->base.base.bsh;
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switch (bytes) {
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case 1:
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bus_space_write_1(t, h, offset, val);
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bus_write_1(sc->base.base.res, offset, val);
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break;
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case 2:
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bus_space_write_2(t, h, offset, htole16(val));
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bus_write_2(sc->base.base.res, offset, htole16(val));
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break;
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case 4:
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bus_space_write_4(t, h, offset, htole32(val));
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bus_write_4(sc->base.base.res, offset, htole32(val));
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break;
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default:
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break;
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@ -113,8 +113,8 @@ n1sdp_init(struct generic_pcie_n1sdp_softc *sc)
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shared_data = (struct pcie_discovery_data *)vaddr;
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paddr_rc = (vm_offset_t)shared_data->rc_base_addr;
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error = bus_space_map(sc->acpi.base.bst, paddr_rc, PCI_CFG_SPACE_SIZE,
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0, &sc->n1_bsh);
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error = bus_space_map(sc->acpi.base.res->r_bustag, paddr_rc,
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PCI_CFG_SPACE_SIZE, 0, &sc->n1_bsh);
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if (error != 0)
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goto out_pmap;
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@ -245,10 +245,10 @@ n1sdp_get_bus_space(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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return (EINVAL);
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*bsh = sc->n1_bsh;
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} else {
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*bsh = sc->acpi.base.bsh;
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*bsh = rman_get_bushandle(sc->acpi.base.res);
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}
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*bst = sc->acpi.base.bst;
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*bst = rman_get_bustag(sc->acpi.base.res);
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*offset = PCIE_ADDR_OFFSET(bus - sc->acpi.base.bus_start, slot, func,
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reg);
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@ -126,9 +126,6 @@ pci_host_generic_core_attach(device_t dev)
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}
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rman_set_mapping(sc->res, &map);
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#endif
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sc->bst = rman_get_bustag(sc->res);
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sc->bsh = rman_get_bushandle(sc->res);
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}
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sc->has_pmem = false;
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@ -233,8 +230,6 @@ generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, int bytes)
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{
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struct generic_pcie_core_softc *sc;
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bus_space_handle_t h;
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bus_space_tag_t t;
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uint64_t offset;
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uint32_t data;
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@ -248,18 +243,16 @@ generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
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return (~0U);
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offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
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t = sc->bst;
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h = sc->bsh;
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switch (bytes) {
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case 1:
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data = bus_space_read_1(t, h, offset);
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data = bus_read_1(sc->res, offset);
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break;
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case 2:
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data = le16toh(bus_space_read_2(t, h, offset));
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data = le16toh(bus_read_2(sc->res, offset));
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break;
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case 4:
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data = le32toh(bus_space_read_4(t, h, offset));
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data = le32toh(bus_read_4(sc->res, offset));
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break;
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default:
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return (~0U);
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@ -273,8 +266,6 @@ generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, uint32_t val, int bytes)
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{
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struct generic_pcie_core_softc *sc;
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bus_space_handle_t h;
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bus_space_tag_t t;
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uint64_t offset;
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sc = device_get_softc(dev);
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@ -286,18 +277,15 @@ generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
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offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
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t = sc->bst;
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h = sc->bsh;
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switch (bytes) {
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case 1:
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bus_space_write_1(t, h, offset, val);
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bus_write_1(sc->res, offset, val);
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break;
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case 2:
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bus_space_write_2(t, h, offset, htole16(val));
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bus_write_2(sc->res, offset, htole16(val));
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break;
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case 4:
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bus_space_write_4(t, h, offset, htole32(val));
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bus_write_4(sc->res, offset, htole32(val));
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break;
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default:
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return;
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@ -80,8 +80,6 @@ struct generic_pcie_core_softc {
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int bus_start;
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int bus_end;
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int ecam;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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device_t dev;
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bus_space_handle_t ioh;
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bus_dma_tag_t dmat;
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